KR100338626B1 - The Duplication Method for Communication system - Google Patents

Abstract

The present invention relates to a redundancy switching method between a first processor board and a second processor board in a communication system of a redundant structure including first and second processor boards each including communication processor modules. To this end, determining the first and second processor boards in an active and standby mode, respectively, initializing the communication processor modules in the first and second processor boards in the determined active and standby modes, and Storing, by the CPU in the first processor board in the active mode, data generated when the program is executed in a memory in the second processor board in the standby mode; and in the first processor board in the active mode, Determining whether a transfer condition occurs to the second processor board in the standby mode; when the transfer condition occurs, setting a transfer condition generation flag by a CPU in the first processor board in the active mode; After setting the condition flag, the first processor board Completing and disabling the functions being performed by the communication processor modules of the processor; setting a transfer interrupt instruction bit by a CPU in the first processor board in the active mode; and setting the first interrupt processor bit in the active mode. And a CPU in a board transferring a core register value indicating a program counter to the second processor board in the standby mode.

Description

Duplication Method for Communication System

The present invention relates to a communication system having a redundant processor device. In particular, when the processor device includes various communication processor modules as the performance is improved, the communication device in the processor board operating in an active mode in order to enable the processor device to operate quickly and stably when a reset, hernia, or alarm occurs. The present invention relates to a method for allowing modules to operate normally without disconnection of a call by switching to a processor board operating in a standby mode after completing and disabling a function being performed.

In general, when a problem occurs in one general board constituting a communication system, a great problem does not occur in service, but when a problem occurs in a main processor board device that controls the communication system as a whole, paralysis occurs in the whole service. Accordingly, in order to increase the stability of the communication system, the main processor board device adopts a redundant structure. This redundancy continues control of the communication system by performing redundancy switching from the active processor board to the standby board in the standby mode when an alarm or HALT occurs in the active board. To make it work.

1 is a block diagram of a redundant processor board in a general communication system. Referring to FIG. 1, the redundant processor boards include a first processor board 100 and a second processor board 200. The first processor board 100 includes a CPU 102, an address buffer 104, a data buffer 106, a dual port RAM (hereinafter referred to as DPRAM) 108, and the second processor. The board 200 is composed of a CPU 202, an address buffer 204, a data buffer 206, and a DPRAM 208.

The first processor board 100 and the second processor board 200 are set to an active mode or a standby mode according to the state of each board, etc., which may be redundantly switched. The first processor board 100 in the active mode during the redundancy switching stores application information, which is being performed using a communication memory, in the second processor board 200 operating in the standby mode using a bus. The communication memory becomes the DRAM 208 of the second processor board 200 when the first processor board 100 is set to the active mode, and the communication memory is set to the active mode when the second processor board 200 is set to the active mode. It becomes the DRAM 108 of the first processor board 100. Address buffers 104 and 204 and data buffers 106 and 206 for accessing the DRAMs 108 and 208 are occupied by the first processor board 100 operating in an active mode. The bus of the DRAM of the second processor board 200 operating in the standby mode is determined according to the selection signal STAND-BY DPRAM CS of the first processor board 100 operating in the active mode. That is, the DRAMs 108 and 208 open a path for each processor board operating in the active and standby modes to access the communication boards. In addition, although not shown in the drawings, in recent years, as the performance of the processor boards is improved, the processor boards perform functions of a communication processor module (hereinafter referred to as CPM), which is configured as a separate board and performs a communication function. Doing.

Functions corresponding to the CPM include an HD1 frame transmitting data through a serial port and an E1 / T1 frame using a local area network (LAN) and a time division multiplex (TDM) transmitting data through an Ethernet. Includes the QUICC Multichannel Controller (QMC), which transmits data through the serial port, and the SAR (Segmentation and Reassembly) function, which disassembles or assembles data units into cells in the asynchronous transfer mode (hereinafter referred to as ATM). .

However, as the processor boards additionally perform the CPM functions, redundancy switching is smoothly performed by transferring only the core register value of the first processor board operating in the active mode to the second processor board operating in the standby mode. I do not lose. That is, when a switching condition occurs in the first processor board in the active mode, the second processor board in the standby mode may not be able to process functions that were being performed in the CPM region in the first processor board. This is happening.

Accordingly, an object of the present invention is to complete and perform a function being performed by the communication processor module in a first processor board operating in an active mode in a redundant switching, when the redundant processor boards of the communication system include communication processor module functions. After enabling, the present invention provides a method for performing redundant switching to a second processor board operating in a standby mode.

In order to achieve the above object according to the present invention, in a redundant communication system having first and second processor boards each comprising a communication processor module, in the redundant switching method between the first processor board and the second processor board In

Determining the first and second processor boards in an active and standby mode, respectively;

Initializing the communication processor modules in the first and second processor boards in the determined active and standby modes;

Storing, by the CPU in the first processor board in the active mode, data generated when the program is executed in a memory in the second processor board in the standby mode;

Determining whether a switching condition occurs from the first processor board in the active mode to the second processor board in the standby mode;

Setting a transfer condition occurrence flag by a CPU in the first processor board in the active mode when the transfer condition occurs;

After setting the switching condition occurrence flag, completing and disabling a function that the communication processor modules in the first processor board are performing;

Setting a transfer interrupt command bit by a CPU in the first processor board in the active mode;

And transmitting, by the CPU in the first processor board in the active mode, the core register value representing the program counter to the second processor board in the standby mode.

1 is a block diagram of a conventional dual processor device

2 is a block diagram of a redundant processor device having a communication processor module;

3A and 3B are diagrams illustrating a method of operating a redundant switching operation of an active and standby board according to the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that the same reference numerals and the same elements among the drawings are represented by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a diagram illustrating a configuration of redundant processor boards according to an exemplary embodiment of the present invention. Referring to FIG. 2, the redundant processor boards may include a first processor board 300 and a second processor board 400. Since the configuration and operation of the first processor board 300 and the second processor board 400 are the same, only the configuration and operation of the first processor board 300 will be described below. First, the configuration of the first processor board 300 will be described. The CPU 302 in the first processor board 300 controls the overall communication system. The ROM 304 stores a boot program of the CPU 302, and the CPU 302 stores data generated when the boot program is executed in the DRAM 310. To this end, a self path is enabled, and the self path is composed of a data path and an address path, and the data path of the self path is composed of 'CPU 302-> first self buffer 306-> DRAM 310. The address path of the self path consists of 'CPU 302 → second self buffer 308 → DRAM 310'. In order to enable the self path, the CPU 302 outputs a buffer control signal for enabling the first self buffer 306 and the second self buffer 308 while the booting program is executed. Control to occur.

When the execution of the boot program is completed, the CPU 302 searches whether the first processor board 300 is initially determined to operate as an active mode processor board, and if so, performs an OS boot and application program. Data generated during execution is concurrently stored in the DRAM 310 and the DRAM 410 in the second processor board 400. For this purpose, a local path and a remote path are enabled, and the local path is composed of a data path and an address path, and the data path of the local path is' CPU 302 → first local buffer 314 → first remote buffer. 318? DPRAM 310, and the address path of the local path consists of the CPU 302, the second local buffer 316, the second remote buffer 320, and the DPRAM 310. To enable this local path, the CPU 302 buffers to enable the first and second remote buffers 318 and 320 and the first and second local buffers 314 and 316 while the first processor is operating in active mode. The control signal is controlled to generate the buffer control signal generator 312. The remote path includes a data path and an address path, and the data path of the remote path is' CPU 302 → first local buffer 314 → first remote buffer 418 of the second processor device 400. DPRAM 410 of the second processor device 400, and the address path of the remote path is' CPU 302 '→ the second local buffer 316 → the second remote of the second processor device 400'. Buffer 420 → DPRAM 410 'of the second processor device 400'. The CPU 402 in the second processor board 400 operating in the standby mode for enabling the remote path controls the buffer control signal generator to generate a buffer control signal for enabling the remote buffers.

Meanwhile, the CPM areas 337 and 437 in the processor boards 300 and 400 perform a function of processing data of the communication system. The CPM regions 337 and 437 generally use a HDLC 333 for transmitting data through a serial port and a LAN 334 for transmitting data through an Ethernet and a time division multiplexing (TDM) scheme. QMC 335 for transmitting E1 / T1 frame information through the serial port, and SAR 336 for disassembling or assembling data units in cell units in an asynchronous transmission mode (ATM) system.

When the first processor board 300 operating in the active mode as described above occurs in the following switching conditions of Table 2, the CPU 302 reads the switching condition state, and the magnetic board reset interrupt and the magnetic board alarm interrupt. Only when it is regarded as a transfer condition, the transfer condition occurrence flag is set and returned from the interrupt. When the transfer condition occurrence flag is set, the CPM completes the function that the CPM is performing in the redundant task of the first processor board operating in the returned active mode. Thereafter, each CPM is disabled and the transfer interrupt is generated again by setting the transfer interrupt command bit of the transfer condition state table of Table 1 described later. After that, the CPU 302 in the first processor board 300 operating in the active state in the interrupt state concurrently stores a core register value in the DRAMs 310 and 410 and then executes an interprocessor communication (IPC). A readiness ready signal is provided to read a core register value to the CPU 402 in the second processor board 400 operating in the standby mode. The core register value may be various flags indicating a current operation state, a program counter, various pointers, and the like. After providing the signal, the CPU 302 in the first processor board 300 disables the first local buffer 314 and the second local buffer 316 to disable the local path. Control the buffer control signal generation unit 312 to generate a.

On the other hand, when the first processor board 300 is initially set to operate in the standby mode after the CPU 302 completes the execution of the boot program, the CPU 402 in the second processor board 400 The remote path of the second processor board 400 is enabled to store data generated during the OS and application program execution of the DRAM 410 through the remote path. In order to enable the remote path of the second processor board 400, the CPU 302 may include a buffer control signal for enabling the first remote buffer 318 and the second remote buffer 320. 312 is controlled to occur. Here, the CPU 302 in the first processor board 300 operating in the standby mode operates in a state where only communication through IPC is possible without operating the OS.

The CPU 302 in the first processor board 300 operating in the standby mode as described above simultaneously checks information on the cause of the switching condition through the IPC when the redundant processor condition occurs in the second processor board 400. . Thereafter, the CPU 302 checks whether the transfer preparation completion signal is received through the IPC. When the transfer preparation completion signal for reading the core register value of the CPU 402 in the second processor board 400 stored concurrently from the second processor board 400 through the IPC is received, the first processor board ( According to the signal, the CPU 302 of the 300 includes the core register values stored in the DRAM 301 by the CPU 402 in the second processor board 400 and the CPU 402 in the second processor board 400. By using the data generated during the execution of the stored OS and application programs, the OS and application programs previously executed by the CPU 402 in the second processor board 400 are continuously executed. It also initializes the CPM so that it can also perform communication functions. As such, various data generated while executing the OS and application programs are concurrently stored, and the CPM function is executed again from the beginning.

As described above, the CPU 302 controls the buffer control signal generator 312 to enable the self path, the local path, and the remote path according to the state of the first processor board 300. That is, the CPU 302 controls the buffer control signal generator 312 to generate a signal for enabling the first and second self buffers 306 and 308 to enable the self path at boot time and to activate the self path. When operating in the mode, the buffer control signal generator 312 generates a signal for enabling the first and second local buffers 314 and 316 and the first and second remote buffers 318 and 320 to enable the local path. ), And when operating in the standby mode, the buffer control signal generator 312 generates a signal to enable only the first and second remote buffers 318 and 320 to enable the remote path by the counterpart device. ).

The signal check logic unit 322 detects and provides an alarm to the alarm logic unit 324 by checking the shape of a periodic waveform of a signal in hardware, and the alarm logic unit 324 provides a signal check logic unit. Upon receiving the alarm detection from 322, the alarm logic unit 324 may check whether it is an error state in software. In such a case, the alarm logic unit 324 provides the CPU 302 with an interrupt indicating an alarm. When the first processor board 300 is notified of an interrupt from the signal check logic unit 322 while the first processor board 300 is operating in an active mode, the CPU 302 sets a switching condition occurrence flag and returns from the interrupt state. The CPU 302 then completes the function that the CPM is performing and disables the CPM. When the CPU 302 sets the transfer interrupt command bit, the CPU 302 stores the core register values in the DRAM 310 and the DRAM 410 so that the second processor board 400 reads the core register values through the IPC. It provides a transfer ready signal. The CPU 302 then stops storing data generated in accordance with the execution of the OS and application programs. It then cleans up the task, reboots, and then runs as a standby mode processor. On the other hand, when the CPU 302 confirms that a switching condition has occurred in the second processor board 400 operating in the active mode through the IPC while the first processor board 300 operates in the standby mode, the second processor board 300 thereafter operates in the standby mode. It is checked whether the transfer preparation completion signal is received from the CPU 402 in the processor board 400. When the CPU 302 receives the transfer preparation completion signal, the first processor board 300 receives a core register value from the second processor board 400 and stores it in its register.

The refresh controller 330 receives the state information of the second processor board 400 through the buffer 328 and is responsible for refreshing the DRAM 310 while the second processor board 400 operates in the active mode. do. In addition, for the refresh operation of the DRAM 410 of the refresh control unit 430 in the second processor board 400, the CPU 302 stores its state information through the buffers 326 and 428 whenever an initial and redundant switching occurs. The refresh control unit 430 in the processor board 400 is provided.

In the above embodiment, the CPU directly handles the refresh of the DRAM when the processor operates in the active mode, and the refresh controller controls the refresh of the DRAM when the processor operates in the standby mode. In addition, the CPU of the partner device provides status information to the refresh controller so that the refresh controller can determine when the processor operates in standby mode. Alternatively, however, the CPU may load status information on the flag shown in Table 1 and provide the status information to the CPU of the counterpart device so that the refresh method of the DRAM can be selected according to the status information provided by the CPU. That is, when the CPU receives the state information of the counterpart device and the partner device is in the active mode, the CPU may refresh the DRAM through the refresh control unit. If the counterpart device is in the standby mode, the DRAM may directly refresh the DRAM.

In addition, since the timing of the refresh and the redundancy of the DRAM are asynchronous, it is necessary to refresh the DRAM even when performing the redundancy switchover so that information is not lost even when the redundancy is performed while leaving the time required for the refresh. desirable.

In addition, in the above embodiment, a refresh procedure is required as the DRAM is used. However, when the SRAM is used instead of the DRAM, the refresh may not be performed.

beat meaning One Active board status 2 Standby board status 3 Concurrent Light Enable 4 Current Light Enable Status 5 Transmission end signal 6 Status of transmission end signal 7 Board Position Identification Information 8 Relative board mounting information 9 Active state information of counterpart board 10 Standby status information of opponent's board 11 Alternate Interrupt Command

The operation of the first processor board 300 will now be described with reference to the process flow diagram shown in FIGS. 3A and 3B. When power is supplied to the communication system in operation 500 of FIG. 3A, the CPU 302 of the first processor board 300 performs initialization. That is, the CPU 302 reads and executes a boot program stored in the ROM 304 and stores data generated when the boot program is executed in the DRAM 310 through self-path. In addition, the CPU 302 may initialize IPC, which is a communication channel between the first processor board 300 and the second processor board 400 at the time of initialization. In addition, the CPU 302 may perform matching on a region where data is concurrently written in the DRAM 310 of the first processor board 300 and the DRAM 410 of the second processor board 400. . In operation 502, the CPU 302 searches whether the first processor board 300 is set to operate in an active mode after initialization. This setting uses the board position identification information (bit 7), the partner board unmounting information (bit 8), and the active state information (bit 9) of the counterpart board in the register shown in Table 1 to set the active and standby modes. After the determination, the active board operation state (bit 1) and the standby board operation state (bit 2) are set respectively. First, the case of using the opponent board mounting information (bit 8) will be described. When there is no partner board, that is, when there is no second processor board 400, the first processor board 300 is determined as an active mode. Here, the board position identification information (bit 7) is determined by the hardware so that the first processor board 300 is displayed as "0" and the second processor board 400 is displayed as "1", respectively. If there is a partner board, that is, if there is a second processor board 400, it is determined according to the state table of Table 3 described later. Referring to Table 3, when the second processor board 400 is in a non-none state and the board position identification information value is "0", the first processor board 300 determines an active mode. When the second processor board 400 is non-none and the board position identification information value is "1", the state of the second processor board 400 is read again after a predetermined time, for example, about 1 second, and is still non- None), the first processor board 300 is determined to be an active mode. However, if the state of the second processor board 400 is in an active mode after a certain time, the first processor board 300 is determined to be in a standby mode. At this time, if the first processor board 300 is determined to operate in the active mode after initialization, the CPU 302 initializes the CPM in step 504, performs an OS and an application program, and occurs during execution of the OS and an application program. The data is concurrently stored in the DRAMs 310 and 410 through the local path and the remote path. The CPU 302 is also responsible for refreshing the DRAM 310. The CPU 302 provides status information of the first processor board 300 to the refresh control unit 430 in the second processor board 400 as a counterpart device through the buffers 326 and 428 in step 506. The state information includes information indicating whether the first processor board 300 operates in an active mode or a standby mode.

The CPU 302 then detects in step 508 whether the signal check logic unit 322 detects an alarm and the alarm logic unit 324 generates an interrupt indicative of the alarm. That is, it is determined whether the switching interrupt of Table 2 has occurred.

Interrupt types are shown in Table 2.

Alternate Interrupt Type Explanation Relative Board Hernia Interrupt When the opponent board is dismounted from the shelf Relative Board Mount Interrupt When the opponent board is mounted on the shelf Partner Board Reset Interrupt When the opponent board is reset Partner Board Alarm Interrupt When the partner board has an alarm Magnetic Board Reset Interrupt When the magnetic board is reset Magnetic Board Alarm Interrupt When magnetic board alarm Alternate Command Interrupt When the transfer interrupt command bit of the magnetic board is set

Partner board active status information Partner board standby status information condition 0 0 You 0 One Standby One 0 active One One You

These interrupts may be notified to the CPU 302 via the alarm logic unit 324. If the alarm logic unit 324 generates a magnetic board alarm or reset interrupt among the interrupts in Table 2, the CPU 302 may perform a redundancy transfer from the active mode to the standby mode. To judge. When it is determined that duplication transfer is to be performed, the CPU 302 sets the transfer condition occurrence flag in step 510 and returns from the interrupt. On the other hand, other partner reset or unmounted interrupt manages the status of the partner board and exits the interrupt. When the transfer condition occurrence flag is set in step 510, the redundancy task of the first processor board operating in the active mode in step 512 completes the function performed by the CPM, and returns that allocated to the memory in the OS. Then, disable each CPM. In operation 514, the first processor board operating in the active mode sets the transfer interrupt command bits of Table 1 and determines whether the transfer interrupt command bits are set in operation 516. If the transfer interrupt command bit is set in step 516, the CPU 302 in the first processor board operating in the active mode in step 518 concurrently stores core register values in step 520. The transfer ready signal for reading the core register value is provided to the second processor board operating in the standby mode via IPC. In operation 522, the CPU 302 disables the first and second local buffers and enables the first and second self buffers to stop the concurrent storage. In step 524, the CPU 302 reboots the first processor board 300.

Meanwhile, when the first processor board 300 is set to the standby mode in step 502, step 526 of initializing the board is performed. The first processor board 300 set in the standby mode performs a step 528 of searching for a transfer condition by the CPU 402 in the second processor beam 400 operating in the active mode through the IPC. When the transfer condition occurs, the first processor board 300 operating in the standby mode searches for a transfer preparation completion signal received from the second processor board 400 operating in the active mode (530). Perform. When the first processor board 300 receives the transfer preparation completion signal in this step, the CPU 302 in the first processor board 300 receives the core register value transmitted from the second processor board 400. In step 532, the program stores the register in its register. Subsequently, the CPU 302 performs a control to initialize the CPM (534), and then performs a process (536) of switching the first processor board 300 to an active mode.

As described above, the present invention is characterized in that the CPU in the processor board operating in the active mode sets a switching condition occurrence flag when the processor board operating in the active mode among the redundant processor boards generates a redundancy switching condition due to a reset or an alarm. And return from the interrupt. The CPU then completes the function that the CPM is performing, disables each CPM, and then sets the transfer interrupt command bit. Then, the processor board operating in the standby mode is provided to the processor board operating in the standby mode by providing the core register values such as various pointers, flags, and program counters related to the program starting point. Allows the processor board running in active mode to continue running the operating system and application programs without restarting. In addition, after the CPM, which is in charge of the communication function, completes the function being performed and is disabled in the processor board operating in the active mode, the processor board in the standby mode is redundantly transferred. Therefore, by performing the redundancy switchover in this manner, the time required for the redundancy switchover is greatly reduced, and data transmission and reception can operate normally without disconnection of the call in the communication system.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. For example, the communication processor module may include modules other than those mentioned above. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention, in the communication system of a redundant structure including a communication processor module, in accordance with the trend of integration of communication equipment board includes a variety of complex functions and the like in the current processor board, unlike the conventional processor board, In particular, CPM modules such as HDLC, LAN, QMC, and SAR are used to provide a redundant light method. Therefore, in case of data loss or interruption, there is an advantage of minimizing service delay when switching by reset or failure and switching without call disconnection of subscriber.

Claims (8)

In a redundant communication system including first and second processor boards each including a communication processor module, in the redundant switching method between the first processor board and the second processor board, Determining the first and second processor boards in an active and standby mode, respectively; Initializing the communication processor modules in the first and second processor boards in the determined active and standby modes; Storing, by the CPU in the first processor board in the active mode, data generated when the program is executed in a memory in the second processor board in the standby mode; Determining whether a switching condition occurs from the first processor board in the active mode to the second processor board in the standby mode; Setting a transfer condition occurrence flag by a CPU in the first processor board in the active mode when the transfer condition occurs; After setting the switching condition occurrence flag, completing and disabling a function that the communication processor modules in the first processor board are performing; Setting a transfer interrupt command bit by a CPU in the first processor board in the active mode; The CPU in the first processor board in the active mode transferring a core register value indicating a program counter to the second processor board in the standby mode. The process of claim 1, wherein the first processor board in the active mode transmits the core register value to the second processor board in the standby mode, and notifies the second processor board of the transfer preparation completion signal. The method characterized in that it further comprises 2. The communication processor module of claim 1, wherein the communication processor module transmits E1 / T1 frame information through a serial port by using an HDLC for transmitting data through a serial port, a LAN for transmitting data through an Ethernet, and a time division scheme. The method comprising a QMC and a SAR for disassembling or assembling a data unit by cell in an asynchronous transmission method. The method as claimed in claim 1, wherein the transfer condition is a condition in which the board does not operate normally due to a reset or a failure of the first processor board in the active mode. 2. The method of claim 1, wherein the core register value of the first processor board in the active mode is transferred to the second processor board in the standby mode via a bus. The CPU of claim 1, wherein the CPU is booted when the first processor board is powered on, and the first processor board in the always active mode transfers the core register value to the second processor board in the standby mode. And further comprising the step of rebooting the first processor board. 2. The method of claim 1, wherein data generated when a CPU in the first processor in the active mode executes a program is stored concurrently in memory in the first processor board and in memory in the second processor board in the standby mode. The method characterized in that The method as claimed in claim 1, wherein the communication processor module includes a function of disassembling or assembling data units into cells in an asynchronous transmission method.