KR100336564B1 - Semiconductor memory - Google Patents

Abstract

The present invention relates to a semiconductor memory that can maintain a conventional high speed operation speed for a good-quality memory that does not require repair, and solves a functional malfunction problem that may occur when a redundant scheme is applied.

To this end, the semiconductor memory of the present invention comprises a memory cell array having normal cells and redundant cells; A control unit which receives external control signals and controls the operation of each component; An address input buffer unit for receiving and buffering an address signal applied from the outside; A pre-decoding unit pre-decoding the address value output from the address input buffer unit; An address comparison section for comparing whether or not an address value output from the address input buffer section is an address of a redundant cell; A redundancy determination unit for outputting a low or high redundancy determination signal according to a logic level of an output signal of the address comparison unit; A transition detector for generating a transition pulse of a predetermined length when the logic level of the redundant determination signal changes; A pulse generator for periodically generating a pulse signal having a predetermined length in accordance with a selection clock applied from a controller, and delaying and outputting the pulse signal by a length of a transition pulse; According to the logic level of the redundant determination signal, the address of the redundant cell and the address of the normal cell are divided, and the address value outputted from the pre-decoding unit is received and decoded, and the select line of the corresponding memory cell is output to the pulse signal output from the pulse generator. It is made by including a decoding unit to be activated by,

Accordingly, by detecting the level shift of the redundant determination signal and outputting the delayed pulse signal generated by the pulse generator at this time, the functional malfunction that may occur during the operation of the redundant mode while maintaining the access timing in the normal mode operation is maintained. There is an effect that can prevent.

Description

Semiconductor memory

The present invention relates to an access operation (Redundant Scheme) for the extra memory cells in the semiconductor memory, in particular, to maintain the conventional high-speed operation speed as the original good die (Repair Good) that does not require repair (Repair) The present invention relates to a semiconductor memory that solves a functional failure problem that may occur when a redundant scheme is applied.

In general, any one of a number of fine cells (memory cell) is a defect because it can not be used as a memory compartment as a memory. However, as memory density increases, the probability of defects in a small number of cells increases. Nevertheless, discarding it as a defective product is an inefficient treatment method that lowers the yield of the good.

Therefore, in this case, the yield of memory production is increased by installing a redundancy cell in the memory in advance and replacing the defective cell using the redundancy cell.

Redundancy cells of a semiconductor memory are usually provided for each sub-array block of the memory, and usually, extra row address lines and column address lines are provided for each cell array at regular intervals. The method of pre-installing and replacing a defective memory cell with a defective cell in a row / column unit is mainly used.

When the semiconductor memory manufacturing process on the wafer is completed, a programming is performed in the internal circuit that selects a defective memory cell through a test and replaces the corresponding address with an address signal corresponding to a spare cell. When the address is input, the selection is changed to a spare line instead.

Such a program method includes an electric fuse method that melts and blows a fuse due to overcurrent, a method that burns a fuse with a laser beam, and a program that uses an EPROM cell.

In addition, a programming method for replacing a bad column or row address line with an extra line includes a physical method and a logical method.

Among them, the physical method is to fuse the output terminal of each address line and the decoder of the extra line to completely isolate the bad word line from the remaining memory circuit. In this method, the selection line of the bad cell is the extra cell. Although it is replaced by a 1: 1 selection line for the operation, the layout of the redundancy circuit that must be provided for this is not suitable for the highly integrated memory. Therefore, a logic method of inserting a fuse in the decoder circuit to deactivate the decoder corresponding to the defective line at the decoder level is mainly used.

1 is a circuit diagram showing an example of a basic redundancy circuit of a semiconductor memory.

The circuit shown in FIG. 1 generates a signal NRD for disabling the normal normal decoder 22 when the addresses A0 to An corresponding to the bad word lines are input, thereby preventing the normal word lines from operating. Logical redundancy circuit that controls only the spare word line (Spare WL) to operate.

In this circuit, the extra word lines and the extra decoder 11 connected thereto are installed so that the extra decoder 11 can be freely programmed.

Thereafter, the fuse of the redundant decoder is blown to match the address decoder logic of the word line. During operation, if a normal address (A0 to An) is input, rather than a spare address generated as a repair, one or more of the nMOSs connected in parallel through the fuse are turned on to make the NRD 'low' but the bad line When the corresponding addresses A0 to An are input, the fuses are all cut off, and the discharge path is blocked. Therefore, the NRD becomes 'high' and the output node of the normal word line decoder 22 is discharged and disabled. . After that, a high voltage pulse is applied to the RX2 terminal to output a pulse on an extra word line. Since the normal decoder 22 is deselected by the NRD signal generated by the determination result of the address comparison circuit that determines whether or not the input addresses A0 to An are selected, the access time is determined by the determination time in the comparison circuit. Loss of time will occur.

Fig. 2 is a block diagram showing the configuration of a conventional semiconductor memory having a logical redundancy circuit.

In the semiconductor memory shown in Fig. 2, the memory cell array 10 is composed of normal normal cells and redundant cells (hereinafter referred to as 'redundant cells'), which are selected by the row decoder 20 and the column decoder 30. / Is activated.

The row and column decoders 20 and 30 may be configured to distinguish between normal cells and redundant cells among memory cells.

That is, YSELn of the column decoder 30 is a column select line connected to the normal cell, and YSELr is a column select line connected to the redundant cell.

Since the fundamental memory access operations of the row decoder 20 and the column decoder 30 are identical to each other, the configuration and operation of the semiconductor memory will be described below with reference to the column address, and the description of the configuration and operation related to the row address will be omitted.

The controller 40 receives control signals such as CLK, CKE, / RAS, / CAS, CS, DQM, and / WE from the outside to generate signals necessary for internally controlling all blocks of the semiconductor memory.

The address input buffer 50 receives the SIB signal generated by the controller 40, latches and buffers an address input from the outside.

The predecoder 60 receives the SPD signal generated by the controller 40, latches the output CA of the address input buffer 50, and predecodes it.

The address comparison unit 70 receives an output CA of the address input buffer 50, compares whether the value A of the input address is an address of a bad cell or an address of a normal cell, and compares the result with a redundant plate. Output to the government 80. It is common to have a plurality of such address comparison units 70 in a semiconductor memory circuit. The address comparison unit 70 may vary depending on the number of select lines YSELr of a redundant cell.

The redundant determination unit 80 receives the output signal HM of the address comparison unit 70 and generates redundant determination signals Sn and Sr for distinguishing whether the current operation is the normal mode or the redundant mode operation. Output

The selection lines YSELn and YSELr of the memory cells are generally controlled in the form of pulses to reduce power consumption during activation. At this time, the pulse signal Sp1 is generated by the pulse generator 90.

The pulse generator 90 receives a selection clock CLKysel applied from the controller 40 and generates a pulse signal Sp1 required to activate the selection lines YSELn and YSELr.

Finally, the column decoder 30 receives and decodes the output signal PCA of the predecoder 60 and selects the selected line YSELn or YSELr using the pulse signal Sp1 input from the pulse generator 90. Activate

3 is a timing diagram showing waveforms of input / output signals for explaining the operation of the conventional semiconductor memory described above.

As shown in Fig. 3, when the address Ai corresponding to the redundant cell and the address Aj corresponding to the normal cell are input from the outside, the address input buffer section 50 latches this signal A. And buffer and output (CA: Valid1, Valid2).

The predecoding unit 60 receives the signal CA and predecodes it to output it.

The address comparison unit 70 receives the outputs Valid1 and Valid2 of the address input buffer unit 50 and determines whether the address corresponds to a redundant cell. That is, when the address corresponds to a redundant cell, a signal having a 'high' level is output, and when the address corresponds to a normal cell, a 'low' level signal is output (HM).

The redundant determination unit 80 receives the output signal HM of the address comparison unit 70, and outputs the redundant determination signals Sr and Sn to the column decoder 30. That is, when the HM signal is' high ', the Sr signal is output' high 'and the Sn signal is output' low '. When the HM signal is' low', the Sr signal is' low 'and the Sn signal is' Outputs high.

The control unit 40 generates the selection clock CLKysel based on the external clock CLK input from the outside, and the pulse generator 90 receiving the input signal pulses Sp1 required to activate the selection lines YSELn and YSELr. Will generate).

The column decoder 30 selects YSELr and YSELn according to the levels of the Sr and Sn signals, receives and decodes the address value PCA output from the predecoder 60, and decodes the corresponding select line by the pulse signal Sp1. Will be activated.

However, in the prior art, it does not have the timing margin of the part shown by the round circle in FIG. That is, there is no timing margin between the redundant determination signals Sr and Sn and the pulse signal Sp1, which may cause a functional malfunction. This is because the path through the redundant determination unit 80 is longer than the path through the predecoder 60. Therefore, in order to prevent such a malfunction, it is necessary to adjust the timing of generating the pulse signal Sp1 based on the redundant determination signals Sr and Sn, as shown in FIG. This can be solved by delaying the timing of the generation of the pulse signal Sp1. However, since the generation of the pulse signal Sp1 is delayed even when the normal cell is accessed, the operation timing of the entire memory is delayed. There is a problem that the timing margin at the time of writing is reduced.

A problem in the operation of the conventional semiconductor memory will be described with reference to FIG. 4 as follows.

As shown in FIG. 4, when the input address is applied in the order of a normal cell, a normal cell, a redundant cell, and a normal cell, the redundant determination signals Sr and Sn are 'low' and 'high' respectively when the normal normal cell is accessed. Is applied. However, when the redundant cell is accessed, the Sr and Sn signals transition to become 'high' and 'low', respectively. As described above, when the redundant determination signals Sr and Sn transition, the redundant determination signals Sr and Sn become later than the timing of the generation of the pulse signal Sp1, thereby causing a functional malfunction in the portion shown by the circle of FIG. There is a problem that occurs, such a problem occurs when the normal cell is accessed after the redundant cell.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and is configured to detect the level shift of the redundant determination signal and output the delayed pulse signal generated at the pulse generator at this time, thereby accessing in normal mode operation. It is an object of the present invention to provide a semiconductor memory circuit capable of preventing functional malfunctions that may occur when operating in redundant mode while maintaining the timing.

The present invention for achieving the above object is a memory cell array having a normal cell and a redundant cell; A controller which receives a clock and external control signals related to the operation of the semiconductor memory and generates predetermined control signals and a selection clock for controlling the operation of each component; An address input buffer unit which receives an address signal input from the outside, latches, buffers and outputs the address signal; A pre-decoding unit which receives an address value output from the address input buffer unit and pre-decodes the output value; An address comparison unit which receives an address value output from the address input buffer unit, compares whether the input address value is an address of a redundant cell, and outputs a result; A redundant determination unit which receives an output signal of the address comparison unit, determines whether the input address value is an address of a redundant cell or an address of a normal cell, and accordingly outputs a 'low' or 'high' redundant determination signal; A transition detector for receiving a redundant determination signal output from the redundant determination unit and generating a transition pulse of a predetermined length when a logic level of the redundant determination signal changes; A pulse generator which receives a selection clock applied from a controller and periodically generates a pulse signal having a predetermined length, and delays and outputs the pulse signal by the length of the transition pulse when a transition pulse is generated from the transition detector; According to the logic level of the redundant determination signal output from the redundant determination unit, the address of the redundant cell and the address of the normal cell are distinguished and received and decoded from the address value output from the predecoding unit, and the selected line of the corresponding memory cell is pulsed. And a decoding unit to be activated by the pulse signal output from the unit.

1 is a circuit diagram showing an example of a basic redundancy circuit of a semiconductor memory.

2 is a block diagram showing the structure of a conventional semiconductor memory;

3 is a timing diagram showing waveforms of input / output signals during operation of a conventional semiconductor memory;

4 is a timing diagram for explaining a problem in the operation of the conventional semiconductor memory.

5 is a block diagram showing the configuration of a semiconductor memory according to the present invention;

6 is a timing diagram of each input / output signal waveform shown for explaining the operation of the semiconductor memory according to the present invention;

Fig. 7 is a timing diagram showing each input / output signal waveform of the present invention with yet another configuration.

Explanation of symbols on the main parts of the drawings

1: memory cell array 2: control unit

3: address input buffer section 4: pre-decoding section

5: address comparison unit 6: redundant determination unit

7: transition detector 8: pulse generator

9: decoding unit

Hereinafter, with reference to the accompanying Figures 5 to 7 will be described the technical configuration and operation of the present invention.

5 is a block diagram showing the configuration of a semiconductor memory according to the present invention.

A semiconductor memory according to the present invention includes a memory cell array 1 having a normal cell and a redundant cell; Predetermined control signals SIB for receiving the clock CLK and external control signals CKE, / RAS, / CAS, CS, DQM, / WE, etc. related to the operation of the semiconductor memory to control the operation of each component. And a control unit 2 for generating a selection clock CLKysel; An address input buffer unit 3 which receives an address signal A input from the outside, latches, buffers and outputs the address signal A; A pre-decoding unit 4 for receiving an address value CA output from the address input buffer unit 3 and pre-decoding and outputting it; An address comparison section 5 which receives an address value PCA output from the address input buffer section 4, compares whether or not the input address value A is an address of a redundant cell, and outputs the result; The output signal HM of the address comparison unit 5 is input to determine whether the input address value A is an address of a redundant cell or an address of a normal cell, and accordingly, a redundancy determination of 'low' or 'high' is performed. A redundant determining unit 6 for outputting signals Sr and Sn; Transition detection unit 7 which receives the redundant determination signals Sr and Sn output from the redundant determination unit 6 and generates a transition pulse St of a predetermined length when the logic level of the redundant determination signals Sr and Sn changes. )Wow; Generates a pulse signal Sp2 of a predetermined length periodically by receiving the selection clock CLKysel applied from the control unit 2, and when the transition pulse St is generated from the transition detection unit 7, A pulse generator 8 for delaying and outputting the pulse signal Sp2 by a length; The address of the redundant cell and the address of the normal cell are classified according to the logic levels of the redundant determination signals Sr and Sn output from the redundant determination unit 6, and the address value PCA output from the predecoding unit 4 is output. And a decoding unit 9 which receives and decodes and activates the selection lines YSELn and YSELr of the corresponding memory cell by the pulse signal Sp2 output from the pulse generating unit 8.

In the block diagram of the present invention shown in FIG. 5, the configuration related to the decoding of the row address is omitted. Since the fundamental memory access operations of the row decoder and the column decoder are the same, the structure and operation of the semiconductor memory according to the present invention will be described below with reference to the column address.

The difference between the semiconductor memory according to the present invention and the conventional semiconductor memory shown in FIG. 2 is that the transition detector 7 detects the level transition of the redundant determination signals Sr and Sn, which are output signals of the redundant determination unit 6. It is further provided that the operation of the pulse generator 8 is controlled by the output signal of the transition detection unit (7).

That is, the rest of the components of the present invention except for the transition detector 7 and the pulse generator 8 are the same as those of the prior art shown in FIG. 2 and therefore, the transition detector 7 and the pulse generator 8 will be described below. The operation of the semiconductor memory according to the present invention will now be described.

The transition detection unit 7 of the present invention receives the redundant determination signals Sr and Sn output from the redundant determination unit 6. In response to the change of the logic level of the redundant determination signals Sr and Sn, a transition pulse St having a short pulse width is generated.

Then, the pulse generator 8 of the present invention is made to be slightly controlled by the transition pulse St output from the transition detector 7.

That is, the pulse generator 90 according to the related art performs a function of periodically generating a pulse signal Sp1 having a predetermined length periodically by the selection clock CLKysel output from the controller. 8 periodically generates a pulse signal Sp2 of a predetermined length by the selection clock CLKysel output from the controller 2, and in the case where the transition pulse St is input from the transition detection unit 7, The output time of Sp2) is delayed by the pulse width of the transition pulse St.

Therefore, the transition detector 7 generates a transition pulse St only when there is a level transition of the redundant determination signals Sr and Sn, so that only the access to the normal cell is repeated or only the access to the redundant cell is repeated. If so, the pulse generator 8 of the present invention generates the pulse signal Sp2 at regular intervals, thereby maintaining the existing high speed operation speed.

6 is a timing diagram of each input / output signal waveform shown for explaining the operation of the semiconductor memory according to the present invention. Here, both are shown to clearly distinguish the difference between the pulse signal Sp1 output from the conventional pulse generator 90 and the pulse signal Sp2 output from the pulse generator 8 according to the present invention.

As shown in Fig. 6, when the input address is applied in the order of normal cells, normal cells, redundant cells, and normal cells, the redundant determination signals Sr and Sn output from the redundant determination unit 6 indicate normal normal cells. In the case of accessing, the low and high voltages are respectively applied. Subsequently, when the redundant cells are accessed, the logic levels of the redundant determination signals Sr and Sn transition to the high and low levels, respectively. However, in this case, the transitioned redundant determination signals Sr and Sn are applied later than the timing of the generation of the pulse signal Sp1 which is periodically generated due to the delay of the circuit itself.

That is, the transition of the redundant determination signals Sr and Sn is later than the timing of the generation of the pulse signal Sp1 of the prior art, and the decoding unit recognizes the input address as the address of the normal cell at the portion indicated by the circle of FIG. It may cause malfunction.

However, in the memory semiconductor of the present invention, the transition detection unit 7 detects the level transition of the redundant determination signals Sr and Sn so as to generate a transition pulse St having a short pulse width as shown in FIG. As a result, the pulse generator 8 of the present invention operates to generate the pulse signal Sp2 after the transition pulse St is applied.

In the internal view of the semiconductor memory, the data line corresponds to a section where the data line is equalized and precharged during the transition pulse St. Thus, the configuration and operation described above have the following effects. You can expect

In the redundant scheme of the semiconductor memory according to the present invention, a short pulse St is generated by detecting the level shift of the redundant determination signals Sr and Sn, and the generation time of the pulse signal Sp is used as a transition pulse St. By delaying the width by, the timing margin problem that can occur in redundant mode access operation can be solved.

In addition, it is possible to expect the effects of the present invention as described above by changing the functional configuration of the pulse generator (8).

As shown in Fig. 7, even when the pulse generator 8 of the present invention is configured to extend the pulse signal Sp3 while the transition pulse St is applied, the same effects as described above can be obtained. .

As described above, the semiconductor memory according to the present invention further includes a transition detection unit for detecting a level transition of the redundant determination signal and generating a pulse having a predetermined length, so as to generate a pulse signal generated by the pulse generator by the length of the pulse. By configuring the delayed output, the normal mode operation has the effect of preventing the functional malfunction that may occur during the redundant mode operation while maintaining the access timing.

Claims (2)

A memory cell array having normal cells and redundant cells; A controller which receives a clock and external control signals related to the operation of the semiconductor memory and generates predetermined control signals and a selection clock for controlling the operation of each component; An address input buffer unit which receives an address input from the outside and latches, buffers, and outputs the buffer according to a control signal of the controller; A pre-decoding unit which receives the address value output from the address input buffer unit and pre-decodes the output signal according to the control signal of the controller; An address comparison unit which receives an address value output from the address input buffer unit, compares whether the input address value is an address of a redundant cell, and outputs a result; A redundant determination unit which receives the output signal of the address comparison unit, determines whether the input address value is an address of a redundant cell or an address of a normal cell, and accordingly outputs a low or high redundant determination signal; A transition detection unit which receives a redundant determination signal output from the redundant determination unit and generates a transition pulse of a predetermined length when a logic level of the redundant determination signal changes; A pulse generator for receiving a selection clock applied from the controller and periodically generating a pulse signal having a predetermined length, and delaying and outputting the pulse signal by the length of the transition pulse when a transition pulse is generated from the transition detector; The address of the redundant cell and the address of the normal cell are classified according to the logic level of the redundant determination signal output from the redundant determination unit, and received and decoded the address value output from the predecoding unit, and the corresponding memory of the memory cell array. And a decoding unit for activating a selection line of a cell by a pulse signal output from the pulse generator. The method according to claim 1, The pulse generator generates a pulse signal having a predetermined length periodically by receiving the selection clock applied from the controller, and when the transition pulse is generated from the transition detector, extends the pulse signal by the length of the transition pulse and outputs the pulse signal. It is characterized by a semiconductor memory.