KR100334125B1 - Digital frequency synthesizer with enhanced frequency spectrum - Google Patents

Abstract

A digital frequency synthesizer with improved frequency spectrum characteristics is disclosed. In order to ensure that the sample value does not fall out and that the value does not change suddenly, the symmetry is used by changing the value of sin signal 0 of the lookup table memory to a sin 45 degree value rather than 0. If you need to use the sample values of the zero address lookup table of sine and cosine, use logic circuit to externally assign zero for sine and 1 for cosine. . Configuring the digital frequency synthesizer in this way adds a bit of logic circuitry, but it can improve frequency spectrum characteristics by reducing spurious noise.

Description

Digital Frequency Synthesizer with Improved Frequency Spectrum Characteristics {DIGITAL FREQUENCY SYNTHESIZER WITH ENHANCED FREQUENCY SPECTRUM}

FIELD OF THE INVENTION The present invention relates to digital communications, and more particularly to digital frequency synthesizers with improved frequency spectrum characteristics.

Digital frequency synthesizers are used in various applications in digital communications. Characteristics required include wide frequency bandwidth, high frequency resolution, fast switching speed, and good frequency spectrum characteristics.

The modulator / demodulator of the communication modem includes a frequency synthesizer. The phase locked loop method, which has been used for a long time in frequency synthesizers, has a low spurious noise, but the disadvantage is that the higher the frequency resolution, the higher the phase noise and the slower the switching speed to the new frequency. Compensating this disadvantage is the Numerically Controlled Oscillator (NCO), which is a direct digital synthesis method. This approach provides a low cost, high frequency resolution, fast switching speed, and high phase noise. In addition, since the required clock speed is fast, power consumption is increased. Therefore, it is important to increase the clock speed while getting low power to obtain a wide frequency bandwidth.

1 shows an NCO block diagram and signal flow. The input frequency control word (hereinafter referred to as 'FCW') adjusts the output frequency, and accumulates in the j-bit phase accumulator 10 and overflows, resulting in a 2 ^j module operation. The output phase of the phase accumulator 10 corresponds to the magnitude of the sine signal stored in the lookup table 20, outputs the magnitude corresponding to the phase, and passes through the digital / analog converter 30 and the filter 40. Finally an analog signal is produced.

Since the lookup table 20 is implemented in ROM, the size of the lookup table 20 should be minimized in order to reduce complexity and speed up memory access time. Equation (1) below determines the output frequency of the NCO, and Equation (2) shows the frequency resolution.

f _out = FCW f _clk / 2 ^j

Δf = f _clk / 2 ^j

Therefore, to increase the bandwidth of the output frequency f _out , the clock frequency f _clk must be increased, and to increase the frequency resolution, the number of bits of the phase accumulator 10 must be increased. The output frequency of the NCO can be up to 50% of the clock frequency, but since the filtering is difficult, the output frequency is actually limited to about 40%.

Since most of the actual NCO block is occupied by the ROM, it is effective to reduce the size of the lookup table 20 as much as possible. There are also ways to implement an NCO using a 90 degree lookup table, but using a 45 degree lookup table can significantly reduce the amount of hardware. That is, the magnitude information of 0 to 45 degrees of the sine signal and the magnitude information of 0 to 45 degrees of the cosine signal are stored in the look-up table 20 and used to generate a full 360 degree signal.

2 shows a method of generating a sine signal and a cosine signal. In the case of a sine signal, samples of the A and C regions are stored in a lookup table, and samples of the remaining regions can be obtained using symmetry and inverting properties. Among the N bit outputs of the phase accumulator 10, the most significant three bits p [N-1, N-2, N-3] are used to divide each area and mirror or invert the contents of the lookup table. Decide if you want to Symmetry is determined by p [N-3] and inverting is determined by p [N-1]. The A, D, E and H regions use sine lookup tables, and the B, C, F and G regions use cosine lookup tables. This is determined by the exclusive-OR of p [N-2] and p [N-3].

In the case of the cosine signal, the symmetry is the same as the sine and the inverting is determined by the exclusive-OR of p [N-1] and p [N-2]. The A, D, E and H regions use cosine lookup tables and the B, C, F and G regions use sine lookup tables. This is also determined by the exclusive-OR of p [N-2] and p [N-3].

When implementing NCO, a digital frequency synthesizer, the sine cosine lookup table stores the contents from 0 to 45 degrees because of the effect of reducing the size of the ROM that implements the lookup table. The way of expressing is commonly used. p [N-1], p [N-2], and p [N-3] serve to distinguish each area and accordingly mirror the contents of the lookup table or invert the sign. ).

FIG. 3 illustrates the sine signal in detail. In the method of implementing NCO using symmetry based on the x point, the sample of the middle portion of the sinusoid indicated by the white circle is dropped, resulting in discontinuity of the signal resulting in an increase in spurious noise. There is a problem coming. The reason for the discontinuity is that the actual sine lookup table is provided only for the 0 degrees to 44 degrees phase of the 1/8 upper limit 50a, and the cosine lookup table is also 90 to 134 degrees phase of the 3/8 upper limit 50b. This is because it is provided only for. That is, the data about 45 degrees and 135 degrees are not provided in the lookup table because the collision between the mirroring and the inverting occurs.

Thus, as in the conventional method illustrated in FIG. 4, if the position of the symmetric point x is changed, the problem of missing the sample due to perfect symmetry can be solved. However, the phenomenon that the value suddenly changes around 45 degrees and 135 degrees appears. Therefore, between 1/8 upper limit 60a and 2/8 upper limit 60b, between 3/8 upper limit 60c and 4/8 upper limit 60d, 5/8 upper limit 60e and 6/8 upper limit (60f). ) And between 7/8 upper limit (60g) and 8/8 upper limit (60h), a sudden change in the sampling function value occurs, which adversely affects the frequency spectrum characteristics. The performance criterion for NCO, a direct digital synthesis method, is the amount of spurious noise. If the sample is dropped in the middle of the sine wave, the result is an increase in the spurious noise in the frequency spectrum.

An object of the present invention is to provide an NCO that can improve the frequency spectrum characteristics of the NCO by reducing spurious noise by modifying the contents of the lookup table so that there are no missing or sudden changes of samples.

Figure 1 shows a block diagram showing the configuration of a numerically controlled oscillator (NCO) with signal flow.

FIG. 2 is a diagram for describing a method of generating sine and cosine signals using mirroring and inverting by dividing a 360 degree phase into eight upper limits.

FIG. 3 is a diagram for explaining a conventional method of generating a sinusoidal signal having a problem that signal discontinuity occurs due to incomplete symmetry.

4 is a diagram illustrating a conventional sinusoidal signal generating method having a problem of generating spurious noise due to a sudden change section of a sample value.

5 is a view for explaining a sign signal generating method according to the present invention.

6 is a circuit diagram showing the configuration of an NCO according to the present invention.

<Description of the code for the main part>

10: phase accumulator 20: lookup table

30: D / A converter 40: filter

100: frequency control word 102: adder

104: Phase accumulator 106, 128, 130: 2's complement generator

116: Zero Commission, 112: Sign Lookup Table

114: cosine lookup table 108, 124, 126, 134, 136: multiplexer

In order to achieve the above object, ^2N module operation is performed while accumulating the phase of the frequency control word (FCW), and the 360 degree phase is sine, cosine_mirror, cosine, sine_mirror, sine_inversion, cosine_ It is divided into eight upper limits of mirror_inversion, cosine_inversion, sine_mirror_inversion, and the upper limit data is used to designate the upper limit of t bit, and the Mt as 0t ~ 45 degree phase data. Phase accumulation means for outputting a bit; The first selection data for distinguishing the upper limit of the mirroring and the non-mirror upper limit, the second selection data for distinguishing the upper bound of the sine and the upper limit of the cosine using the upper limit data of the t bits, the upper limit related to the inverting and the non-inverting related to the sine. Selection data generating means for generating third selection data for distinguishing an upper limit and fourth selection data for distinguishing an upper limit related to inverting and a non-inverting upper limit relating to cosine; First maintenance generating means for receiving the phase data output from the phase accumulation means and generating and outputting two's complement data for the phase data; First selection means for receiving the phase data outputted from the phase accumulation means and the complementary data outputted from the first reward generating means in parallel and selectively outputting only one designated by the first selection data; The first selection means for storing a value of sin π / 4 as a value corresponding to 0 degrees and storing a sine function value sin x as a value corresponding to a phase x between 0 <x <π / 4, A sine lookup table for outputting a sine function value corresponding to the phase indicated by the output value of the sine function; Storing the value of cos π / 4 as a value corresponding to 0 degrees and storing a cosine function value cos x as a value corresponding to a phase x between 0 <x <π / 4, the first output means being applied to an input terminal A cosine lookup table for outputting a cosine function value corresponding to the phase indicated by the output value of the cosine; The output value of the sine lookup table and the output value of the cosine lookup table are respectively inputted through separate input stages and output separately through the first output stage and the second output stage, respectively, corresponding to zero phase of the sine lookup table and the cosine lookup table. A zero-phase processing means for coercing an output value of the sine lookup table to 0 and outputting it to a first output stage, and forcing the output value of the cosine lookup table to a second output stage; Second selection means for separately receiving a sine function value and a cosine function value output from the zero phase processing means in response to the second selection data and selectively outputting one of the sine function value and the cosine function value; Third selecting means for separately receiving a sine function value and a cosine function value output from the zero phase processing means and selectively outputting the other one not selected by the second selecting means in response to the second selection data; Second reward generating means for generating a two's complement of the output value of the second selecting means; Third reward generating means for generating a two's complement of the output value of the third selecting means; Fourth selecting means for selectively outputting any one of an output value of the second selecting means and an output value of the second maintenance generating means in response to the third selection data; And fifth selecting means for selectively outputting any one of an output value of the third selecting means and an output value of the third maintenance generating means in response to the fourth selection data. .

Preferred configurations and various embodiments of the invention will be more clearly understood from the description of the claims and the following detailed description.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

For spurious noise to be small, the change in the value of the digital sample must be similar to the shape of the original analog signal. Accordingly, as shown in FIG. 5, the zero phase sign value of the lookup table memory, that is, the initial phase value of the 1/8 upper limit 70a and the cosine signal zero value value, that is, the initial phase value of the 3/8 upper limit 70c are set to 0 ( If you change the value to sin 45 degrees (shown as a black circle in the figure) instead of a white circle in the figure, the sample does not drop out and the value does not change suddenly when using symmetry.

In addition, samples of the zero address lookup table of the sine and cosine, that is, the 1/8 upper limit 70a, the 3/8 upper limit 70c, and the 5/8 upper limit as indicated by the white circles in FIG. If you need to use a function value corresponding to the zero phase of 70e and 7/8 upper limit (70g), use logic circuit to externally give zero for sine and maximum for cosine. Force a value of 1. This method adds a bit of logic circuitry, but it can improve frequency spectrum characteristics by reducing spurious noise.

6 shows a circuit configuration of an NCO according to a preferred embodiment of the present invention. The NCO is mainly composed of phase accumulation means 200, selection signal generation means 210, phase mirroring means 220, sine and cosine lookup tables 112 and 114, zero phase processing means 230, path switching means 240 And first and second inverting processing means (250, 260).

The phase accumulating means 200 has a frequency control word part 100, an adder 102 and a phase accumulator 104. The adder 102 adds the N-bit control word provided by the frequency control word unit 100 and the N-bit phase data fed back from the phase accumulator 104 to provide it to the phase accumulator 104. The N-bit phase data provided from the adder 102 accumulates in the phase accumulator 104 and becomes a ^2N module operation when an overflow occurs.

Of the N bits of data generated as a result of this operation, M bits are used as input data for generating sine and cosine function values. The upper limit data P [N-1: N-3] of the most significant three bits of the M bit data is input to the selection signal generating means 210, and the phase data P [N-4: NM] of the remaining M-3 bits is phase mirrored. Provided by means 220.

The selection signal generation means 210 includes two exclusive-or gates (Ex-OR). The first exclusive-orgate 110 performs an exclusive OR operation on two bits of P [N-2] and P [N-3], and the second exclusive-orgate 132 is P Perform an exclusive OR operation on two bits, [N-1] and P [N-2].

Phase mirroring means 220 is a two's complement 106 for generating a complement to two of the phase data P [N-4: NM], and the phase data P [N-4: NM] input phase of logic 0 And a 2x1 multiplexer 108 which receives the output of the two's complementer 106 through the input of logic 1 and outputs any one according to the value of the P [N-3] bit data. As shown in Fig. 5, the phase data P [N-4: N-M] and its complement to two are in a symmetrical relationship. When P [N-3] bit data has a value of 1, it corresponds to selecting upper limits 70b, 70d, 70f, and 70h to be mirrored from a total of eight upper limits, and having a value of 0. Corresponds to selecting the non-mirror related upper limits 70a, 70c, 70e, 70g.

The phase data selected by the multiplexer 108 is input not only to the sine lookup table 112 but also to the cosine lookup table 114. The sine and cosine lookup tables 112 and 114 are implemented in ROM. The sine lookup table 112 stores the sine function value sin x as a value corresponding to phase x between 0 <x <π / 4, but does not store the value of sin 0 as a function value corresponding to phase 0 degrees. Store the value of sin π / 4. Similarly, the cosine lookup table 114 stores the cosine function cos x as a value corresponding to phase x between 0 <x <π / 4, but stores the value of cos 0 as a function value corresponding to phase 0 degrees. Rather than storing the value of cos π / 4. The sine lookup table 112 and the cosine lookup table 114 respectively output L-1 bit function values stored at addresses corresponding to the phase data output from the multiplexer 108.

The function values sin π / 4 (or cos π / 4) corresponding to the phase 0 degrees stored in the sine lookup table 112 and the cosine lookup table 114 respectively are mirroring-related upper limits 70b, 70d, 70f, and 70h. ) Is an accurate value, but is an incorrect value for the non-mirror-related upper limits 70a, 70c, 70e, 70g. Therefore, a means for correcting this is necessary, zero phase processing means 230 is for this purpose.

The zero phase processing means 230 outputs a logic 0 when P [N-3] = 0 and simultaneously satisfies the condition that the phase data P [N-4: NM] = 0, and otherwise The zero phase determination unit 116 for outputting logic 1, the inverter 122 for inverting and outputting the output of the zero phase determination unit 116, the output of the sine lookup table 112 and the zero phase determination unit 116 An AND gate 118 for logic and outputting the output and an OR gate 120 for outputting the output of the cosine lookup table 114 and the output of the inverter 122 are output.

The zero phase determination unit 116 outputs a value of 0 only when the initial phase values of the non-mirror-related upper limits 70a, 70c, 70e, and 70g are input to the zero phase determination unit 116. Therefore, in this case, 0 is input to the AND gate 118 and 1 is input to the OR gate 120. The AND gate 118 always outputs 0 regardless of the size of data input from the sine lookup table 112. In addition, the orgate 120 always outputs 1 regardless of the size of the output data of the cosine lookup table 114. As a result, the sine and cosine function values corresponding to the initial phase values in the non-mirror-related upper limits 70a, 70c, 70e, and 70g are correctly corrected to 0 and 1.

The output value of the AND gate 118 and the output value of the or gate 120 pass through the path switching means 240 and are controlled with respect to the output path. Path switching means 240 comprises two multiplexers 124, 126. Output terminals of the AND gate 118 and the OR gate 120 are connected to two input terminals of logic 0 and logic 1 of one multiplexer 124, respectively. The output terminals of the or gate 120 and the AND gate 118 are connected to two input terminals of logic 0 and logic 1 of the remaining multiplexer 126, respectively. In addition, an output terminal of the exclusive-or 110 is connected to each control terminal of the two multiplexers 124 and 126. When the exclusive-orgate 110 outputs 1, the cosine-related upper limits ( 70b, 70c, 70f, 70g), and the case where 0 is outputted is the sign-related upper limits 70a, 70d, 70e, 70h. According to the above connection, when the multiplexer 124 selects the output value of the AND gate 118, the multiplexer 126 selects the output value of the or gate 120. In another case, when the multiplexer 126 selects the output value of the AND gate 118, the multiplexer 124 selects the output value of the or gate 120. As a result, the data output through the multiplexer 124 relates to a sine function, whereas the data output through the multiplexer 126 relates to a cosine function.

The first inverting processing means 250 is connected to the output terminal of the multiplexer 124. The first inverting processing means 250 generates a complement of two of the output data of the multiplexer 124, that is, a two's complement 128 that generates a value obtained by converting a sine function value, and the multiplexer. Among the two input data according to the value of the most significant bit data P [N-1] inputted to the input of logic 0 and logic 1 and the output of 124 and the complement of 128, respectively, to the input of logic 0 and logic 1, respectively. And a multiplexer 134 for selectively outputting either. In the sine function, if the value of the most significant bit data P [N-1] is 0, it corresponds to the positive upper limit (70a, 70b, 70c, 70d), and thus the multiplexer 134 converts the sign applied to the input of logic 0. If the value of P [N-1] is equal to 1 and the value of P [N-1] is 1, it corresponds to the negative upper limit (70e, 70f, 70g, 70h), and thus the multiplexer 134 applies the sign-converted data applied to the input terminal of logic 1. Outputs

In addition, the second inverting processing means 260 is connected to the output terminal of the multiplexer 126, respectively. The second inverting processing means 260 generates a complement of two of the output data of the multiplexer 126, that is, a two's complement 130 for generating a value obtained by inverting a cosine function value, and the multiplexer. Among the two input data according to the output value of the exclusive-orgate 132 which is input to the control terminal and the output data of the 126 and the complementary device 130 of the 2 are respectively input to the inputs of logic 0 and logic 1, respectively. And a multiplexer 136 for selectively outputting either. In the cosine function, if the output value of the exclusive-orgate 132 is zero, it corresponds to a positive upper limit (not shown, which corresponds to 70a, 70b, 70g, and 70h of FIG. 5), and therefore, the multiplexer 136 is logic 0. Outputs unsigned data applied to an input terminal of the output terminal, and if the output value of the exclusive-orgate 132 is 1, it corresponds to a negative upper limit (not shown, 70c, 70d, 70e, and 70f of FIG. 134 outputs the sign-converted data applied to the input terminal of logic 1.

As a result, the NCO according to the present invention uses the upper limit data of 3 bits and the phase data of the remaining bits of the most significant M bits output from the phase accumulator 104 through the multiplexer 134 and the multiplexer 136, respectively. Output the sampling value sin 2πFT and the cosine sampling value cos 2πFT respectively.

The sample values thus obtained are subjected to post-processing such as digital / analog conversion processing and filtering to finally produce analog signals of a desired type (see FIG. 1). Digital outputs are further output by adding a digital / analog (D / A) converter (not shown) to the output terminals of the first and second inverting processing means 250 and 260, that is, the output terminals of the multiplexer 134 and the multiplexer 136. Convert the sample value of the form to an analog signal. Further, a filter circuit (not shown) is further added to the rear end of the D / A converter to filter an output value of the D / A conversion unit to produce an analog signal subjected to a smoothing process.

In the above, a preferred embodiment of the present invention has been described. The phase accumulator employs 24-bit, 10-bit 45-degree sine and cosine lookup table with 2 ¹⁰ addresses, the operating clock frequency is 40 MHz to form the NCO, and spurious noise according to each FCW. Computer simulations were performed by comparing the size of the proposed method with the proposed method.

The output frequency of the digital carrier signal varies depending on the FCW input. Assuming that the operating clock frequency is 40 MHz, the IF frequency is obtained by Equation (1) mentioned above, and the frequency resolution is 2.384 Hz by Equation (2). When the output signal is viewed in the frequency spectrum, spurious signals appear and the results are compared with the magnitude of the carrier signal and the results are summarized in Table 1. As can be seen from the table, it can be seen that the NCO according to the present invention has much better frequency spectrum characteristics than the conventional method.

FCW IF [Hz] Traditional way Proposed method 2 ¹¹ 4.883K -72 dBc -90 dBc 2 ¹² 9.766K -72 dBc -88 dBc 2 ¹³ 19.531K -72 dBc -84 dBc 2 ¹⁴ 39.063K -72 dBc -82 dBc 2 ¹⁵ 78.125K -71 dBc -81 dBc 2 ¹⁶ 156.25K -71 dBc -80 dBc 2 ¹⁷ 312.50K -72 dBc -75 dBc 2 ¹⁸ 625.00K -70 dBc -74 dBc 2 ¹⁹ 1.25M -71 dBc -72 dBc 2 ²⁰ 2.50M -71 dBc -70 dBc 2 ²¹ 5.00M -69 dBc -72 dBc

As a result of coding the proposed method with Verilog, the total number of gates except for the ROM size of the lookup table was about 1500. This adds only 10 endgates, 11 orgates, and one more inverter than traditional methods. As a result, the present invention enables the implementation of an NCO with improved frequency spectrum characteristics over the existing method with little difference in the amount of hardware from the existing method. The implemented NCO can be very useful for FSK modulation, FM modulation, SSB modulation, and digital synchronous demodulation circuit.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (9)

Performs 2 ^N module operations while accumulating the phase of the frequency control word (FCW) and shifts the 360 degree phase to sine, cosine mirror, cosine, sine mirror, sine in mirror, cosine mirror in version, and cosine in Phase accumulation means for outputting t bits as the upper limit data for specifying one of the upper limit data of the version and the sine_mirror inversion, and Mt bits as 0 to 45 degree phase data; A first selection signal for distinguishing a mirroring upper limit and a non-mirror upper limit, a second selection signal for distinguishing a sign related upper limit and a cosine related upper limit, an inverting related upper limit and a non-inverting related time Selection signal generating means for generating a third selection signal for discriminating an upper limit and a fourth selection signal for discriminating an inverting related upper limit and a non-inverting upper limit relating to cosine; Phase mirroring means for selectively outputting either of the phase data and two's complement data of the phase data, which are phase mirroring data of the phase data, in response to the first selection signal; Storing a value of sin π / 4 as a value corresponding to 0 degrees and a sine function value sin x as a value corresponding to a phase x between 0 <x <π / 4, and outputting the phase from the phase mirroring means. A sine lookup table for outputting a sine function value corresponding to the data; Storing a value of cos π / 4 as a value corresponding to 0 degrees and a cosine function value cos x as a value corresponding to a phase x between 0 <x <π / 4, and outputting the phase from the phase mirroring means. A cosine lookup table for outputting a cosine function value corresponding to the data; A function corresponding to the zero phase of the sine lookup table and the cosine lookup table after receiving the output value of the sine lookup table and the output value of the cosine lookup table through separate inputs and outputting the same through the first and second outputs. A zero phase processing means for converting an output value of the sine lookup table to a first output stage when the value is to be used and converting the output value of the cosine lookup table to a first output stage to a second output stage; Path switching means for switching control of an output path for outputting a sine function value and a cosine function value output from the zero phase processing means applied through two input terminals to the first and second output terminals in response to the second selection signal; First inverting processing means for selectively outputting any one of an output value of a first output stage of said path switching means and a two's complement value of said output value in response to said third selection signal; And And second inverting processing means for selectively outputting any one of an output value of a second output stage of said path switching means and a two's complement value of said output value in response to said fourth selection signal. . 2. The apparatus according to claim 1, wherein the selection signal generating means receives 3-bit data as the upper limit data, outputs the least significant one of the bits as the first selection signal, and exclusively ORs the lower two bits as the second selection signal. And outputs the most significant 1 bit as the third selection signal, and outputs the most significant 2 bits as the fourth selection signal by performing an exclusive OR. 2. The zero phase processing means according to claim 1, wherein the zero phase processing means outputs a logic zero when simultaneously satisfying the condition that the value of the first selection signal is 0 and the condition that the value of the phase data is 0, and otherwise, logic. A zero phase determination unit outputting 1 to determine whether to use a function value corresponding to zero phase of the sine lookup table and the cosine lookup table; An inverter for inverting and outputting the output of the zero phase determination unit; An AND gate configured to logic and output an output of the sine lookup table and an output of the zero phase determination unit; And an orgate configured to logically output the output of the cosine lookup table and the output of the inverter. 2. The apparatus of claim 1, wherein the phase mirroring processing means comprises: complementary generation means for receiving the phase data output from the phase accumulation means and generating and generating two's complement data for the phase data; And a multiplexer for separately receiving the phase data outputted from the phase accumulation means and the complementary data outputted from the complementary generating means and selectively outputting only one designated by the first selection signal. The first multiplexer of claim 1, wherein the path switching means receives a sine function value and a cosine function value separately output from the zero phase processing means in response to the second selection signal, and selectively outputs any one of them. ; And a second multiplexer configured to separately receive a sine function value and a cosine function value output from the zero phase processing means in response to the second selection signal and selectively output the other one not selected by the second selection means. Digital frequency synthesizer characterized in that. 2. The apparatus of claim 1, wherein the first inverting processing means comprises: reward generating means for generating two's complement of an output value of a first output terminal of the path switching means; And a multiplexer for selectively outputting any one of an output value of the first output terminal of the path switching means and an output value of the maintenance generating means in response to the third selection signal. 2. The apparatus of claim 1, wherein the second inverting processing means comprises: reward generating means for generating two's complement of an output value of a second output terminal of the path switching means; And a multiplexer for selectively outputting any one of an output value of the second output terminal of the path switching means and an output value of the maintenance generating means in response to the fourth selection signal. The digital frequency synthesizer of claim 1, further comprising D / A converting means for receiving output data of the first and second inverting processing means and converting the output data into an analog signal corresponding to the magnitude of the output data. The digital frequency synthesizer of claim 8, further comprising filtering means for filtering an output value of the D / A conversion means and outputting the analog signal as an analog signal.