KR100333977B1 - The switch control device of Switch Mode Power Supply - Google Patents

Abstract

The present invention relates to a switch control device of the SMPS.

The present invention provides an oscillator for outputting a pulse signal of a predetermined period; A first short pulse generator for generating a first short pulse signal according to a pulse signal input from the oscillator, a first voltage increases according to the first short pulse signal, and compares the first voltage with the set comparison voltage A comparator for different outputs, a reset unit for initializing the first voltage after the comparator's output is in a first state, and a second short pulse signal generated each time the output of the comparator is in the first state. And a two-stage pulse generator, and an output unit for raising and outputting a voltage according to the second short pulse signal.

According to the embodiment of the present invention, the present invention does not require an external element for soft start, and thus does not have to have a pin for this external element, and there is an effect that soft start is possible.

Description

The switch control device of Switch Mode Power Supply

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch mode power supply (hereinafter referred to as 'SMPS'), and more specifically, to control the turn-on time of the switch, and a pin connected to the outside for a constant time constant. The present invention relates to a switch control device of an SMPS that does not require a soft start and enables a soft start.

In general, SMPS is a device that allows a desired power to be output through an output terminal by adjusting the turn-on time of a switch (Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) for input power.

The SMPS provides precise output stably without stress to the peripheral circuits under any conditions, and protects the device by driving a separate protection circuit under abnormal conditions so that it can be used more reliably and reliably.

However, SMPS is protected by abnormally controlling the turn-on time of the switch due to the capacitive component of the output stage during initial start-up, thereby causing stress on the peripheral circuits, or by detecting the abnormality of the switch control device that controls the turn-on time of the switch. By operating the circuit, the output cannot be controlled reliably.

For this reason, the conventional SMPS is connected to the external capacitor (Css) by separately forming a terminal (P1) with a pin (P2) for the feedback voltage for controlling the turn-on time of the switch as shown in FIG. At the initial start-up, as the current of the current source I charges the external capacitor Css, the current applied to the base of the transistor Q2 through the diode D2 gradually increases, thereby switching through the transistor Q2. Causes soft start (soft_start).

Here, the turn on time of the switch depends on when the threshold voltage is reached by the current applied through the diode D2.

Therefore, in the related art, the system is configured to gradually increase the turn-on time of the switch at initial startup by increasing the capacity of the external capacitor.

However, as shown in FIG. 1, a pin for connecting to an external capacitor has to be formed in the related art, and an external capacitor has to be used separately.

The present invention provides a switch control device of an SMPS that does not require a pin for an external device and enables soft start without using an external capacitor.

1 is a view showing a pin formed in a switch control apparatus of a conventional SMPS and an element connected to the pin.

2 is a block diagram of an apparatus for controlling a switch of an SMPS according to an exemplary embodiment of the present invention.

3 is a circuit diagram of a switch control apparatus of an SMPS according to an embodiment of the present invention.

4 is a signal waveform diagram generated by a switch control device according to an embodiment of the present invention according to a clock signal of an oscillator.

5 is a view showing a pin formed on the switch control device of the SMPS according to an embodiment of the present invention and the element formed on the pin.

An apparatus for controlling a switch of an SMPS according to a feature of the present invention for achieving the above technical problem is to generate a first short pulse signal corresponding to an output pulse of an oscillator by inputting an output pulse of an oscillator embedded in the SMPS, and The first voltage to be input to the comparator is increased according to the one-pulse signal. If the first voltage is greater than the reference voltage of the comparator, the output of the comparator is toggled and the first voltage is reset by subsequent circuit operation. The reset first voltage is caused to rise again according to the first short pulse signal and reset by the operation after the output of the comparator is toggled. Accordingly, the first voltage has a certain shape like an oscillator although its period is different.

It is apparent that the period of the first voltage is longer than that of the oscillator.

The output of the comparator causes a second short pulse signal to be generated, the second short pulse signal depending on the signal waveform of the first voltage. Therefore, the second short pulse signal has a longer period than the first short pulse signal.

The present invention allows the output voltage to increase when the second short pulse signal is generated to gradually increase the time for turning on the switch of the SMPS.

Accordingly, in order to achieve the above, the SMPS switch control apparatus according to the characteristics of the present invention, the oscillator for outputting a pulse signal of a certain period; A first short pulse generator for generating a first single pulse signal according to a pulse signal input from the oscillator; A comparator for causing a first voltage to increase according to the first short pulse signal, and comparing an increased first voltage with a set comparison voltage to vary an output; A reset unit for initializing the first voltage when the output of the comparator is in a first state; A second short pulse generator configured to generate a second short pulse signal whenever the output of the comparator is in a first state; And an output unit for increasing and outputting a voltage according to the second short pulse signal.

The first short pulse signal or the second short pulse signal may be an impulse signal.

The first short pulse generator is a first transistor to be turned on / off according to the pulse signal of the oscillator, a turn-on time is determined according to the first capacitor and the reference voltage, the charge is determined according to the on / off of the first transistor, And a second transistor for turning off the outputting first short pulse signal.

The comparator includes a second capacitor which charges a current each time the first short pulse signal is generated, and a comparator for varying an output by comparing a voltage of the second capacitor with a set comparison voltage.

The second short pulse generator may include a third capacitor configured to charge according to the output signal of the comparator and a third transistor configured to turn off the second short pulse signal determined and output according to a reference voltage.

Hereinafter, a switch control apparatus of an SMPS according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, the present invention causes the output to be applied to the switch of the SMPS at initial startup to gradually increase the time for turning on the switch of the SMPS without using an external element.

This concept is explained with reference to 2.

2 is a block diagram of an SMPS switch control device according to an embodiment of the present invention, the oscillator 10, the first short pulse generator 20, the comparison unit 30, the reset unit 40, the second It consists of a short pulse generator 50 and an output unit 60.

When the oscillator 10 continuously outputs a clock pulse having a predetermined period, the first short pulse generator 20 receives a clock pulse and outputs a high state for a predetermined time after the clock pulse falls from a high state to a low state. Create a pulse.

That is, the first short pulse generator 20 outputs a high state signal only in a specific section and a low state signal in a remaining section even when a clock pulse for outputting a high state signal is input. When the clock pulse to which the low state signal is output is input, the low state signal is output.

The comparator 30 includes a comparator, and the two voltages compared by the comparator are a comparison voltage and a first voltage. The first voltage is designed such that the level rises when the first short pulse signal is input from the first short pulse generator 20, and the comparison voltage exists at a set value. Therefore, when the first short pulse signal is gradually input to the comparator 30, the first voltage is increased, and at some point, the first voltage becomes greater than the comparison voltage. In this case, the comparator for comparing the first voltage and the comparison voltage outputs a high state signal in which the previous signal is toggled when the first voltage is equal to the comparison voltage.

Here, the signal output from the comparator 30 is input to the reset unit 40, which is input to the second short pulse generator 50, and the output of the second short pulse generator 50 is output to the output unit 60. When the output of the i) satisfies, the reset unit 40 is operated to initialize the input of the comparator 30.

Accordingly, the first voltage rises and falls to the minimum value by the reset unit 40, and rises and falls again.

The second short pulse generator 50 outputs a high signal when the high signal of the comparator 30 outputs when the first voltage and the comparison voltage are equal to each other. Like the single pulse generator 10, a high signal is output only for a certain period among the sections for outputting a high signal, and a low signal is output for the remaining sections.

Therefore, the second short pulse generator 50 outputs a second short pulse signal having a predetermined period. At this time, since the second short pulse signal depends on the output of the comparator 30, the period of the second short pulse signal is longer than that of the first short pulse signal.

The second short pulse signal is applied to the output unit 60. The output unit 60 causes the output voltage to rise when the second short pulse signal is input, and the voltage rises when the second short pulse signal is not input. It is designed to remain as it is.

Accordingly, the level of the turn-on voltage of the SMPS output from the output unit 60 gradually increases, and thus the switch of the SMPS is soft-started.

Here, the first voltage rises and the output change of the comparator 30 depends on the length of the on section of the first short pulse signal, and the output of the output unit 60 depends on the on section of the second short pulse signal.

However, for the soft start, the longer the time to reach the threshold voltage of the switch is the gain, it is preferable to make the first and second short pulse signal to be an impulse signal.

Hereinafter, the present invention with reference to Fig. 2 will be described in detail with reference to Figs.

3 is a circuit diagram of a switch control apparatus of an SMPS according to an embodiment of the present invention. As illustrated in FIG. 3, the first short pulse generator 20 may turn on / off transistors Q1 and CS1 that are turned on / off according to clock signals of the current sources CS1, CS2, and CS8 and the oscillator 10. A capacitor C1 that charges or discharges a current, a transistor Q2 that turns on / off according to a potential of the capacitor C1, a transistor Q3 that turns on while a current is charged in the capacitor C1, and a transistor Q3. Is turned on and outputs the first short pulse signal Va to the transistor Q4. Here, the base of the transistor Q2 is coupled to the output terminal of a reference voltage generator (not shown).

The comparator 30 is connected to the current source CS3 and the current source CS3 and operates according to the first short pulse signal and consists of the transistors Q5, Q6, Q7 and Q8. A comparator for comparing the voltage Vb of the capacitor C2 and the voltage of the capacitor C2 and the comparison voltage Vt and outputting a high signal when the voltage Vb becomes equal to the comparison voltage Vt. (COMP).

The reset unit 40 includes a transistor Q9 driven according to the high signal of the comparator COMP.

The second short pulse generator 50 is turned on when the transistors Q10 and Q10 turned on / off according to the outputs of the current sources CS4, CS5, CS6, and CS9 and the comparator COMP. The transistor Q11, the capacitor C3 that charges the current of the current source CS5 when the output of the comparator COMP is high, the capacitor C12 that turns on when the potential of the capacitor C3 becomes a constant potential, The transistors Q13 and Q14 turned on by the current source CS5 and the transistors Q15 turned on when the transistor Q13 is turned off and output a second short pulse signal. Here, the base of the transistor Q12 is coupled to the output terminal of a reference voltage generator (not shown).

The output unit 60 is connected to a current source CS7, a current source CS7, driven by a second short pulse signal, and includes a current mirror CM2 consisting of transistors Q16, Q17, Q18, Q19, and Q20, and a current mirror. It consists of a capacitor (C4) that enters the input of the comparator 30 to determine the on time at the initial startup of the SMPS through a buffer (b) to charge the current supplied from and to transfer the charging voltage.

Therefore, when the clock signal CLK as shown in Fig. 4A is output from the internal oscillator 10, and the clock signal CLK is changed from the high state to the low state, the transistor Q1 is turned off and the current source CS1 is turned off. The current of is charged in the capacitor C1, so that the transistor Q3 is turned on to flow the current of the current source CS2 to the ground, and the transistor Q4 is turned off.

Therefore, the high voltage is formed by the current source CS2 of the voltage Va formed at the collector end of the transistor Q4.

This voltage Va turns on the current mirror CM1 and causes the current of the current source CS3 to charge the capacitor C2.

On the other hand, after the transistor Q1 is turned on, when a predetermined time (T = C (capacitance of C1) x V (voltage of C1) / I (current of CS1)) passes, the voltage V of the capacitor C1 becomes It rises by Vref + 1Vbe (the potential between the emitter and the base of transistor Q2), and this voltage acts as the emitter voltage of transistor Q2 to turn on transistor Q2.

Therefore, even when the clock signal CLK is turned off with the transistor Q1 turned low, the current of the current source CS1 flows to the ground through the transistor Q2, so that the transistor Q3 is turned off and the transistor Q4 is turned off. Is turned on so that the current of the current source CS3 flows to the ground through the transistor Q4.

As a result, the voltage Va drops to 0 V to become a short pulse.

Here, the time when the voltage Va is formed and falls to 0V depends on the capacity of the capacitor C1. In other words, when the capacitance of the capacitor C1 is increased, the waveform of the voltage Va becomes long in the on period, and when the capacitance is reduced, the on period is shortened and becomes an impulse signal. Here, in the present invention, it is preferable that the waveform of the voltage Va is an impulse signal.

When the voltage Va drops to OV, the current of the current source CS3 applied to the capacitor C2 is cut off, so that the charging of the capacitor C2 is stopped until the next voltage Va becomes high. At this time, the potential of the capacitor C2 is maintained at a constant voltage because there is no charge / discharge path.

As a result, the voltage Va represents a short pulse signal having a predetermined period according to the clock signal CLK as shown in FIG. 4B, and the capacitor C2 is charged only while the voltage Va is displayed.

While the voltage Vb of the capacitor C2 maintains a constant voltage, when the next clock signal CLK changes from a high state to a low state and the voltage Va is formed again, a current is applied to the capacitor C2 so that the voltage (Vb) becomes high.

The charging operation of the capacitor C2 is repeated according to the clock signal CLK, and each time the voltage Vb of the capacitor C2 becomes high.

The voltage Vb of the capacitor C2 gradually increasing is input to the non-inverting terminal of the comparator COMP and is compared with the comparison voltage Vt by the comparator COMP.

If the voltage Vb is less than the comparison voltage Vt, the comparator COMP outputs a low level signal, and thus, the currents of the current sources CS4, CS5, CS6, and CS7 all flow to the ground terminal. There is no output through the buffer (b).

However, when the voltage Vb rises to reach the comparison voltage Vt, the comparator COMP outputs a high level signal, thereby turning on the transistor Q10 and turning off the transistor Q11. . When the transistor Q11 is turned off, the current of the current source CS5 is charged to the capacitor C3 and turns on the transistors Q13 and Q14.

The transistor Q15 is turned off, and a voltage Vc is formed at the collector of the transistor Q15 by the current of the current source CS7. This voltage Va turns on the current mirror CM2, causes the current of the current source CS7 to charge the capacitor C4, turns on the transistor Q9, and forms a discharge path of the capacitor C2 to form a capacitor. Let C2 discharge.

On the other hand, after the transistors Q13 and Q14 turn on, when a predetermined time (T = C (capacitance of C3) x V (voltage of C3) / I (current of CS5) passes, the voltage of the capacitor C3 (V) ) Rises by Vref + 1Vbe (the potential between the emitter and base of transistor Q12), and this voltage acts as the emitter voltage of transistor Q12 to turn on transistor Q12. When the transistor Q12 is turned on, the current of the current source CS5 flows to the ground terminal through the transistor Q12, so that the transistors Q13 and Q14 are turned off and the voltage Vc drops to 0V.

Here, the time when the voltage Vb is formed and falls to 0V depends on the capacity of the capacitor C3. In other words, when the capacitance of the capacitor C3 is increased, the waveform of the voltage Vb becomes longer in the on period, and when the capacitance is reduced, the on period is shortened and becomes an impulse signal. Here, in the present invention, it is preferable that the waveform of the voltage Vb is an impulse signal.

When the voltage Vb falls to 0V, the charging of the capacitor C4 is stopped and the transistor Q9 is turned off to restart the charging of the capacitor C2. As a result, as the clock pulse CLK is input, each transistor operates to charge the capacitor C4 again.

That is, when the clock signal CLK of a certain period as shown in a shown in Figure 4 occurs, the voltage Va is formed when the clock signal CLK changes from a high state to a low state as shown in b of FIG. The short pulse signal form immediately falls to 0 V due to the turn-on of the transistor Q2 due to the voltage of (C1), and the short pulse signal form again when the clock signal changes from the high state to the low state again.

In addition, the voltage Vb represents a periodic signal shape in which the level rises each time the voltage Va is generated, and falls off at the same time as the comparison voltage Vt of the comparator COMP, as shown in FIG. Vc indicates a high level when the voltage Vb falls from a high level to a low level as shown in d of FIG. 4, but immediately falls to 0V by the turn-on of the transistor Q12 by the voltage of the capacitor C3. Indicates the pulse signal shape. The short pulse signal shape of the voltage Vc periodically appears according to the voltage Vb.

The voltage Vout of the capacitor C4 supplied to the switch side of the SMPS increases as the voltage Vc represents a short pulse as shown in FIG.

Therefore, the current pulse charged in the capacitor C4 can make the desired frequency and high duty by adjusting the turn-on time of the transistors Q2 and Q12, that is, by adjusting the capacitances of the capacitors C1 and C3. As a result, the time for turning on the switch of the SMPS can be gradually increased.

As a result, the present invention does not require an external device as shown in FIG. 5, does not require an external pin, and does not require a separate pin connected to the external device, and enables soft start.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

The present invention does not require an external device for soft start, thus eliminating the need for a pin for this external device and having a soft start effect.

Claims (5)

An oscillator for outputting a pulse signal of a predetermined period; A first short pulse generator configured to generate a first short pulse signal according to a pulse signal input from the oscillator; A comparator for causing a first voltage to increase according to the first short pulse signal, and comparing an increased first voltage with a set comparison voltage to vary an output; A reset unit for initializing the first voltage after the output of the comparator becomes a first state; A second short pulse generator configured to generate a second short pulse signal whenever the output of the comparator is in a first state; And And an output unit for increasing and outputting a voltage according to the second short pulse signal. In claim 1, Switch control device of the SMPS, characterized in that at least one of the first short pulse signal or the second short pulse signal is an impulse signal. In claim 1, The first short pulse generator and the second short pulse generator, The first transistor to be turned on / off according to the pulse signal of the oscillator, the first capacitor to be charged according to the on / off of the first transistor, and the turn-on time is determined according to the time constant of the first capacitor. And a second transistor for determining the on duration of the pulse signal. In claim 1, The comparison unit, A second capacitor which charges a current each time the first short pulse signal is generated, a first capacitor positioned between a predetermined current source and the second capacitor and allowing the second capacitor to charge current only in a high period of the first short pulse signal And a comparator for varying an output by comparing a current mirror and a voltage of the second capacitor with a set comparison voltage. In claim 1, The output unit, A third capacitor that charges a current each time the second short pulse signal is generated, a second capacitor positioned between a predetermined current source and the third capacitor, and allowing the third capacitor to charge current only in a high period of the second short pulse signal Switch for controlling the SMPS, characterized in that it comprises a current mirror, and a buffer for transmitting the voltage formed in the third capacitor to the outside.