KR100333692B1 - Method and apparatus for drain-back operation of trace back data - Google Patents

Abstract

The present invention provides a method and apparatus for backflowing data for accurate and reliable data error checking, wherein the received data is divided into at least first and second groups. First step; A second step of storing the first and second groups of data in at least one storage device; A third step of backtracking the first group of data stored in the storage device; Backflowing the backtracked first group of data; A fifth step of sequentially storing the reversely leaked first group of data in an auxiliary memory device; And a sixth step of sequentially storing the second group of data discharged from the storage device in the auxiliary storage device while outputting the first group of data stored in the auxiliary storage device. .

Description

Method and apparatus for drain-back operation of trace back data

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver chip for receiving satellite broadcasts, and more particularly, to a method and apparatus for backflowing data traced back in a Viterbi decoder of the receiver chip.

In general, a receiver chip for receiving satellite broadcasts includes a Viterbi decoder for checking and correcting errors in received data. The Viterbi decoder includes a reverse drainer for performing a drain-back operation of backtracking the received data to temporarily store the rearranged data and rearrange and output the rearranged data. The conventional backflow discharger is implemented as a storage device for temporarily storing backtracked data including a plurality of static random access memories (SRAMs) and a controller for increasing and decreasing addresses of the SRAMs.

In addition, the reverse tracking algorithm of the Viterbi decoder is basically implemented as follows.

1. Write the decision values. Usually, they are stored using SRAM.

2. Trace Back: Trace the address using the values stored in the SRAM.

That is, a trace having eight different initial values uses the characteristic of a Viterbi decoder that always converges.

3. Drain Back: Use the initial value (memory address) obtained by converging from the traceback.

The data value stored in each address represents the address of the next step. Since the traceback memory and the traceback algorithm are the basic architecture of the Viterbi decoder, detailed descriptions are omitted (Reference Book Error Control Coding, Lin / Costello).

However, the backflow device including a plurality of SRAMs and a controller for controlling them has a disadvantage in that the occupied area in the receiver chip is excessive and power consumption for operating the SRAM is added. In particular, although data need to be stored only for a relatively short period of time, it is not necessary to use a memory device having a complex structure such as SRAM in order to realize sufficient backflow operation. Macroblocks are a major cause of prolonging the overall chip design time, and it is very difficult to check design errors and change the design accordingly.

It is therefore an object of the present invention to provide a method and apparatus for backflowing data for accurate and reliable data error checking.

1 conceptually illustrates a pipeline structure of a Viterbi decoder of the present invention.

2 is a specific circuit block diagram of one embodiment of a register chain included in the Viterbi decoder of the present invention.

3 is an operational waveform diagram of the major part of the register chain of FIG.

* Explanation of the symbols of the main parts of the drawings

100, 102, 104, 106: storage device 108: register chain

200a to 200h: register unit 202: input terminal

204: output stage

In order to achieve the above object, the present invention provides a method for checking an error of received data, comprising: a first step of dividing the received data into at least a first group and a second group; A second step of storing the first and second groups of data in at least one storage device; A third step of backtracking the first group of data stored in the storage device; Backflowing the backtracked first group of data; A fifth step of sequentially storing the reversely leaked first group of data in an auxiliary memory device; And a sixth step of sequentially storing the second group of data discharged from the storage device in the auxiliary storage device while outputting the first group of data stored in the auxiliary storage device. .

According to another aspect of the present invention, there is provided an error checking apparatus for received data, comprising: at least one storage device for storing the received data in at least a first group and a second group; And at least one auxiliary storage device for sequentially storing data of the first group backflowed from the storage device, wherein the auxiliary storage device outputs the first group of data in a last-in-first-out manner. The present invention provides a data error checking apparatus for sequentially receiving and storing data of a second group that is leaked from the apparatus.

According to the present invention, the LIFO operation is performed by using two SRAMs when rearranging the decoded data in block units in the conventional architecture. However, in the present invention, a simple form using a register and a multiplexer without using an SRAM is used. Enables you to implement the same behavior and performance as LIFO.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 1, FIG. 1 conceptually illustrates a pipeline structure of a Viterbi decoder. As shown, taking a Viterbi decoder composed of four pipelines as an example, the processing steps up to writing data to the storage device and backflowing are described. That is, the Viterbi decoder may include four memory devices 100 to 106 to process four groups of data in parallel. Taking the first memory device 100 as an example, the first memory device 100 writes data determined at another part of the receiver chip at a first time point T1 (W). Then, at the second time point T2, the determined data is traced back (T), and after a brief wait (I) at the third time point, the traceback data is leaked back (D). The rest of the storage devices 102 to 106 also perform the write (W), backtracking (T), atmospheric (I), and backflow (D) operations as described above at different times.

In this case, the backflowed data should be temporarily stored in a separate memory device and rearranged. In the present invention, the register chain 108 is used as this separate memory device. That is, as shown in FIG. 1, the data backflowed by the first memory device at the fourth time point T4 is input to the register chain 108. The size of the data input from the first memory device 100 (or the second to fourth memory devices 102 to 106) into the register chain 108 is referred to as a trace-back depth. In one preferred embodiment, the backtracking depth is 128 bits. Thus, the register chain 108 includes 128 register units (described below). Of course, the backtracking depth may vary according to design choices, and thus the number of register units included in the register chain 108 may also vary.

Meanwhile, as shown in FIG. 1, since there are four groups of data leaked back at each time point, it is determined that the number of the register chains 108 needs to be four, but according to a preferred embodiment of the present invention. According to this, the register chain 108 can be reduced to one by the following method. To this end, reference will be made to FIG. 1 and will be described with reference to only the steps of outflowing data according to the progress of each time point. That is, if data is leaked out of the second memory device 102 at the first time point T1, data flowing out of the second memory device 102 is sequentially input to the register chain 108. Let's do it. For convenience, if each register unit included in the register chain 108 exists from the unit 0 (REG0 of FIG. 2) to the unit 127 (REG127 of FIG. 2), the reverse flow inputted at the first time point T1 is performed. The data is shifted right from the unit REG0 so that the first data is stored in the unit REG127 and the last data is stored in the unit REG0.

At the next time point, i.e., the second time point T2, the last input data must first be output (i.e., last-in-first-out) in order to rearrange the data stored in the register chain 108, so that the register chain 108 While outputting the last data stored in unit 0 of the register (REG0), all the data stored in the remaining register unit is left shifted. At this time, since the stored data does not exist in unit 127 of the register chain 108, new data can be input. Therefore, the data from the memory device (ie, the third memory device 104) that causes the data to flow back at the second time point T2 is transmitted to the first data unit 127 of the register chain 108. Enter it. If the above process is repeated with respect to the remaining data, the data from the second memory device 102 stored at the first time point T1 is output for subsequent processing in a last-in-first-out manner, and as they are outputted, The backflow data from the third memory device 104 is sequentially shifted left and stored in each register unit.

Similarly, when the third time point T3 is reached, the data of the register chain 108 inputted from the third memory device 104 at the second time point T2 is shifted to the right and outputted in a last-in first-out manner. At the same time, the backflow data from the fourth memory device 106 which is performing the backflow operation at the current third time point T3 is inputted back to the 0th unit REG0 of the register chain 108 and shifts rightward. Let's do it. This process is repeated at the fourth time point T4.

By alternately performing left-shifting and right-shifting operations of the input / output data as described above, backflow data from a plurality of storage devices can be stored and reprinted using only one register chain 108. However, the above embodiment does not mean that only one register chain should be used, and designing to perform such a function using two or more register chains is well known in the art. It is self-evident to him.

Referring now to FIG. 2, FIG. 2 is a specific circuit block diagram of one embodiment of the register chain 108. As shown, the register chain 108 includes a plurality of register units 200a to 200h, and the register units 200a to 200h are composed of a multiplexer and a register. The register chain 108 further includes an input terminal 202 for receiving backflow data from each of the storage devices 100 to 106 and an output terminal 204 for outputting data stored in each register unit again. Include.

Unit 0 (200a) of the register chain 108 can receive and selectively store both the signal from the input terminal 202 and the signal from unit 1 (200b), while the unit 0a (200a) The output of is transmitted to both the output terminal 204 and the first unit 200b. The first unit 200b may receive and selectively store both the output from the unit 0a and the output from the unit 200c, and the output of the unit 200b may be selectively stored. It is delivered to both the 0th unit 200a and the 2nd unit 200c. Furthermore, the unit 127 200h may receive and selectively store both the signal from the input terminal 202 and the signal from the unit 126 200g, and the output of the unit 127 200h may be It is delivered to both the output terminal 204 and the unit 126 (200g). The input / output of each register unit 200a to 200h of the register chain 108 is connected to the unit before and after each of them to implement both the left shift and the right shift, and to select one from the above two inputs. To include multiplexers. Furthermore, in order to enable both input and output at both ends of the register chain 108, two units of units 0 200a to 63 200d and units 64e 200e to 127 200h are provided. The groups were to have a symmetrical structure.

Finally, referring to FIG. 3, FIG. 3 is an operational waveform diagram of the major portion of the register chain 108 of FIG. 2. As shown, the left shift or right shift operation is controlled by the control signal we_rifo_1.

According to the present invention, the total size of the receiver chip can be reduced, and the chip can be designed by a logic-synthetic design method, unlike the existing design method, thereby simplifying the overall chip structure and increasing the reliability of the chip operation. The yield in the manufacturing process can also be increased. Furthermore, the time required for chip design can be shortened to respond appropriately and quickly to market conditions.

Although a preferred embodiment of the present invention has been described, those skilled in the art will be able to modify and modify the same. Accordingly, the following claims should be construed as including all modifications and variations that fall within the scope of the preferred embodiments and the spirit of the present invention.

Claims (9)

In the error checking method of the received data, A first step of dividing the received data into at least first and second groups; A second step of storing the first and second groups of data in at least one storage device; A third step of backtracking the first group of data stored in the storage device; Backflowing the backtracked first group of data; A fifth step of sequentially storing the reversely leaked first group of data in an auxiliary memory device; And A sixth step of sequentially storing the second group of data discharged from the storage device in the auxiliary storage device while outputting the first group of data stored in the auxiliary storage device; Data error checking method comprising a. The method of claim 1, The auxiliary memory device Using a register chain containing multiple register units How to check for data errors. The method of claim 2, The fifth step, Shifting and storing each of the backflowed first group of data in one register in each register unit of the register chain; How to check for data errors. The method of claim 3, wherein The sixth step, Shifting and storing each of the data of the first group in a direction opposite to the direction of the fifth step while outputting the data of the first group in a direction opposite to the direction of the fifth step. How to check for data errors. The method of claim 1, The sixth step, Outputting the data of the first group by a last-in first-out method How to check for data errors. In the error checking device of the received data, At least one storage device for storing the received data into at least a first group and a second group; At least one auxiliary storage device for sequentially storing the first group of data flowed back from the storage device, The auxiliary memory device sequentially receives and stores data of the second group which is flowed back from the memory device while outputting the data of the first group in a last-in first-out manner. Data Error Checking Device. The method of claim 6, The auxiliary memory device, Register chain containing multiple register units Data Error Checking Device. The method of claim 7, wherein The register chain is An input for receiving the backflowed first or second group of data; And An output terminal for outputting the first or second group of data Data error checking device further comprising. The method of claim 7, wherein The register unit, Containing multiplexers and registers Data Error Checking Device.