KR100333585B1 - Method and system for selective disablement of expansion bus slots in a multibus data-processing system - Google Patents

Abstract

The present invention provides a Peripheral Component Interconnect (PCI) bus having a plurality of slots for interconnecting peripheral devices in an automatically formed configuration and a plurality of slots for interconnecting peripheral devices in a user-selected configuration. A method and system for eliminating collisions between peripherals in a multibus data processing system including an Industry Standard Architecture (ISA) bus. Each slot included in the ISA bus includes a reset line that temporarily disables the associated slot in response to power supply to the data processing system to prevent power fluctuation problems. In response to an existing device or potential conflict between devices caused by a user-selected configuration, a control signal is selectively applied to the reset line for one or more slots included in the ISA bus, and the slot during normal operation of the data processing system. Temporarily disables it.

Description

{METHOD AND SYSTEM FOR SELECTIVE DISABLEMENT OF EXPANSION BUS SLOTS IN A MULTIBUS DATA-PROCESSING SYSTEM}

The present invention relates generally to an improved data-processing system, and more particularly to a method for eliminating peripheral device conflicts in a multibus data-processing system. It is about the system. More particularly, the present invention relates to a method and system for selectively disabling expansion slots associated with a given bus in a multibus processing system.

Modern data processing systems use one or more sets of hardware lines to transfer data between components of a computer system. A set of hardware lines, called buses, connect the different parts of the system, including microprocessors, disk-drive controllers, memory, and input / output ports, and share virtually any device that enables such devices to transmit information. Shared highway.

Buses typically consist of specialized line groups that carry various types of information. One group carries the memory address where the data items can be found, while the other group of lines can carry the data. Other line groups of the bus may also carry control signals. Buses are generally characterized by the number of bits that can be transmitted in a single time. Most recent data processing systems also include one or more expansion slots that additional peripherals can be plugged to connect themselves to the bus.

Many other types of bus configurations can be distinguished by the structure of the data processing system. For example, the first personal computers manufactured by IBM used a bus that supported 8 bits at a time. A further refinement of the bus is a so-called AT bus which simultaneously supports 16 bits of data.

More recently, an Industry Standard Architecture (ISA) bus design specification has been introduced that allows peripheral components to be added as cards connected with standard expansion slots. Peripheral devices or expansion cards connected with the standard expansion slots must be configured to operate with a personal computer system. That is, the memory location, specific interrupt requests (IRQs), and various other specifications must be appropriately selected for the peripheral connected to the ISA to perform the appropriate function.

Today's modern personal computers frequently use what is called a peripheral component interconnect (PCI) local bus. The specification of the PCI local bus was introduced by Intel Corporation, which allows the local bus system to have up to 10 PCI-compliant expansion cards in a computer that can be mounted in a computer. PCI local bus systems require a PCI controller card that must be mounted in one of the PCI-compliant slots. PCI controllers can exchange data with the central processor of the system at the same time, either 32-bit or 64-bit, depending on the particular implementation, with PCI controllers intelligent bus-mastered by intelligent PCI-compliant adapters A technique called bus mastering is used to perform tasks with the central processor. In addition, devices designed to Plug and Play specifications automatically configure the computer itself to work with the expansion slots and attached peripherals mounted on the PCI local bus.

Many current computers include both an ISA bus and a PCI bus. Based on industry experience, customer support requests are often caused by resource conflicts or loss of functionality that occurs when end-users improperly attach peripherals such as modems, audio cards, or multimedia devices to ISA slots. I know that Such conflicts do not occur on the PCI bus since these conflicts are initially resolved by automatic configuration, which automatically changes the computer configuration.

Typically, a system that includes both ISA and PCI expansion slots can be employed by the manufacturer because certain features can only be used for ISA expansion slots. However, there are many customer bases that do not use ISA expansion slots, and as a result, the ability to prevent end users from inserting peripherals into ISA expansion slots would be highly desirable.

Thus, those skilled in the art will understand that a method and system for selectively disabling expansion slots associated with an ISA bus can reduce the number of service support requests from customers associated with problems that arise as a result of resource conflicts.

It is an object of the present invention to provide an improved data processing system.

Another object of the present invention is to provide an improved method and system for eliminating collisions between peripheral devices in a multiverse data processing system.

It is yet another object of the present invention to provide an improved method and system for selectively disabling expansion slots associated with a given bus in a multibus data processing system.

The above object is achieved by the following technique. The method and system of the present invention includes a PCI bus having a plurality of slots for interconnecting peripheral devices in an automatically formed configuration, and a plurality of slots for interconnecting peripheral devices in a user selected configuration selected by a user. It can be used to eliminate collisions between peripherals in a multibus data processing system including an ISA bus. Each slot included in the ISA bus includes a reset line that temporarily disables the associated slot in response to powering the data processing system to prevent problems due to power transitions. In response to a potential conflict between existing or peripheral devices caused by the user-selected configuration, a control signal is selectively applied to the reset line for one or more slots included in the ISA bus to normal operation of the data processing system. Temporarily disable one or more of these slots.

In addition to additional objects, the above features and advantages of the present invention will become apparent from the following detailed description.

1 is a high level block diagram of a network that may be used to implement the methods and systems of the present invention.

2 is a high level block diagram of a multiverse client system that may be used in the network of FIG.

3 is a high level block diagram of the multiverse client system of FIG. 2 with additional network connection circuitry used to implement one embodiment of the method and system of the present invention.

4 is a high level block diagram of control logic circuitry of the network connection circuit of FIG. 3 that may be used to implement the method and system of the present invention.

5 is a schematic diagram of a data packet that may be used to remotely control connector slots in the multibus client system of FIG. 2 in accordance with the method and system of the present invention.

6 is a high level logic flow diagram of an implementation sequence for implementing the method and system of the present invention.

A high level block diagram of a network that can be used to implement the method and system of the present invention is shown in particular in the diagram as in FIG. 1. As illustrated, the network master system 100 is connected to a hub 102 by a LAN connector bus 106. Multiple client systems 104A, 104B, 104C are also connected to hub 102 by respective LAN connector bus 106. In the illustrated embodiment of the present invention, the network illustrated in FIG. 1 follows the Ethernet specification and uses a common hub in this application. It will be apparent to those skilled in the art that other forms of network, such as a token ring, may also be used to implement the present invention.

A high level block diagram of a multiverse client system that can be used in the network of FIG. 1 is shown in FIG. As illustrated, the multibus client system of FIG. 2 is a central processing unit connected to a memory controller and a PCI bus bridge chip 208 by an address bus, control bus, and data bus 202. Unit; CPU). System memory 212 is also coupled to the memory controller and PCI bus bridge 208.

Industry-Standard PCI expansion bus 240 includes memory controller and PCI bus bridge 208, IDE device controller 214, PCI connector slot 218, PCI bus ISA bus bridge chip 216 Connect to Common in this application, the PCI bus corresponding to ISA bus bridge 216 also includes power management logic.

The multiverse data processing system shown in FIG. 2 also typically includes a storage device such as an input device, a fixed disk drive 222, and a floppy disk drive 224. . As shown, the fixed disk drive 222 is preferably connected to the IDE controller 214 and the floppy disk drive 224 is connected to the input / output controller 234. Input / output controller 234 is for flash memory 232 that includes a microcode that is coupled to the ISA bus 242 and can be executed by the illustrated multibus data processing system upon power up. It is preferable to include an interface.

As will be apparent to one of ordinary skill in the art, the flash memory 232 is preferably an electrically erasable programmable read-only memory (EEPROM) module, and is preferably located between the input / output device and the operating system. It contains a Basic Input / Output System (BIOS) that is used to interface with the. Input / output controller 234 also includes low voltage memory, such as CMOS memory, which may be used to store system configuration data, i.e., data depicting the current configuration of the multiverse data processing system of FIG. do. The information is a sequence used for a specific power method, display type, memory capacity, time, date, etc., and a list of Initial Program Load (IPL) devices set by the user. It may include. Additionally, the data stored in the low voltage memory may include a special configuration program, such as a configuration / setup program, which may be executed by a user of the multiverse data processing system shown in FIG. The battery 236 is typically provided in connection with the input / output controller 234 to provide power to the low voltage memory included in the specification of the present invention to prevent loss of configuration data.

A plurality of ISA expansion slots 220 are connected to the ISA bus 242. As described above, each ISA expansion slot 220 includes a dedicated reset line coupled to the reset logic 226. If the reset line is active, any card or peripheral device in the ISA expansion slot 220 is disabled. The signal on the reset line is generated in the power management logic of the ISA bus bridge chip 216 and is only active upon initial supply of power and is released when the power reaches normal operating conditions. In this manner, the operation of the peripheral device of the ISA expansion slot 220 may not occur during the initial supply of power to prevent certain problems that may occur as a result of power fluctuations. As shown, a power reset signal coupled with reset logic 226 disables each ISA expansion slot 220 upon initial power up.

3, a high level block diagram of the multibus data processing system of FIG. 2 with added network connection circuitry that may be used to implement one embodiment of the method and system of the present invention. do. As shown, each component of the multiverse data processing system other than the network connection circuit is not changed in FIG. 2 and uses the same reference numerals for these components.

As described above, the modified network adapter 300 is connected to the multiverse data processing system by one PCI expansion slot 218. Modification network adapter 300 includes control logic 400 coupled to a bus extending between a physical layer 304 and a media access controller (hereinafter referred to as 'MAC') 308. The physical layer 304 is connected to the network shown in FIG. 1 by the connector 306.

As described herein, the control logic 400 may be a 'hard-wired' application-specific integrated circuit (ASIC) or a programmed general-purpose processor. Can be implemented using By connecting the control logic 400 to the bus between the physical layer 304 and the MAC 308, the control logic 400 can send and receive network packets using the physical layer 304. According to the method and system of the present invention, the control logic 400 can accept data transmitted at the physical layer 304 and send control signals to the illustrated multibus data processing system to implement the method and system of the present invention. Can provide.

As shown, the control signal from the control logic 400 can be coupled to the reset logic 226 and is active in the reset line for one or more ISA expansion slots 220 in a manner described in more detail herein. Can be used to selectively generate a signal. In this way, one or more ISA expansion slots 220 may be selectively disabled to prevent collisions between peripheral devices during application. Here ISA expansion slot 220 is not used as specified by the system administrator of the network of FIG. Of course, the power reset signal may also be generated by the power management logic of the ISA bus bridge chip 216 as described above. In addition, each reset signal can also be generated by a software routine or via a general purpose input / output pin.

With reference to FIG. 4, a high level block diagram of a control logic portion of the network connection circuit of FIG. 3 that can be used to implement the method and system of the present invention is shown. As shown, the signal is received to the control logic 400 via the interface unit 514 on a bus interconnecting the physical layer 304 and the MAC 308. The interface unit 514 is preferably a carrier because it has multiple access interfaces implementing suitable network protocols to allow data packets transmitted from the network to be received by the multiverse data processing system of FIG. 2. Therefore, the received signal is transferred to a first-in / first-out buffer 508. Microcontroller 502 is used to coordinate the information processing according to the method and system of the present invention, and when a suitable network packet is received, the network packet is in the state of an expansion slot associated with the ISA bus. Is processed by the microcontroller 502 to update. Data regarding the state of the ISA expansion slot may be stored in register 510. A System Management (SM) bus interface 506 is provided from the control logic 400 to the multibus data processing system such that the status of the ISA expansion slot 220 and the contents of the register 510 are multiverse data. May be accessed by the processing system.

As shown in FIG. 4, one output of the microcontroller 502 is connected to a reset drive 520. Reset drive 520 is coupled to reset logic 226 and, in the manner described above, selectively disables one or more ISA expansion slots 220 in accordance with the methods and systems of the present invention during normal operation of the data processing system. Multiple logic signals 401 are typically provided.

Thus, as those skilled in the art will appreciate by the above technique, in a network system where a multiverse data processing system is provided and the system administrator decrees that the ISA expansion slot 220 is not used, collisions between peripheral devices are avoided. To avoid, the methods and systems of the present invention provide a technique in which control signals can be generated and used to selectively disable one or more ISA expansion slots of a multiverse data processing system. Since all peripheral devices connected to the PCI bus 240 automatically change configuration so that no collision can occur, this technique effectively prevents collisions between devices.

5, a schematic diagram of a data packet 600 that can be used to remotely control an ISA expansion slot 220 in accordance with the method and system of the present invention is shown. As shown, packet 600 includes a network head, which may include a MAC header, an IP header, and a UDP header, as in conventional well-known network communications that provide an address, identifier, and other information to transmit the packet correctly. It is preferable to include. The data packet also preferably contains the content of information to be transmitted. As illustrated in FIG. 5, the data packet preferably includes a data format and multiple bits of data. In the format shown in FIG. 5, a number of data signals provide a signal comprising an enable / disable state of each ISA expansion slot 220. As described above with respect to FIG. 4, when processed by the control logic 400, this information may cause one or more ISA expansion slots 220 (see FIG. 2) during normal operation of the multiverse data processing system. It can be used efficiently and effectively to selectively prohibit use.

Finally, in conjunction with FIG. 6, a high level logic flow diagram of execution order for implementing the methods and systems of the present invention is shown. As shown, processing begins at block 700 and then proceeds to block 702. Block 702 illustrates determining whether a packet has been received in the control logic 400. If a packet is not received by the control logic 400, the process continues to repeat until the packet is received.

Once the packet is received, processing proceeds to block 704. Block 704 illustrates the removal of header data, and processing then proceeds to block 706. Block 706 illustrates determining whether a received packet is a slot control packet, and if the received packet is not a slot control packet, processing proceeds to block 708 where the data in the packet is processed normally.

Referring back to block 706, if the identified packet is a slot control packet, processing proceeds to block 710. Block 710 illustrates determining whether the state of each ISA expansion slot of the multiverse data processing system is enabled / disabled. Processing then proceeds to block 712. Block 712 illustrates sending a suitable reset signal to each ISA expansion slot. Processing then proceeds to block 714 and returns. Referring back to block 708, after normally processing packets that are not slot control packets, processing also proceeds to block 714 and returns.

Referring to the above description, those skilled in the art will recognize that the applicant of the present invention may be selectively disabled during normal operation of the data processing system in order to prevent one or more expansion slots from colliding with peripheral devices in a single bus in a multibus data processing system. It will be appreciated that we have devised a method and system that can minimize the customer's service needs associated with the problem.

In the present invention, one or more expansion slots are selectively prohibited in the multiverse processing system, thereby preventing data collision between peripheral devices, thereby improving reliability of operation.

Claims (10)

A first bus including a plurality of slots for interconnecting peripherals in an automatically formed configuration, and a plurality of slots for interconnecting peripherals in a user-selected configuration, each of which is powered by a data processing system A method for eliminating collisions between peripheral devices in a data processing system having a second bus, the reset bus comprising a reset line that temporarily disables an associated slot in response to the second bus. Identifying a particular slot associated with the second bus; Selectively applying a control signal to the reset line associated with the particular slot, wherein the particular slot may be selectively disabled, during normal operation of the data processing system. Way. The system of claim 1, wherein the data processing system is interconnected to a network, Selectively applying a control signal to a reset line associated with the particular slot includes selectively applying a control signal to a reset line associated with the particular slot in response to a remote signal from the network. How to eliminate conflicts between devices. The method of claim 1, And simultaneously applying a control signal to the reset line associated with all slots associated with the second bus, wherein all slots may be selectively disabled during normal operation of the data processing system. To eliminate conflicts between peripherals in Windows. The method of claim 1, Selectively removing the control signal from a reset line associated with the particular slot in response to a user input. a) a central processing unit, b) a memory coupled to the central processing unit; c) a first bus coupled to the central processing unit, the first bus including a plurality of slots for interconnecting peripheral devices to the central processing unit in an automatically formed configuration; d) a second bus coupled to the central processing unit, wherein the second bus includes a plurality of slots for interconnecting peripheral devices to the central processing unit in a user-selected configuration; e) a reset line coupled to each slot associated with the second bus to temporarily disable the associated slot in response to power supply to the data processing system; f) control logic for selectively applying a control signal to a reset line coupled to a particular slot associated with the second bus, wherein the particular slot may be selectively disabled during normal operation of the data processing system. Data processing system. 6. The data processing system of claim 5, further comprising a network interface connecting the data processing system to a network. 7. The data processing system of claim 6, wherein the control logic is coupled to the network interface and selectively applies a control signal to a reset line in response to a remote signal from the network. 7. The data processing system of claim 6, wherein the control logic further comprises means for removing the control signal from a reset line. 7. The data processing system of claim 6, wherein the first bus comprises a Peripheral Component Interconnect (PCI) bus. 10. The data processing system of claim 9, wherein the second bus comprises an Industry Standard Architecture (ISA) bus.