KR100333335B1 - Phase Synchronous Loop Apparatus for Optical Disk Apparatus Adopting MPL Detection - Google Patents

Abstract

The phase locked loop apparatus of the present invention used in an optical disk apparatus employing a PLM detection method includes an analog / digital converter for converting a signal read by a pickup of an optical disk apparatus into a digital signal of a predetermined bit, and on the basis of a predetermined control voltage. A voltage controlled oscillator for outputting a frequency- and phase-controlled clock to the analog / digital converter and a data recovery unit of a PLM detection method at a later stage, and generating a pulse signal by comparing a signal read from the pickup with a predetermined slice level A synchronization pattern section is found in the digital signal, the synchronization pattern section is counted as the clock to determine whether the number is required for the synchronization pattern section, and a frequency error signal corresponding to the difference is output; The number of clocks counted in the sync pattern section is required for the sync pattern section. A frequency error detection unit for outputting a frequency lock detection signal when the number is matched, and detecting a phase difference between a clock closest to a zero crossing point appearing as the digital signal is sliced by the slice level and a predetermined edge of the pulse signal. A phase error detector for outputting a phase error signal, a selector for selectively outputting the frequency error signal and a phase error signal according to whether or not the frequency lock detection signal is applied, and loop filtering the error signal selected by the selector A loop filter is provided to the voltage controlled oscillator as a control voltage.

Description

Phase Synchronous Loop Apparatus in Optical Disc Device Adopting MPL Detection Method

The present invention relates to an optical disk device, and more particularly, to a phase locked loop (PLL) device in an optical disk device employing a PRML (Partial Response, Maximum Likelihood) detection method.

In general, PRML technology has been employed in digital communications for many years, and is now applied to hard disk drives (HDDs), which are widely used as computer auxiliary memory devices. The adoption of the PRML detection method in the HDD greatly contributed to the implementation of the system to enable high capacity and high speed access in the HDD.

Invented by inventor William L. Abbott et al., US Pat. Is disclosed.

PRML detection hard disk drives form digital channels for signal recording and reading, and the PLLs used together for PRML detection also use a typical digital PLL. The characteristics of the PRML detection method employed in the hard disk drive are largely characterized by equalized and sampled data that produces a desired waveform by appropriately controlling intersymbol interference (ISI) caused by an increase in linear density. The sequence is summarized in terms of sequence detection, digital gain and timing control to recover data using a Viterbi Algorithm. The PRML detection technique is implemented in hardware in a read / write channel circuit of a hard disk drive. For example, the equalizer for the equalization, the Viterbi decoder for sequence detection, the gain for digital gain and timing control are implemented. And timing control circuits. These configurations are the circuits of the PRML lead channel. The configuration of the PRML lead channel is already known, and an example thereof includes SILICON SYSTEMS STORAGE PRODUCTS 1994 DATA BOOK.

On the other hand, the invention was invented by inventor Yoo Seung-jun and assigned to the applicant of the present application and filed with a patent application dated 1997-May-Date No. 1977-59071 (Invention: Data Restoration Apparatus and Method of Optical Disc Playback System) and inventor Kim Il-kwon. No. 1998-28842 (name of the invention: data recovery device and reference voltage and phase error correction method in optical disc reproducing system) adopts PRML detection method. Disclosed is an optical disk device for restoring data.

The PLL circuit used in the optical disk device for restoring data adopting the PRML detection method cannot use the PLL circuit used in the HDD as it is. In general, the PLL device in the PRML lead channel circuit used in the HDD uses a typical digital PLL. That is, a method of restoring a data clock by digitally detecting a zero cross point of an input signal read from a disk and locking an analog-to-digital converter (ADC) clock. However, this method is complicated and difficult to lock the PLL clock due to the characteristics of the EFM (Eight to Fourteen Modulation) signal to apply to an optical disk device such as a DVD device employing the PRML detection method.

Accordingly, an object of the present invention is to provide a PLL device suitable for an optical disk device of a PRML detection method.

Another object of the present invention is to provide a PLL device for stably restoring data in a PRML detection optical disk device.

In accordance with the above object, the present invention provides an analog / digital conversion unit for converting a signal read by a pickup of an optical disk device into a digital signal of a predetermined bit in a phase locked loop device in an optical disk device employing a PLM detection method. A voltage controlled oscillator for outputting a frequency- and phase-controlled clock based on a predetermined control voltage to the analog / digital converter and a data recovery unit of a PLM detection method at a later stage, and comparing the signal read from the pickup with a predetermined slice level. A pulse signal generator for generating a pulse signal and a sync pattern section are found in the digital signal, and the clock is counted during the sync pattern section to determine whether the number is required for the sync pattern section. Outputs a frequency error signal and counts the number of clocks counted during the A frequency error detection unit for outputting a frequency lock detection signal if it matches the number required for the pre-pattern section, and between a clock closest to a zero crossing point appearing as the digital signal is sliced by the slice level and a predetermined edge of the pulse signal. A phase error detector for detecting a phase difference and outputting a phase error signal according to the present invention, a selector for selectively outputting the frequency error signal and a phase error signal according to whether the frequency lock detection signal is applied or not, And a loop filter which loop-filters an error signal and provides the voltage-controlled oscillator with a control voltage.

1 is a block diagram of a phase locked loop (PLL) device according to an embodiment of the present invention;

2 is a detailed block diagram of a frequency error detector (FD) 16 according to an embodiment of the present invention;

3 is a detailed block diagram of a phase error detector (PD) 18 of FIG. 1 according to an embodiment of the present invention;

4 is a block diagram of a PLL device according to another embodiment of the present invention;

5 is a detailed block diagram of the PD 18 of FIG. 4 according to another embodiment of the present invention;

6 is a waveform diagram of an RF IN signal applied to the AGC circuit 10 of FIG. 1 and an EFM pulse signal EFM_PLS output from the EFM slicer 26;

7A and 7B are timing diagrams of the parts of the PD 18 of FIG. 3 for an example of when the phase is slow and when the phase is fast;

8A and 8B are timing diagrams of the parts of the PD 18 of FIG. 5 for an example of when the phase is slow and when the phase is fast.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are denoted by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

FIG. 1 is a block diagram of a PLL device according to an embodiment of the present invention, FIG. 2 is a block diagram of a concrete detector 16 according to an embodiment of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention. Concrete block diagram of PD (Phase Detector) 18.

In Fig. 1, the RF IN signal is an EFM signal read by the pickup, which is a signal composed of 3T to 14T as an example of DVD. Here, T means the length of one clock pulse. Among the configured signals, the 14T signal means a synchronization pattern. When the sign of the RF IN signal is inverted 512 times, one 14T signal is necessarily present in the signal section. According to the preferred embodiment of the present invention, the RF IN signal is composed of 3T to 14T, the synchronization pattern is 14T, and if the sign of the RF IN signal is inverted 512 times, there is necessarily one in the signal interval. It is to be understood that the contents thereof may be changed or modified.

The EFM signal is automatically adjusted by the AGC (Automatic Gain Control) circuit 10 and then simultaneously applied to the ADC (Analog to Digital Converter) 12 and the EFM Slicer 26. The ADC 12 outputs the signal (analog signal) output from the AGC circuit 10 as an n-bit digital signal in response to the clock CLK output from the voltage controlled oscillator (VCO) 24. When the RF IN signal (shown in FIG. 6) is greater than the slice level, the MSB (Most Significant Bit) of the n-bit digital signal is represented by "1", and when the RF IN signal is less than the slice level, The MSB of the n bit digital signal is represented by " 0 ". The output signal of the ADC 12 is applied to the PRML core 14, FD (Frequency error Detector) 16, and PD (Phase error Detector) 18. The PRML core 14 restores data in a PRML detection method.

On the other hand, the output signal of the AGC circuit 10 is applied to the EFM slicer 26. The EFM slicer 26 slices the RF IN signal to slice level " 0 " as shown in Fig. 6 and outputs the EFM pulse signal EFM_PLS. do. The EFM pulse signal EFM_PLS is applied to the PD 18.

The FD 16 finds the sync pattern section (14T signal section) by inputting the output signal of the ADC 12, counts the clock pattern during the sync pattern section, and counts the number 14T required for the sync pattern section. And the frequency error signal FD_ER corresponding to the difference is output. The frequency lock detection signal FD_LK_DET is outputted when the number of clocks CLK counted during the synchronization pattern period matches the number required for the synchronization pattern period.

The operation of the FD 16 will be described in more detail with reference to FIG. 2, which is a specific block diagram of the FD 16 according to an embodiment of the present invention. The FD 16 shown in FIG. 2 includes a code inversion detecting unit 30, a code inversion detecting unit 32, a Tmax1 counter 34, a Tmax2 counter 36, an update control unit 38, a Tmax latch unit 40, And a comparator 42.

In Fig. 2, the sign inversion detecting unit 30 detects whether the sign is inverted by using the MSB of the output signal of the ADC 12. For example, if the MSB is changed from "1" to "0", the sign is detected as being inverted from (+) to (-). If the MSB is changed from "0" to "1", the sign is (- Is detected by reversing the sign from () to (+).

Each time the code inversion detection unit 30 detects a sign inversion of a signal, the sign inversion number counter 32 counts up the number of sign inversions in response thereto. When counting up to a maximum of 512 times, a count completion signal is output to the Tmax latch unit 40 and then initialized to "0". The count up to 512 times is because there is always one sync pattern in the signal section 512 reversed as described above.

On the other hand, when the sign inversion detection unit 30 detects the sign inversion of the signal from (+) to (-), the Tmax1 counter 34 is operated, and the signal from the sign inversion detection unit 30 to (-) → (+) is reversed. The Tmax2 counter 36 is activated when the sign reversal is detected. When the Tmax1 counter 34 operates, the Tmax1 counter 34 counts the number of clocks CLK output from the VCO 24 of FIG. 1 during the negative sign period of the signal. For example, referring to FIG. 6, the number of clocks CLK output from the VCO 24 is counted during the interval between the previous zero cross point ZCP1 and the current zero cross point ZCP2. When the Tmax2 counter 36 operates, the Tmax2 counter 36 counts the number of clocks CLK output from the VCO 24 of FIG. 1 during the positive sign period of the signal. For example, referring to FIG. 6, the number of clocks CLK output from the VCO 24 is counted during the interval between the previous zero cross point ZCP2 and the current zero cross point ZCP3.

The update control unit 38 compares the count value CNT1 or CNT2 output from the Tmax1 counter 34 or the Tmax2 counter 36 with the previously updated maximum count value OUCNT, and latches a large value in the Tmax latch unit 40. To be. That is, the large value is latched to the new maximum count value NUCNT by comparing the count value CNT1 and the updated maximum count value OUCNT, and the large value is latched to the new maximum count value NUCNT by comparing the count CNT2 and the updated maximum count value OUCNT. do. The Tmax latch unit 40 latches a new maximum count value NUCNT to be updated by the update control unit 38, and is updated every time the count values CNT1 and CNT2 are output from the Tmax1 counter 34 and the Tmax2 counter 36. The value OUCNT is provided to the update control unit 38. In addition, the Tmax latch unit 40 receives a count completion signal from the sign inversion count counter 32 and outputs the maximum count value NUCNT updated thereafter to the comparison unit 42.

The comparator 42 compares the clock number 14T corresponding to the preset synchronization pattern with the maximum count value NUCNT output from the Tmax latch unit 40 and outputs the difference value as the frequency error signal FD_ER. The comparison unit 42 outputs the frequency lock detection signal FD_LK_DET in binary logic " H " state when the clock number 14T corresponding to the synchronization pattern and the maximum count value NUCNT output from the Tmax latch unit 40 match. Otherwise, the frequency lock detection signal FD_LK_DET is output in binary logic " L " state. The frequency error signal FD_ER output from the Tmax latch unit 40 is applied to an input terminal 0 of the multiplexer 20 of FIG. 1, and the frequency lock detection signal FD_LK_DET is applied to a selection terminal S of the multiplexer 20. Is approved.

Returning to FIG. 1, when the frequency lock detection signal FD_LK_DET is applied in binary logic " L " state, the multiplexer 20 selects and outputs the frequency error signal FD_ER provided by the FD 16 to the loop filter 22. . Since the loop filter 22 loop-filters the output of the multiplexer 20 to apply a control voltage to the VCO 24, the VCO 24 correspondingly outputs a clock-controlled clock CLK with the ADC 12 and the PRML. Output to the core 14. The FD 16 of FIG. 2 outputs a frequency error signal FD_ER which causes the frequency of the clock CLK to be up when the number of clock CLKs output from the VCO 24 is less than 14T, and outputs it from the VCO 24. If the number of clocks CLK is greater than 14T, a frequency error signal FD_ER is output to cause the frequency of the clock CLK to be down.

When the PLL device of FIG. 1 repeatedly performs such frequency error correction control, 14 clock CLKs enter the synchronization pattern section (14T signal section) of the RF IN signal. As a result, the frequency lock detection signal FD_LK_DET is received by the FD16. Output as logic "H". This means that it is a frequency lock. When the frequency lock detection signal FD_LK_DET is applied to the selection terminal S of the multiplexer 20 as logic "H" as described above, the multiplexer 20 selects the input terminal 1. Accordingly, the loop filter 22 of FIG. 1 is provided with a phase error signal PD_ER, which is an output signal of the PD 18.

After the frequency lock, the PD 18 of FIG. 1 detects a phase difference between the zero cross point of the RF IN signal and the clock CLK closest to the zero cross point, and outputs a phase error signal PD_ER. An operation of the PD 18 of FIG. 1 for outputting the phase error signal PD_ER will be described in more detail with reference to FIGS. 3, 7A, and 7B.

3 is a detailed block diagram of a phase error detector 18 shown in FIG. 1 according to an exemplary embodiment of the present invention, and FIGS. 7A and 7B are diagrams illustrating an example of a case where the phase is slow and fast. Is a timing diagram of each part of the PD 18.

The PD 18 shown in FIG. 3 is composed of a sign inversion detector 50, an absolute value comparison unit 52, a toggle pulse generator 54, and a phase comparator 56. FIG.

The n-bit digital signal output from the ADC 12 of FIG. 1 is applied to the code inversion detecting unit 50 and the absolute value comparing unit 52 of the PD 18 shown in FIG. The code inversion detecting unit 50 detects whether the code is inverted using the MSB in the n-bit digital signal. For example, if the MSB is changed from "1" to "0", it is detected that the sign is inverted from (+) to (-). If the MSB is changed from "0" to "1", the sign is It detects that the sign is reversed from (-) to (+). When the sign inversion detecting unit 50 detects the sign inversion, the sign inversion detecting signal B1 is output to the absolute value comparing unit 52 at the clock timing immediately after the zero crossing point ZCP as shown in FIGS. 7A and 7B.

The absolute value comparison unit 52 compares the absolute value of the digital signal of the clock immediately before the sign inversion with the absolute value of the digital signal of the clock immediately after the sign inversion in response to the code inversion detection signal of the code inversion detecting unit 50, The pulse signal B2 is output at a timing one clock after the clock timing of. This will be described below with reference to FIGS. 7A and 7B when the phase is slow and when the phase is fast.

First, as shown in FIG. 7A, when the phase of the clock CLK is slower than the zero crossing point ZCP, the absolute comparison unit 52 performs the digital signal at the clock timing ① immediately before the sign inversion and the clock signal ② at the clock timing ② after the sign inversion. The absolute value is compared, and the pulse signal B2 is output at the clock timing ③ after one clock at the clock timing ② for the smaller absolute value. Next, as shown in FIG. 7B, when the phase of the clock CLK is faster than the zero crossing point ZCP, the absolute value comparing unit 52 performs the digital signal at the clock timing ① 'immediately before the sign inversion and the clock timing ②' after the sign inversion. And compares the digital signal of absolute value, and outputs pulse signal B2 at clock timing ② 'one clock after the clock timing ①' with respect to the absolute value.

When the pulse signal B2 is output from the absolute value comparing unit 52, the toggle pulse generating unit 54 toggles the binary logic state of the previous pulse signal TGP as shown in FIGS. 7A and 7B. The toggle pulse TGP generated by the toggle pulse generator 54 is applied to the phase comparator 56 together with the EFM pulse signal EFM_PLS output from the EFM slicer 26 of FIG. After the comparison, the phase error signal PD_ER corresponding to the difference is output.

7A outputs a phase error signal PD_ER as shown in FIG. 7A to increase the phase of the clock CLK when the phase is slow as shown in FIG. 7A, and decreases the phase of the clock CLK when the phase is high as shown in FIG. 7B. Outputs the phase error signal PD_ER as shown in FIG. In the example of FIGS. 7A and 7B, when the pulse of the phase error signal PD_ER is represented by the same pulse as one clock period, it means that the phase is locked.

7A and 7B, the phase error signal PD_ER is applied to the loop filter 22 through the multiplexer 20 which selects the input stage 1 by the frequency lock detection signal FD_LK_DET = "H" and loop filtered. The control voltage loop-filtered by the loop filter 22 is applied to the VCO 24, and the VCO 24 outputs a clock CLK whose phase is controlled accordingly to the ADC 12 and the PRML core 14.

If the phase correction for the clock CLK is repeatedly performed in the manner as described above, the clock CLK output from the VCO 24 is eventually phase locked. That is, the clock CLK coincides with each zero cross point of the RF IN signal. Thus, the stable clock CLK can be applied to the ADC 12 and the PRML core 14 at the rear end of FIG.

Hereinafter, a PLL device and an operation thereof according to another embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a PLL device according to another embodiment of the present invention, and FIG. 5 is a detailed block diagram of the PD 18 of FIG. 4 according to another embodiment of the present invention.

The PLL device block configuration shown in FIG. 4 has a configuration similar to that of the PLL device block configuration shown in FIG. Different from the block configuration of FIG. 1, the signal applied from the ADC 12 to the PD 18 is an MSB signal. That is, although the n-bit digital signal is provided from the ADC 12 to the PD 18 in the configuration of FIG. 1, the MSB signal of the n-bit digital signal from the ADC 12 to the PD 18 is provided in the configuration of FIG. 4. Is provided. The detailed block configuration of the PD 18 according to the configuration as shown in FIG. 4 is different from the detailed block configuration of the PD 18 based on FIG. 1. The detailed block configuration of the PD 18 according to FIG. 4 is FIG. 5. Meanwhile, the detailed configuration of the FD 16 in the block configuration according to FIG. 4 is the same as the detailed block configuration of the FD 16 shown in FIG.

The PD 18 shown in FIG. 5 includes an exclusive logical sum gate 60, first and second di-type flip-flops 62 and 64, first and second switches 66 and 68, and a charge / discharge unit 70. It is composed. The MSB signal of the n-bit digital signal output from the ADC 12 of FIG. 4 is applied to one input terminal of the exclusive OR gate 60, and the EFM slicer 26 of FIG. 4 is applied to the type force terminal of the exclusive OR gate 60. The EFM pulse signal EFM_PLS output from is applied. The output of the exclusive OR gate 60 is connected to the input terminal D of the first de-type flip-flop 62 and is provided as a selection signal of the first switch 66. An input terminal 64 of the second di-type flip-flop 64 is connected to an output terminal Q of the first di-type flip-flop 62, and an output of the second di-type flip-flop 64 is connected to the second switch 68. Is provided as a selection signal. One end of the first switch 66 is connected to the power supply voltage Vcc and the other end thereof is connected to the second switch 68 having one end connected to the ground. The node 69 between the first switch 66 and the second switch 68 is connected to a charge / discharge unit 70 composed of a resistor R and a capacitor C. The output of the charge / discharge unit 70 is a phase error signal PD_ER. Becomes

Referring to the configuration of FIG. 5, the PD 18 outputs the phase error signal PD_ER in response to the MSB signal among the n-bit digital signals output from the ADC 12 provided to the PD 18. It will be described later with reference to Figures 8a and 8b. 8A and 8B are timing diagrams of the parts of the PD 18 of FIG. 5 for an example of when the phase is slow and when the phase is fast.

Of the n-bit digital signals output from the ADC 12 of FIG. 4, the MSB signal is applied to one input terminal of the exclusive OR gate 60 of FIG. 5, and the EFM pulse signal EFM_PLS output from the EFM slicer 26 of FIG. It is applied to the type force stage of the exclusive OR gate 60. 8A and 8B show an example of the MSB signal and the EFM pulse signal EFM_PLS of the digital signal. The exclusive OR gate 60 performs an exclusive OR gate of the MSB signal of the digital signal and the EFM pulse signal EFM_PLS to output the output signal A1 as shown in FIGS. 8A and 8B.

First, when the phase of the RF IN signal is slow as shown in FIG. 8A, the operation of outputting the phase error signal PD_ER by the PD 18 of FIG. 5 is as follows. When the RF IN signal is slow in phase as shown in FIG. 8A, the output signal A1 as shown in FIG. 8A is output from the exclusive logic sum gate 60. In the "H" state of the output signal A1, the first switch 66 is used. Comes on. Accordingly, the power supply voltage Vcc is charged in the charge / discharge unit 70. On the other hand, the first and second di-type flip-flops 62 and 64 operating at the falling edge of the clock CLK are always maintained in the "L" state. Therefore, since the output signal A3 of the second di-type flip-flop 64 always shows the "L" state as shown in Fig. 8A, the second switch 68 is turned off. As a result, in the charging and discharging unit 70, as shown in FIG. 8A, the phase error signal PD_ER for increasing the phase of the clock CLK is output to the input terminal 1 of the multiplexer 20 of FIG. 4.

Next, when the phase of the RF IN signal is fast as shown in FIG. 8B, an operation of outputting the phase error signal PD_ER by the PD 18 of FIG. 5 will be described. When the RF IN signal is out of phase as shown in FIG. 8B, the output signal A1 as shown in FIG. 8B is output from the exclusive logic sum gate 60. In the “H” state of the output signal A1, the first switch 66 is output. Comes on. Accordingly, the power supply voltage Vcc is charged in the charge / discharge unit 70. On the other hand, the first de-type flip-flop 62 operating at the falling edge of the clock CLK latches the logic " H " state when the output signal A1 of the exclusive OR gate 60 is in the " H " state. The same output signal A2 is output, and the second di-type flip-flop 64 outputs the output signal A3 of FIG. 8B in response. When the output signal A3 of the second di-type flip-flop 64 is output as "H", the second switch 68 is turned on so that the current charged in the capacitor C of the charging / discharging unit 70 causes the second switch 68 to turn off. Discharged to ground. Therefore, in the charging and discharging unit 70, a phase error signal PD_ER is output to the input terminal 1 of the multiplexer 20 of FIG. 4 in a waveform as shown in FIG. 8B to slow the phase of the clock CLK. The first and second di-type flip-flops 62 and 64 in FIG. 5 prevent the first switch 66 and the second switch 68 from being turned on at the same time.

In the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be defined by the equivalent of claims and claims.

As described above, the present invention provides a stable PLL device suitable for an optical disk device of a PRML detection method to stably perform data restoration at a later stage.

Claims (7)

In a phase locked loop device in an optical disk device employing a PLM detection method, An analog / digital converter for converting a signal read by the pickup of the optical disk device into a digital signal of a predetermined bit; A voltage controlled oscillator for outputting a frequency- and phase-controlled clock based on a predetermined control voltage to the analog / digital converter and a data recovery unit of a PLM detection method at a later stage; A pulse signal generator for generating a pulse signal by comparing the signal read from the pickup with a predetermined slice level; Finding a sync pattern section in the digital signal, counting the time period during the sync pattern section as the clock to determine whether the count is required for the sync pattern section, outputting a frequency error signal according to the difference, and synchronizing the sync pattern section. A frequency error detection unit for outputting a frequency lock detection signal if the number of clocks counted during the period matches the number required for the synchronization pattern section; A phase error detection unit for detecting a phase difference between a clock closest to a zero crossing point appearing as the digital signal is sliced by the slice level and a predetermined edge of the pulse signal, and outputting a phase error signal accordingly; A selection unit for selectively outputting the frequency error signal and the phase error signal according to whether the frequency lock detection signal is applied; And a loop filter for loop filtering the error signal selected by the selector to provide the voltage control oscillator with a control voltage. The method of claim 1, wherein the frequency error detection unit A code inversion detector for detecting a code inversion of the digital signal using the most significant bit of the digital signal; A code inversion counter for counting the number of sign inversions of the digital signal up to a preset count value and outputting a count completion signal; When the code inversion detection unit detects a code inversion from the (+) sign to the (-) sign, the number of clocks output from the voltage controlled oscillator is counted and output as the first count value during the (-) sign section of the digital signal. The first counter, When the code inversion detection unit detects a code inversion from the (-) sign to the (+) sign, the number of clocks output from the voltage controlled oscillator is counted and output as a second count value during the (+) sign section of the digital signal. The second counter, An update controller for controlling the first count value or the second count value to be updated to a new maximum count value by comparing the first count value or the second count value with an already updated maximum count value; When the first count value or the second count value is applied to the update controller, the already updated maximum count value is provided to the update controller, and when a count completion signal is applied from the code inversion counter, a new maximum value is updated. A maximum count value latch unit for outputting a count value, The maximum count value output from the maximum count value latch unit is compared with the number of clocks corresponding to a preset synchronization pattern, and the difference is output as the frequency error signal, and the maximum count value and the number of clocks corresponding to the preset synchronization pattern are output. And a comparator for outputting the frequency lock detection signal to the selector if there is a match. The method of claim 1, wherein the phase error detection unit A code inversion detector for detecting a code inversion of the digital signal using the most significant bit of the digital signal; In response to the sign inversion detection of the sign inversion detector, the absolute value of the digital signal of the clock immediately before the sign inversion is compared with the absolute value of the digital signal of the clock immediately after the sign inversion, and the pulse signal is output at the clock first edge timing of the absolute value smaller. With an absolute value comparison section And a phase comparator for comparing the phase between the pulse signal of the pulse signal generator and the pulse signal of the absolute value comparator and outputting the phase error signal according to the difference. The phase locked loop device according to claim 1, wherein the slice level is a zero level. The method of claim 1, wherein the phase error detection unit An exclusive-OR gate for outputting the most significant bit of the digital signal and the pulse signal of the pulse signal generator as a gate signal; A latch unit for latching the gate signal and outputting the delayed signal in response to a second edge of the clock; A phase error signal generation unit configured to charge an internal charging unit according to the gate signal and discharge the ground error signal to the ground charged in the charging unit in response to a gate signal delayed by the latch unit; Synchronous loop device. The method of claim 5, wherein the phase error signal generation unit A first switch connected to a power supply voltage and selected by the gate signal; A second switch having one end connected to the other end of the first switch and the other end connected to the ground, and selected by an output of the latch unit; Phase integrating loop device comprising an integrator connected to the node between the first switch and the second switch. The method of claim 5, wherein the latch unit A first de flip flip-flop for latching and outputting the gate signal in response to a second edge of the clock; And a second di flip-flop configured to latch and output an output signal of the first di flip-flop in response to the clock second edge.