KR100332470B1 - Control circuit for multi-density synchronous-link dynamic random access memory - Google Patents

Abstract

The present invention relates to a multi-density sync-link DRAM (hereinafter referred to as SLDRAM) control circuit, and according to various packet formats of SLDRAM implemented for multi, it is easy to change an address input to a pin. By implementing an address shifter to control, the present invention relates to a technique that can effectively control the address control that occurs when using a multi-density SLDRAM in one system.

Description

Multi-density Sink-RAM (SLDRAM) control circuit {Control circuit for multi-density synchronous-link dynamic random access memory}

The present invention relates to a multi-density sync-link DRAM (hereinafter referred to as SLDRAM) control circuit. The present invention relates to controlling an address input to a pin according to various packet formats of an SLDRAM implemented for multi. It's about technology.

In general, systems using SLDRAM have not been able to use multi-density SLDRAM.

In other words, when a plurality of DRAMs having different capacities are used in one system, the pins formed on the DRAMs are the same, but the input addresses are different according to the capacity of the DRAM. Only the memory to transfer it was employed.

Therefore, when using DRAMs of various capacities together in one system, a circuit is needed to control the case where different addresses are inputted on the same pin.

SUMMARY OF THE INVENTION In view of the conventional requirements as described above, the present invention uses a DRAM having a different capacity in one system by inputting a bank address corresponding to a packet format defined in each DRAM having a different capacity into the corresponding DRAM. The purpose.

1 is a schematic block diagram of a multi-density SLDRAM to which the present invention is applied;

2 (a, b, c) are packet format diagrams of respective SLDRAMs used in FIG. 1;

3 (a, b) is an address shifter circuit diagram according to the present invention.

<Description of the reference numerals for the main parts of the drawings>

1, 2, 3: SLDRAM 4: Control part

5: termination 41 to 44: flip-flop

The present invention for achieving the above object, a plurality of DRAM is installed in one system, the packet format is different; And

A control unit controlling a plurality of bank addresses to be input to each of the plurality of DRAMs according to each packet format of the plurality of DRAMs,

The control unit includes a plurality of latch means for shifting the plurality of bank addresses in response to a shift clock to output a bank address corresponding to a packet format of a corresponding DRAM to one pin, wherein one of the plurality of latch means includes the shift means. A clock is input, and the inverted clock of the shift clock is input to the other one of the plurality of latch means.

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a schematic block of a multi-density SLDRAM to which the present invention is applied can be illustrated as an example, as shown in FIG.

A control unit (4) for performing control such as address adjustment to be input to each of the SLDRAMs (1, 2, 3);

And termination (5).

The first SLDRAM 1 is an SLDRAM having a capacity of 64 M, three bank addresses BA, ten row addresses RA, seven column addresses CA, and the second SLDRAM 2 having the same capacity. SLDRAM requires 64M capacity, three bank addresses, eleven row addresses, and six column addresses.

The third SLDRAM 3 is an SLDRAM having a capacity of 128M and requiring four bank addresses, ten row addresses, and seven column addresses.

Each packet format defined in each SLDRAM of the above type is shown in FIG. 2 (a, b, c).

In the pin number 4 (CA4), the address inputted to the first SLDRAM 1 is divided into 'ID3', a bank address 2 (BA2), a row address 2 (ROW2), and a column address 4 (COL4). ID3, BA2, ROW3, and COL4 are input to CA4 of the second SLDRAM 2, and ID3, BA3, ROW3, and COL4 are input to CA4 of the third SLDRAM 3.

Even with the same pin CA4, an input address varies depending on the capacity of the SLDRAM and the memory cell array arrangement.

Therefore, a means for controlling the address as described above is required, and in the present invention, the control unit 4 includes an address shifter to control it.

In the address shifter means according to the present invention, as shown in FIG. 3 (a), the first flip-flop 41 receives the bank address 3 BA3 and outputs it to CA4 according to the enable of the shift clock. ;

And a second flip-flop 42 which receives bank address 2 BA2 and outputs it to CA4 according to the enable state of the inverted clock of the shift clock.

The address shifter shown in FIG. 3 (b) shows an address control state for another pin. The address shifter shown in FIG. 3 (b) is the same principle as that of FIG. 3 (a) and controls an address input to CA3.

A first flip-flop 43 which receives the bank address 2 BA2 and outputs it to CA3 according to the enable of the shift clock;

And a second flip-flop 44 which receives the bank address 1 BA1 and outputs it to CA3 according to the enable state of the inverted clock of the shift clock.

In the same manner as described above, when different SLDRAMs are inputted with different addresses through the same pin, all of them can be controlled.

Referring to the operation of the address shifter as described above, FIG. 3A corresponds to the CA4 terminal of the second and third SLDRAMs 2 and 3 in FIG. 2, and the SLDRAM currently operating is the second SLDRAM 2. In this case, the bank address 2 (BA2) may be output to the CA4 terminal.

Therefore, the shift clock is input as a 'low' value so that the clock applied to the second flip-flop 42 may be a 'high' value. Then, the first flip-flop 41 is disabled to latch the bank address 3 BA3, and the bank address 2 BA2 input to the second flip-flop 42 is output to the CA 4 terminal to output the second SLDRAM 2. Is entered.

In contrast, when the third SLDRAM 3 is operating, the first flip-flop 41 operates by inputting the shift clock as a 'high' value.

Meanwhile, the shifter operation of FIG. 3 (b) is the same as that described above. This corresponds to the CA3 terminal of the second and third SLDRAMs 2 and 3, and when the first flip-flop 43 is enabled, the third SLDRAM ( Bank address 2 BA2 is input to CA3 of 3), and bank address 1 BA1 is input to CA3 of the second SLDRAM 2 when the second flip-flop 44 is enabled.

That is, the address is inputted to the designated terminal by performing address shifting according to the packet format of each SLDRAM.

For reference, in the present invention, only the right shifting has been described. However, when left shifting is required, this description is omitted as a technique that can be implemented by those skilled in the art, and the address shift operation for the remaining terminals is also omitted.

As described in detail above, the present invention implements an address shifter for easily controlling the address of each packet format input to a different SLDRAM in a system using a multi-density SLDRAM, so that a multi- By using the density SLDRAM, the address control generated can be effectively controlled.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, and various modifications, changes, additions, etc. will be possible to those skilled in the art within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (4)

A plurality of DRAMs installed in one system and having different packet formats; And A control unit for controlling a plurality of bank addresses to be input to each of the plurality of DRAMs according to each packet format of the plurality of DRAMs, The control unit includes a plurality of latch means for shifting the plurality of bank addresses in response to a shift clock to output a bank address corresponding to a packet format of a corresponding DRAM to one pin, wherein one of the plurality of latch means includes the shift means. A multi-density sync-link DRAM (SLDRAM) control circuit, comprising: a clock input; and a reversed clock of the shift clock is input to another one of the plurality of latch means. The method of claim 1, And said plurality of latch means is adapted to the number of DRAMs configured in said system. The method according to claim 1 or 2, And said plurality of latching means performs both right shifting and left shifting in accordance with the shift direction of said plurality of bank addresses. The method of claim 1, And said plurality of latching means comprises a D-flip-flop.