KR100331260B1 - Method of designing transistor of electrostatic protection circuit - Google Patents

Abstract

The present invention relates to a method of designing a transistor of an electrostatic protection circuit having a strong electrostatic immunity against CDM, which is characterized in that the length ratio of the wiring electrically connecting the gate electrode of the transistor to . That is, in order to reduce the ESD damage of the transistor to the charge Q charged by the wiring, the ratio of the length of the wiring to the gate electrode (Li / Lg) should be adjusted to a relatively large value on the right side. Accordingly, in the present invention, the breakdown voltage Vo of the gate insulating film of the transistor is increased, the operating voltage Vcc of the chip is lowered, and the parasitic capacitor Ci of the wiring is smaller than the parasitic capacitor Cg of the gate electrode. And the transistor in the electrostatic protection circuit is designed.

Description

Method of designing transistor of electrostatic protection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit of a semiconductor device, and more particularly, to a method of designing a transistor of an electrostatic protection circuit capable of preventing a damage of a gate electrode of a transistor caused by discharge of a charge stored by a parasitic capacitor existing in a chip .

The reliability of an integrated circuit for ESD (Electro Static Discharge) becomes an important issue because the degree of integration of the semiconductor memory device is increased and the size of the device becomes smaller and the internal circuit is destroyed by the gradually lower voltage. This is because submicron process technology makes electrostatic discharge worse by employing technologies such as thin oxide films, shallow junctions, small contact areas and short channels.

On the other hand, semiconductor devices often suffer fatal damage to devices due to high-voltage static electricity in various cases such as manufacturing process or circulation process. The process of damaging a device by static electricity has been largely described as a human body model and a mechanical model. Recently, a CDM (Charged Device Model) that is damaged by the charge accumulated inside the chip is also considered .

In this CDM, the charge is charged by the parasitic capacitor component existing inside the chip, and momentarily flows to the outside of the chip, causing the static damage. Most of the parasitic capacitors are the components existing in the junction layer , Electric charges are accumulated by the parasitic components existing in the wiring of the metal or the like.

To this end, the semiconductor device employs an electrostatic protection circuit for protecting the internal circuit of the semiconductor device from pulses at which high-voltage static electricity is discharged through the input pad.

1 is a circuit diagram showing a conventional electrostatic protection circuit which includes a resistor R1 connected between the input pad 10 and the internal circuit 30 and connected to the input pad 10 and a resistor R1 connected between the resistor R1 and ground A field transistor D1 connected in the form of a diode and another resistor R2 connected to the transistor D1 and an NMOS transistor having a source and a gate connected between the resistor R2 and the ground.

When the conductive pad is applied to the input pad 10, the electrostatic protection circuit reduces the peak value due to the delay caused by the resistors R1 and R2. In addition, when a low voltage is applied, the signal passes through the field transistor D1 to the ground. When a high voltage of several tens of volts or more is applied, the NMOS transistor is also discharged to the ground through the NMOS transistor, so that the internal circuit can be protected from the high voltage of the static electricity.

However, the electrostatic protection circuit is effective in protecting the gate insulating film in the case of the transistor existing in the vicinity of the pad, but has a limitation in protecting the gate electrode of other transistors existing in the chip.

In addition, in the case of logic circuits, the parasitic capacitor component of this wiring is also greatly increased while the chip size is gradually reduced. As a result, the design method of the transistor must be considered so that the internal circuit can be safely protected from the static electricity caused by the CDM to be.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of fabricating the same, which can prevent the CDM from damaging the gate insulating film of the transistor, by determining the proper length ratio between the gate electrode and the wiring connecting the gate electrode. And to provide a method of designing a transistor of an electrostatic protection circuit that can be safely protected.

1 is a circuit diagram showing a conventional electrostatic protection circuit,

2 is a vertical sectional view of a transistor for explaining a method of designing a transistor of an electrostatic discharge protection circuit according to the present invention.

Description of the Related Art [0002]

100: semiconductor substrate 102: element isolation film

110: transistor 120: connection plug

130: Wiring

According to an aspect of the present invention, there is provided a method of designing a transistor of an electrostatic discharge protection circuit connected to an input pad to protect an internal circuit from an external static electricity, the method comprising: As a condition of the above. Vc is the operating power of the chip, Ci is a capacitor per unit length existing in the wiring, Lc is the length of the gate electrode, Vo is the breakdown voltage of the gate insulating film between the gate electrode of the transistor and the substrate, Cg is a capacitor per unit length of the gate electrode.

In the method of designing the transistor of the electrostatic protection circuit of the present invention, the charge accumulated by the parasitic capacitors existing in the gate electrode and the wiring Q = (Cg x Lg + Ci x Li) x Vcc And the charge stored in the gate electrode of the transistor when the ground voltage is applied to the source / drain junction layer of the transistor in a state where the charge Q accumulated in the gate electrode and the wiring is distributed Q = Cg Lg Vg (Vg is the maximum voltage applied to the gate electrode).

Further, in order to prevent electrical damage to the gate electrode of the transistor when the charge accumulated by the parasitic capacitor is concentrated on the gate electrode of the transistor, Vg < Vo is preferable.

Therefore, according to the present invention, a simple model of the parasitic capacitor between the gate electrode of the transistor and the wiring connecting the gate electrode of the transistor is analyzed to prevent static damage by the CDM mechanism, so that the charge accumulated by the parasitic capacitor due to the wiring Is designed in accordance with the ratio of the length of the gate electrode and the length of the interconnection line, which can prevent circuit damage due to static electricity generated when the gate electrode is introduced into the gate electrode of the transistor.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a vertical cross-sectional view of a transistor for explaining a method of designing a transistor of an electrostatic discharge protection circuit according to the present invention. More specifically, FIG. 1 is a cross-sectional view of a transistor 110, .

The reference numeral 100 denotes a semiconductor substrate, and 102 denotes a device isolation film. Reference numeral 112 denotes a gate insulating film of the transistor, and 114 denotes a gate electrode. A vertical plug 120 connects the transistor 110 and the wiring 130 vertically.

In order to protect the gate insulating film 112 of the transistor 110 damaged by the CDM, the method of designing the transistor of the electrostatic protection circuit of the present invention includes a step of forming the gate electrode 114 and the plug The internal circuit can be safely protected from the static electricity by determining a suitable length ratio between the gate electrode 114 and the wiring 130 connected to the gate electrode 114 through the gate electrode 120. [

Vc is the operating power of the chip, Ci is a capacitor per unit length existing in the wiring, Lc is the length of the gate electrode, Vo is the breakdown voltage of the gate insulating film between the gate electrode of the transistor and the substrate, Cg is defined as a capacitor per unit length of the gate electrode.

On the other hand, the operation voltage of the chip is already defined as Vcc, and the charge Q can be accumulated by the parasitic capacitor existing in the gate electrode 114 and the wiring 130, which can be expressed by the following equation (2).

Q = (Cg x Lg + Ci x Li) x Vcc (2)

When the ground voltage is applied to the source or drain junction layer (not shown) of the transistor in a state where the accumulated charge Q is distributed in the gate electrode 114 and the wiring 130 of the transistor, And is instantaneously concentrated on the gate electrode 114 of the transistor when the gate insulating film 112 is damaged by the CDM.

In this case, the voltage induced in the gate electrode 114 increases from Vcc to the maximum voltage Vg applied to the gate electrode 114 of the transistor. This can be expressed by the following equation (3).

Q = Cg 占 Lg 占 Vg (3)

If the equation (2) and (3) are calculated for Vg, the following equation (4) can be obtained.

As described above, in order to prevent electrical damage due to the charge Q accumulated by the parasitic capacitors existing in the chip when the charge Q is concentrated on the gate electrode 114, the breakdown voltage Vo of the gate insulating film 112 of the transistor is set to be larger than Vg And the gate insulating film 112 is maintained in a stable state only when it has a large value (Vg < Vo).

Accordingly, substituting Equation (4) into the above Vg condition yields Equation (5).

And the ratio of the length of the gate electrode 114 of the transistor and the length of the wiring 130 electrically connecting the gate electrode 114 to the gate electrode 114, .

In order to reduce the ESD damage of the transistor with respect to the charge Q charged by the wiring 130, the value of the right side of the ratio of the length of the wiring 130 and the gate electrode 114 should be relatively large do. Thus, the breakdown voltage Vo of the gate insulating film 112 is increased and the operating voltage Vcc of the chip is lowered, so that parasitic capacitors Ci (n) of the wirings 130 are set higher than parasitic capacitors Cg of the gate electrodes 114 ) Is smaller than that of the transistor in the electrostatic protection circuit.

As described above, according to the present invention, in order to prevent deterioration of electrical characteristics of a transistor caused by discharging charges accumulated by a parasitic capacitor existing in a chip, a circuit of a semiconductor device Design.

Therefore, it is possible to prevent damage of the finished chip due to the CDM mechanism during the chip destruction due to the static electricity generated in the device manufacturing process or after completion of the manufacturing process.

Claims (4)

A method of designing a transistor of an electrostatic protection circuit connected to an input pad to protect an internal circuit from external static electricity, Wherein a length ratio of a gate electrode of the transistor to a wiring electrically connecting the gate electrode of the transistor is designed according to the following equation: Vg is the operating power of the chip, Ci is the capacitor per unit length existing in the wiring, Cg is the capacitance of the gate electrode, Capacitor per unit length of the gate electrode. The method for designing a transistor of an electrostatic discharge protection circuit according to claim 1, wherein the charge Q accumulated by the parasitic capacitor existing in the gate electrode and the wiring has the following formula: Q = (Cg x Lg + Ci x Li) x Vcc 2. The method of claim 1, wherein the charge Q accumulated in the gate electrode of the transistor when a ground voltage is applied to the source / drain junction layer of the transistor in the state that the charge Q accumulated in the gate electrode and the wiring is distributed, The method of designing a transistor of an electrostatic protection circuit, Q = Cg Lg Vg Vg is the maximum voltage applied to the gate electrode. 2. The method of claim 1, wherein Vg < Vo is provided to prevent electrical damage to the transistor when the charge accumulated by the parasitic capacitor is concentrated on the gate electrode of the transistor.