KR100330238B1 - Interleaving and deinterleaving apparatus and method for a communication system - Google Patents

Abstract

The present invention relates to an internal interleaving apparatus and method for use in a turbo encoder of a communication system. The interleaver for generating an L address smaller than 2 ^m x N _G virtual addresses to read the data from an interleaver memory having L data stored therein, sequentially stores the L input data. adding an offset value in a memory, and said input data size virtual address size has said integer number of the address generation area is provided to an integral multiple of 2 ^m, and each having a size of 2 ^m corresponds to the offset value in the address generation areas And an address generator for generating addresses other than the addresses to read the input data from the interleaver memory with the addresses generated from the address generation areas.

Description

Interleaving / Deinterleaving Device and Method of Communication System {INTERLEAVING AND DEINTERLEAVING APPARATUS AND METHOD FOR A COMMUNICATION SYSTEM}

The present invention relates to an interleaving / deinterleaving apparatus and method, and more particularly, to an interleaving / deinterleaving apparatus for a turbo coder used in a communication system (satellite system, ISDN, digital cellular, W-CDMA, IMT-2000, W-ATM). And to a method.

In general, a turbo coder is a type of error correcting code that is widely involved in improving reliability of a digital communication system. The turbo coders disclosed to date can be divided into parallel turbo coders and serial turbo coders. The parallel turbo encoder is a system that generates a parity symbol using two simple parallel chain codes on an input consisting of a frame of L information bit streams, and a RSC (component coder) as a component coder. Recursive Systematic Convolutional) code. The parallel turbo code has an internal interleaver between the components.

The interleaver is used to randomize a data string input to the turbo coder encoder in units of a predetermined size (frame) and to improve the distance property of a code word. In particular, it is expected to be used for the supplemental channel used as a data transmission channel in the air interface standardization process of the IMT-2000 (CDMA2000), which has recently attracted much attention. In addition, in the Universal Mobile Telecommunication System (UMTS) standardization process promoted by the European Telecommunication Standards Institute (ETSI), it is promising that a turbo coder is used in a channel through which user data is transmitted. Therefore, a specific implementation method of the interleaver for turbo code is urgently needed.

FIG. 1 is a diagram illustrating a structure of a general parallel turbo coder, which is disclosed in detail in a patent number US Pat. No. 5,446,747, issued on August 29, 1995, which is a patent for a turbo code.

The turbo encoder having the configuration as shown in FIG. 1 outputs the first frame encoder 111 without encoding the input frame data sequence, and encodes and outputs the input frame, and the second component encoder 113 by interleaving the input frame data sequence. It consists of an interleaver 112 for outputting and a second component encoder 113 for inputting and encoding the output of the interleaver. The first and second constituent encoders 112 and 113 may use a recursive systematic convolutional (RSC) encoder or a non-recursive systematic convolutional (NSC) encoder that is well known in the art. Such a constituent encoder may have an internal configuration that depends on the coding rate, the finite length k value, and the generated polynomial. The interleaver 112 has the same memory size as the maximum frame size and reduces the correlation between the information bits by changing the input order of the information bits input to the second component encoder 113.

Conventionally, various methods such as PN random interleaver, random interleaver, block interleaver, non linear interleaver, and S-Random interleaver are proposed as the internal interleaver 112 of the turbo coder. It became. However, these interleavers can be seen as algorithms designed with the focus on performance improvement as an academic field rather than an implementation point of view. Therefore, considering the implementation of the actual system in terms of hardware implementation complexity can be said to be the way to reconsider. Hereinafter, a description will be given of the technology, properties and problems of the conventional turbo coder interleaver.

The turbocoder basically depends on the role of the internal interleaver. In general, turbocoders increase performance as the input frame size (the number of information bits in one frame) increases. However, since the amount of computation required increases exponentially as the interleaver size increases, the actual implementation is impossible if the frame size is very large.

In general, experimental results show that random interleaver performs better than block interleaver. However, one of the problems in designing the random interleaver is that as the frame size varies and becomes larger, the size of the memory for storing the interleaver's mapping rule or address becomes too large. That is, the memory space for addressing is greatly increased. Therefore, if the size of the hardware is a problem, an address is generated at every symbol clock by using a certain rule that generates an index rather than a look-up table method of storing an interleaver's index. An address enumeration method of reading data is required.

Taken together, it is optimal to implement turbo interleaver in consideration of various interleaver sizes such as for IMT-2000 or Universal Telecommunication Mobile System (UTMS) and limited hardware implementation complexity. The interleaver must be designed to ensure performance. That is, an interleaver in which interleaving / deinterleaving is performed by a certain interleaving rule is required. In addition, the various interleaver properties (e.g., Distance Properity, Weight Properity, Random Properity, etc.) required in the turbo internal interleaver are required to be excellent.

In the CDMA-2000 standardization process or the UMTS standardization process, an interleaver with simple design and high performance as a turbo interleaver has not been proposed. In the case of the forward link and the reverse link given in the current CDMA-2000 standard specification, there are various types of logical channels, and various sizes of interleavers according to various data rates are also included. A large amount of memory is required to reflect faithfully. For example, in the CDMA2000 forward link transmission mode, an interleaver having a wide range of sizes ranging from a minimum of 144 bits / frame to a maximum of 36864 bits / frame is used.

As described above, the problems of the prior art are summarized as follows.

First, various methods such as PN random interleaver, random interleaver, block interleaver, nonlinear interleaver, and S-R random interleaver have been proposed as internal interleaver for conventional turbo codes. However, these interleavers can be seen as algorithms designed with the focus on performance improvement as an academic field rather than an implementation point of view. Therefore, when considering the actual system implementation, in addition to the above-mentioned conditions, hardware implementation complexity must be considered. Such an interleaver has not been proposed.

Second, since most of the existing interleaving methods are lookup table methods, the interleaving rules according to each interleaver size must be stored by the control unit (CPU, HOST) of the transceiver, so that a separate storage space in addition to the interleaver buffer is required on the CPU memory side. That is, one of the design problems is that as the frame size varies and increases, the size of the memory for storing the interleaver's index (mapping rule or address) becomes too large. That is, the memory space (hardware space) for addressing is greatly increased.

Third, the implementation of an interleaver that satisfies both distance and random properties was not easy.

Accordingly, an object of the present invention is to provide an apparatus and method for implementing an interleaver that can solve the problems of the prior art.

Another object of the present invention is to provide an interleaving / deinterleaving apparatus and method for satisfying a distance characteristic, a weight characteristic and a random characteristic which are characteristics of a turbo coder in a communication system.

It is still another object of the present invention to provide an apparatus and method for performing interleaving with a virtual address area having a size of 2 ^m × N (integer) by adding a specific value to input data in a communication system.

It is still another object of the present invention to provide an interleaving apparatus and method that does not initially generate an invalid address generated by a specific value added to input data for interleaving.

It is still another object of the present invention to provide a method for finding an optimal initial value of a PN sequence generator that generates a random address component for each partial region of an address of an internal interleaver of a turbo encoder.

An apparatus for generating L addresses smaller than 2 ^m x N _G virtual addresses for reading the data from an interleaver memory having L data stored therein for achieving the above objects, sequentially stores the L input data. the offset value in the interleaver memory and said input data by adding the offset value to a size of the virtual address size providing an integral multiple of 2 ^m, each 2 has said integer number of the address generation areas having the size of ^m and the address generation area And an address generator for generating addresses excluding the addresses corresponding to the readout device, wherein the input data is read from the interleaver memory with the addresses generated from the address generation areas.

1 is a block diagram showing a general turbo encoder.

2 is a block diagram of an interleaving apparatus of a communication system according to the present invention;

3 is a block diagram of a deinterleaving apparatus of a communication system according to the present invention;

FIG. 4 is a diagram illustrating the interleaving of data corresponding to the offset value when interleaving with the virtual address area obtained by adding an offset value to the size of input data according to the present invention.

5 is a view illustrating a state in which output data are concatenated by removing invalid symbols in FIG. 4; FIG.

FIG. 6 shows a pseudorandom generator with a generation polynomial of (1 + x + x6).

7 illustrates an interleaving apparatus according to a first embodiment of the present invention.

FIG. 8 is a diagram showing a detailed configuration of an address generator among the components of FIG.

9 is a diagram illustrating an interleaving address generation process according to the first embodiment of the present invention.

10 illustrates an interleaving apparatus according to a second embodiment of the present invention.

FIG. 11 is a timing diagram relating to the interleaving apparatus of FIG. 10. FIG.

12 is a view for explaining an example of OSV detection in the last PN generator.

13 is a diagram illustrating an address generation process according to a second embodiment of the present invention.

FIG. 14 is a diagram illustrating a procedure for obtaining an optimal initial state value of PN generators in a second embodiment of the present invention. FIG.

In order to find a turbo coder that can achieve the best performance in various frame sizes, considerations such as the number of memory (finite length k) of turbo coder, multiple generation polynomials, and optimal code rate There are so many. In addition, it is very time and effort to experimentally find a turbo coder that performs optimally without theoretically verifying how all these factors affect performance.

Therefore, the method for the actual implementation should implement some criteria that affect the performance and implement the interleaver in a way that satisfies the criteria as much as possible. These standard characteristics are as follows.

Distance property: The distance between adjacent codeword symbols must be maintained to some extent. Since this plays the same role as the codeword distance property of the convolutional code, it is preferable to design the distance as large as possible under the same conditions.

Weight Property: The weight of a codeword corresponding to a non-zero information word should be more than a certain amount. Since it plays the same role as the minimum distance property of the convolutional code, it is desirable to design the weight to be large under the same conditions.

Random Properity: The correlation coefficient between output word symbols after interleaving should be very low compared to the correlation factor between original input information symbols before interleaving. That is, randomization must be faithfully performed between output word symbols. This is a factor that directly affects extrinction information quality generated in iterative decoding.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention proposes an optimal interleaving / deinterleaving apparatus capable of satisfying the above-described interleaver property (distance property, weight property, random property, etc.) of the turbo coder.

In general, a turbo interleaved random interleaver is excellent. The larger the frame size, the better the performance. It is desirable to design the interleaver to improve the complexity while satisfying the performance of the random interleaver. To this end, in the present invention, a linear feedback shift register (LFSR) for generating a PN sequence is used, and a random number generated therefrom is used as an address. However, the following problem should be considered when using this method.

First, the PN sequence has a period of 2 ^m −1.

Second, turbocode processes input frame size units, and most frame sizes are not expressed as powers of two.

In order to solve this problem, the address generator of the turbocoder interleaver proposed by the present invention provides a minimum value (hereinafter referred to as an offset value OSV) when the size L of the input frame data to be interleaved is not represented by a power of two. In addition to the frame size L, the virtual interleaving size (N = L + OSV) is made an integer multiple of 2 ^m . The offset value is a value that converts the frame size into a binary number so that the number of consecutive '1's in the least significant bit becomes at least one or more. And so can the virtual frame size N of determined area so that the area to be represented by ^{_{(N G) × 2 m (}} N G) is obtained with the combination of m. For each combination, a pseudorandom address is generated for each sub-region having a size of 2 ^m , and the entire input frame data is interleaved by sequentially or randomly selecting an address generated pseudo-randomly in each sub-region. The number of regions N _G and m are calculated through computer simulation and search algorithm to optimally satisfy the interleaver properties.

For example, in the case where the frame size is 376 (101111000), a method of obtaining the offset value will be described. In this case, the frame size 376 (101111000) is converted into a binary number so that at least one number of 0s is obtained from the least significant bit. An offset value is added to the frame size, for example, 8 (1000). Therefore, the virtual interleaving size (virtual frame size) is 384. If an interleaving address is generated for the virtual interleaving size, unnecessary read addresses are generated as much as the added offset value. These addresses are called ' invalid addresses' . In the above example, if the offset value is added so that the input frame is represented by two powers without dividing by the number of regions, the virtual interleaving size is 512 and the offset value is 136. If the input frame size 4600 becomes large, the offset value 3592 to be added becomes very large, which complicates the processing of the invalid address. Therefore, an appropriate offset value is added so that the virtual interleaving size is ^2m × N _G.

In addition, it is necessary to appropriately divide the number of regions N _G , but if the number of regions becomes very large, the size of the region becomes small, and thus, the random property may deteriorate. In addition, if the number of regions is too small, the size of the region is large, and thus the size of the memory for storing the interleaver index (mapping rule or address) becomes too large.

The turbo interleaver according to the present invention permutates the order of input information bits in an offset-controlled pseudorandom manner and provides it to the input of the second component encoder. Accordingly, the interleaver structure according to an embodiment of the present invention includes an interleaver memory for storing input information bits and a virtual interleaver size obtained by adding a predetermined offset value to an input data size into several regions. A random address is generated for each region, and an offset control pseudo random interleaver block (Partial Reversal Interleaver + Comparator) is generated for generating an interleaving address by sequentially / randomly selecting random addresses generated for each region. In addition, the first and second constituent encoders of the turbo code exemplified in the present invention can be configured not only with the constituent encoders of the prior art but also by the constituent encoders proposed by CDMA2000 standardized by TIA and UMTS standardized by ETSI. It is not limited by the specific constituent encoders, such as the use of constituent encoders. In addition, the interleaver of the present invention can be utilized not only for the internal interleaver of serial turbo code but also for a channel interleaver.

When the terms used in the present invention are defined below, 'region' means each address region when the virtual interleaver size is divided, and 'group' is divided by invalid addresses generated by the added offset value. Loss means each address area. In addition, the interleaver according to the present invention is referred to as an Offset Controlled PN Interleaver (OCPNI).

2 and 3 show the basic configuration of the interleaver and deinterleaver according to the present invention.

Referring to FIG. 2, a configuration of an interleaver for interleaving frame data output from the first component encoder, the address generator 211 changes the order of data according to an input frame data size L and an input clock. A read address is generated for output to the interleaver memory 212. The interleaver memory 212 stores input data in order in the write mode, and outputs data according to the address provided by the address generator 211 in the read mode. The counter 213 inputs a clock and outputs the clock to the write address of the interleaver memory 212. As described above, the interleaver stores input data in order in the interleaver memory 212 in the write mode, and is stored in the interleaver memory 212 according to the read address generated by the address generator 211 in the read mode. Output the data. As another example, the data may be changed in the interleaver memory in the write mode in advance, and the data may be read out in order in the read mode and output to the second component encoder.

Referring to the configuration of the deinterleaver with reference to FIG. 2, the address generator 211 generates a deinterleaver memory 212 by generating a write address for restoring the original order of data by the input frame data size L and the input clock. To provide. The deinterleaver memory 212 stores input data according to the write address (write ADDR) provided from the address generator 211 in the write mode, and sequentially outputs the stored data in the read mode. The counter 213 inputs a clock and provides a read address (Read ADDR) for reading data from the deinterleaver memory 212 to the memory 212.

As described above, the deinterleaver is a reverse process of the interleaver, and all parts of the deinterleaver are completely identical in structure, and only the order of data input in the read / write mode is different. Therefore, the following description will focus on the interleaver.

Hereinafter, an interleaving apparatus according to a first embodiment of the present invention will be described.

The interleaving apparatus according to the first embodiment of the present invention performs interleaving by an algorithm such as Equation 1 (C-program).

{N = L + OSV;

i = 0;

/ * Find N = 2 ^m × N _G * /

for (ADDRESS_WRITE = 0; ADDRESS_WRITE <= 2 ^m -2; ADDRESS_WRITE ++)

{for (g = 0; g <= N _G -1; g ++)

{ADDRESS_READ [i] = [PNg (ADDRESS_WRITE) -1] + g * 2 ^m ;

if (ADDRESS_READ <= L-1) {

ADDRESS_READ [i] = ADDRESS_READ [i] -OFFSET (ADDERSS_READ [i], GTH);

i ++;

}

}

/ * Overwrite ADDRESS_READ with the same address as ADDRESS_WRITE * /

ADDRESS_WRITE = (2m-1);

for (g = 0; g <= N ^G -1; g ++)

{ADDRESS_READ [i] = ADDRESS_WRITE + g * 2 ^m -OFFSET (ADDRESS_WRITE, GTH);

i ++;

}

}

/ * OFFSET Generation Algorithm * /

function OFFSET (ADDRESS_READ, GTH) {

if (ADDRESS_READ <GTH [0]) OFFSET = 0;

else if (GTH [0] <ADDRESS_READ <GTH [1]) OFFSET = 1;

else if (GTH [1] <ADDRESS_READ <GTH [2]) OFFSET = 2;

else if (GTH [2] <ADDRESS_READ <GTH [3]) OFFSET = 3;

else if (GTH [3] <ADDRESS_READ <GTH [4]) OFFSET = 4;

else if (GTH [4] <ADDRESS_READ <GTH [5]) OFFSET = 5;

else if (GTH [5] <ADDRESS_READ <GTH [6]) OFFSET = 6;

else OFFSET = 7;

}

Read addresses (address_read) generated in Equation 1 are each N _G The number of read addresses belonging to each area is 2 ^m The number of random address components generated by the PN generator corresponding to each region is 2 ^m -1.

The read address ADDRESS_READ generated as shown in Equation 1 is mapped one-to-one with the original address, and the interleaver has the characteristics of the PN interleaver and the distance. In this case, OFFSET (I) is a function that determines which group the corresponding ADDRESS_READ belongs to from the given reference values and shifts the address by the corresponding offset.

If data is read by addressing the corresponding address of the interleaver memory without shifting the address by the offset, invalid data is read by the number of offset values. That is, in addition to the ADDRESS_READ corresponding to the input data of [0..L-1], eight invalid addresses corresponding to the offset [L..N-1] exist between the interleaving sequences. A description of this is shown in FIG. 4. If this is read as it is, OSV (= 8) more N data are transmitted than L symbols to be transmitted, so the address existing in between must be subtracted and the subsequent address concatenated. Description of this is shown in FIG. 5.

For example, if one of the various combinations that can represent the newly obtained virtual interleaver size N as N _G * 2 ^m is selected, the size of each address generation area is determined. The invalid address generated by osv is determined by the initial value of the PN generator generated in the last address generation region. The position of the invalid address (GTH: Group threshold) depends on how to generate the entire address. In other words, if an address is generated using the PN generator corresponding to each address generation area, how is the initial value of each PN generator and the address generated in each address generation area selected (either in sequence or regularity)? Are randomly determined). After all, if we know a given interleaving rule, we can know in advance the location of the invalid address caused by the added offset value.

This means that the interleaved stored data can be output in order except the invalid data corresponding to the invalid address. In detail, ADDRESS_READ corresponding to the last 8 stored data in [L..N-1] is always constantly determined by an interleaving rule. Therefore, the position of the interleaved invalid data can be known in advance. First, let the addresses of the tail eight data be D1, D2, D3, ..., D8 (that is, L..N-1). In addition, suppose that the interleaving address corresponding to each Di (i = 1..8) is Tk = PIRB (Di) and k = 1..8. Of course, D1 < D2 are not necessarily T1 < T2, but are arranged in any order. Therefore, for convenience, the index adjusted to be arranged in the order of T1 <T2 <.. <T8 is called j, and the address using the index is defined as Tj (j = 1..8). Then, the N interleaver spaces are divided into eight groups based on the address, and each Ti becomes a threshold value for separating the boundary. Here, the reference values should be excluded and the addresses should be concatenated. For example, ADDRESS_READ-0 in case of G0, ADDERSS_READ-1 in case of G1, ADDRESS_READ-7 in case of G7, all address generated is between [0..L-1]. Will have

Hardware implementation of the algorithm shown in Equation 1 is as shown in FIG. In particular, FIG. 7 illustrates a detailed configuration of an address generator for interleaving and reading data sequentially stored in the interleaver memory 112 according to an embodiment of the present invention.

Referring to the address generator 211 with reference to FIG. 7, the random address generator 221 generates and outputs random address components by a plurality of pseudo random generators (PN generators). The comparator 222 compares the random address output from the random address generator 221 with the reference values GTH (group reference values for grouping address areas), which are determined by the offset value, to determine which group the group belongs to. A value selection signal and the random address are output. In addition, the comparison unit 222 compares the random addresses output from the random address generator 121 with the group reference values GTH based on the offset value, and deletes the random addresses at the time when any one of them is identical. Do not print. The selector [unit] 223 selects and outputs a corresponding group value according to the selection signal. The subtractor 124 generates a read address for reading data from the memory 112 by subtracting a specific group value output from the selector 123 from the random address output from the comparator 122.

A detailed configuration of the random address generation unit 221 of the configuration of FIG. 7 is illustrated in FIG. 8.

Referring to FIG. 8, PN generators 811-8N1 generate pseudorandom sequences (address components: address components) for changing the order of data stored in corresponding address generation regions, respectively. Will output Here each pseudorandom generator initializes with different state values. The counter 816 outputs a selection signal for selecting an output of the first multiplexer 812. If it is assumed that the number of address areas is N _g , a selection signal of 0..N _g -1 is output. The selection signal may occur sequentially or randomly. When the random occurrence occurs, the selection signal is randomly generated by any pattern obtained by a predetermined algorithm . The multiplexer 812 selects and outputs the output of the pseudorandom generator based on the selection signal provided from the counter. Here, the output data of the multiplexer 812 is subtracted by 1 from the subtractor 818 and input to the second multiplexer. That is, since the pseudorandom generators do not generate an address 0 value, the random random generators are used to map random addresses from 0 by subtracting 1 from all generated values. The area counter 815 generates a counter corresponding to the size of the address generation area and outputs the counter to the comparator 814. The comparator 814 outputs a selection signal '1' to the second multiplexer 813 when the counter value provided by the area counter 815 corresponds to an area size (2 ^m ) −1. The second multiplexer 813, if the counter is 2 when ^m is equal to or smaller than -1, the output select the output of the first multiplexer 712, and the 2 ^m -1 il the comparator generated by the area counter 815 by the selection signal Selectively output 2 ^m -1 (area size -1) provided by 814. The address buffer 817 stores the output data of the counter 816 in the upper address area and the output data of the second multiplexer 813 in the lower address area. The address stored in the address buffer 817 is transferred to the comparator 222. Then, the comparator 222 determines which group the address belongs to and provides a group value selection signal to the selector 223. The selector 223 selects and outputs a corresponding group value according to the selection signal, and the subtractor 224 subtracts the selected group value from the address output from the comparator 222 to obtain a final read (read for interleaving) address. 212, data corresponding to the read address is read from the interleaver memory 112.

A process of generating a read address according to the configuration of FIGS. 7 and 8 will be described. The pseudorandom generators 811-8N1 generate a pseudorandom sequence by shifting a state value stored by clocking, and the first multiplexer 812 generates a state of the pseudorandom generator 811-8N1 by a selection signal provided from the counter 816. Selective output. When all of the states of the pseudorandom generators 817-8N1 are selected by the selection signal, the pseudorandom generators 811-8N1 again generate a pseudorandom sequence by shifting the stored state by clocking. In this way, the pseudorandom sequence output from the first multiplexer 812 is decremented by 1 and input to the second multiplexer 813. The pseudorandom sequence includes the area count of the size (2 ^m ) -1 value of the address generation area. It is passed as it is until it is reached and transferred to the lower area of the address buffer 817. On the other hand, when the area count reaches the size (2 ^m ) -1 value of the address generation area, the value (2 ^m ) -1 is transferred to the lower area of the address buffer 817. Meanwhile, values indicating the area (address generation area corresponding to the currently selected pseudo random generator) stored in the counter 816 are stored in the upper area of the address buffer 817. The address stored in the address buffer 817 is transferred to the comparator 222, and the comparator 222 provides a group value selection signal for determining which group the address belongs to to the selector 223. At this time, the address is outputted to the subtractor 224. Then, the selector 223 selects and outputs a corresponding group value according to the selection signal, and the subtractor 224 subtracts the corresponding group value from the address value output from the comparator 222 and provides a read address to the interleaver memory 212. On the other hand, if the address does not belong to any group, that is, if it corresponds to the reference values by the offset value, the comparator 222 considers the address as an invalid address and does not delete it. The interleaver memory 212 outputs data stored at a corresponding address according to the read address provided.

Hereinafter, an interleaving address generation procedure of the address generator 221 will be described with reference to FIG. 9. 9 is based on the algorithm of Equation 1 described above.

Referring to FIG. 9, the address generator 221 (general CPU) calculates parameter values for interleaving in step 911. When the input frame size is L, the virtual address size N is obtained by converting the frame size into a binary number and adding an appropriate value (offset value) such that at least one number of zeros comes out from the least significant bit. When the virtual address size N is expressed as the square root of 2 (2 ^m ) x N _g , the multiplier value m and N _g (hereinafter referred to as area number) are obtained by an algorithm described below. The parameters are predetermined values at the time of design, and these values are stored in the form of a lookup table, and the values are actually read from the lookup table when interleaving is performed.

In operation 913, the address generator 221 initializes the write address ADDRESS_WRITE to 0, and initializes the area index g to 0 in operation 815.

After the initialization is performed, the address generator 221 calculates a random address using a pseudo random sequence in operation 915 by the following equation. '(ADDRESS_READ = [(PN _g (ADDRESS_READ_WRITE) -1] + g * 2 ^m ' where PN _g (ADDRESS_READ_WRITE) represents a function for generating a pseudorandom sequence, and -1 means the generated pseudorandom sequence. + G * 2 ^m 'is for mapping the generated pseudorandom sequence to each corresponding region, i.e., if the region index g is 0, the generated pseudorandom sequence is mapped to region 0. If the region index is 1, it is mapped to region 1.

In step 919, the address generator 221 calculates the final read address using the following random address. '(ADDRESS_READ = ADDRESS_READ-OFFSET (ADDRESS_READ)' Here, the equation is an address calculated by determining which group the read address belongs to and subtracting a group value corresponding to the group, wherein the group is a group reference value by an offset ( = Invalid address) For example, if the read address corresponds to group 1, 1 is subtracted from the read address, and if it corresponds to group 2, 2 is subtracted.

In step 921, the address generator 221 checks whether the area index g has reached the area number N _g −1. In this case, when it is determined that the region index has reached N _g −1, the address generator 221 proceeds to step 923. When it is determined that the region index has not reached N _g −1, the address generator 221 proceeds to step 925. Increment the index by 1 and return to step 817 above.

On the other hand, the address generator 221 which detects that the area index has reached the area number-1 has a write address ADDRESS_WRITE of 2 ^m −2 (an address that can be generated by one pseudo random generator) in step 923. Check that the number is reached. Here, the write address corresponds to the area count described above. In this case, when it is determined that the write address has reached the 2 ^m −2 value, the address generator 221 proceeds to step 929. When it is determined that the write address has not reached the 2 ^m −2 value, the address generator 221 In step 927, the write address is increased by 1 and the flow returns to step 915.

On the other hand, the address generator 221 which detects that the write address has reached the 2 ^m −2 value maps the write address to the read address of each region using the following equation in step 929 and terminates the program. 'ADDRESS_WRITE = 2 ^m -1, ADDRESS_READ = ADDRESS_WRITE + g * 2 ^m -OFFSET (ADDRESS_WRITE)' That means that the last write address is used as a read address. ^Since only the number of ^m -1 is generated, the last remaining address is used as the read address as the value of the write address.)

Tables 1 and 2 show OCPNI design parameters corresponding to each rate set when the interleaving method according to the present invention is applied to an IMT-2000 system.

Rateset1 @ 19.2kbps @ 38.4kbps @ 76.8kbps @ 153.6kbps @ 307.2kbps Interleaver size L 376 760 1528 3064 6136 Offset Value (OSV) 8 8 8 8 8 N = L + OSV 384 768 1536 3072 6144 m 6 7 8 9 10 N _g 6 6 6 6 6 Initial parameter 101011 1010110 10101101 101011010 1010110101 010100 0101001 01010010 010100101 0101001010 111011 1110110 11101101 111011010 1110110101 101111 1011111 10111110 101111101 1011111010 011101 0111010 01110101 011101010 0111010101 011010 0110101 01101010 011010101 0110101010 GTH
{t0, t1, t2,
t3, t4, t5, t6, t7} {23,41,65,
107,119,131,
269,383} {47,77,191,
335,401,425,
641,767} {491,599,737,
755,1187,1211,
1265,1535} {659,1373,2027,
2447,2531,2825,
2861, 3071} {881,2159,2429,
2807,4307,4559,
4931,6143} PN-generated polynomial p (x) [1100001] [10010001] [101110001] [1000100001] [10010000001]

Rateset2 @ 28.8kbps @ 57.6kbps @ 115.2kbps @ 230.4kbps @ 460.8kbps Interleaver size L 568 1144 2296 4600 9208 Offset Value (OSV) 8 8 8 8 8 N = L + OSV 576 1152 2304 4608 9216 m 6 7 8 9 10

N _g 9 9 9 9 9 Initial parameter 101011 1010110 10101101 101011010 1010110101 010100 0101001 01010010 010100101 0101001010 101010 1010100 10101001 101010010 1010100101 011011 0110111 01101110 011011101 0110111010 001011 0010110 00101101 001011010 0010110101 111100 1111001 11110010 111100101 1111001010 110111 1101110 11011101 110111010 1101110101 100011 1000111 10001110 100011101 1000111010 110000 1100000 11000001 110000010 1100000101 GTH
{t0, t1, t2,
t3, t4, t5,
t6, t7} {107,305,332,
368,431,449,
467,575} {179,224,395,
611,710,746,
1070,1151} {485,647,854,
881,1529,1565,
1646,2303} {197,323,764,
818,2144,3185,
4166,4607} {2006,2384,2942,
6074,7991,8396,
8963,9215} PN-generated polynomial p (x) [1100001] [10010001] [101110001] [1000100001] [10010000001]

In Table 1 and Table 2, p (x) is a primitive polynomial of the pseudorandom generator obtained on GF (2), and the leftmost bit represents the coefficient of the 0th order of p (x). The rightmost bit represents the coefficient of the highest order term. That is, p (x) = [1100001] represents p (x) = 1 + x + x ⁶ . Here, the pseudorandom generator corresponding to the generated polynomial p (x) = 1 + x + x ⁶ is shown in FIG.

In general, initial values corresponding to respective regions are loaded into m shift register cells during initialization. Thereafter, as the clock progresses, the values of the registers are updated by the connected lines, and the 6-bit address is generated by the combination of the values (O / I) stored in the registers after the update. That is, when the content of the lowest order cell is called p [I] and the content of the highest order term is p [m], PN _g (ADDRESS_WRITE) is shifted when it is clocked by ADDRESS_WRITE at the initial time. Address (= p [1] 2 ^m converted from binary value ((p [1] p [2] ... p [m-1] p [m]) expressed as binary) to decimal ^-1 + ... + p [m] 2 ⁰ ). In addition, the address generated in the pseudorandom generator is generated with a period of 2 ^m −1. Further, since the initial values are not zero, substantially all of the generated addresses have a value within the range of {1 ≦ k ≦ 2 ^m −1}. Therefore, in Equation 1, [PN _g (ADDRESS_WRITE) -1] has a value within a range of {0 ≦ k ≦ 2 ^m −2}. In this case, since a number of the address 2 ^m -1 generated by the address number of pseudo-random generators than 2 ^m ever need a last address of each area are rewritten as (Overwrite) by accepting a read address (ADDRESS_READ). Corresponding content is expressed as ADDRESS_WRITE = ADDRESS_WRITE + g * ^2m -OFFSET (ADDRESS_WRITE) in Equation 1 described above.

For example, in Table 1, when the interleaver size N is 376, an example of an OCPNI read address is shown in Table 3 below.

36 73 172 230 317 332 33 68 165 226 286 373 16 113 146 224 318 346 55 88 184 223 302 27 123 171 207 294 365 13 149 199 290 342 6 78 138 195 288 50 118 180 193 287 364 40 106 169 192 271 357 35 100 148 239 262 338 17 97 185 215 259 8 80 156 203 257 363 51 119 189 197 256 341 25 91 158 194 303 330 12 77 190 240 279 372 53 70 174 231 267 361 26 114 166 211 261 340 60 104 162 201 258 45 99 160 196 304 348 22 81 159 241 295 58 72 143 216 275 350 44 115 135 251 265 37 89 131 221 260 366 18 76 129 206 305 358 56 117 128 246 280 354 43 90 175 234 315 352 21 124 151 228 285 351 10 109 139 225 270 335 52 86 133 208 310 327 41 122 130 247 298 323 20 108 176 219 292 321 57 101 167 205 289 320 28 82 147 198 272 367 61 120 137 243 311 343 30 107 132 232 283 331 62 85 177 227 269 325 46 74 152 209 262 322 38 116 187 200 306 368 34 105 157 243 296 359 32 84 142 217 291 339 31 121 182 204 272 329 15 92 170 245 264 324 7 125 164 218 307 369 3 94 161 252 281 344 1 126 144 237 268 1 110 183 214 309 349 47 102 155 250 282 334 23 98 141 236 316 374 11 96 134 229 301 362 5 95 178 210 278 356 2 79 168 248 314 353 48 71 163 235 300 336 39 67 145 213 293 375 19 65 136 202 274 347 9 64 179 244 312 333 4 111 153 233 299 326 49 87 140 212 277 370 24 75 181 249 266 360 59 69 154 220 308 355 29 66 188 253 297 337 14 112 173 222 276 328 54 103 150 254 313 371 42 83 186 238 284 345 63 127 191 255 319

As described above, the OCPNI according to the first embodiment of the present invention is obtained by primitive polynomials of pseudorandom generators or an algorithm in which initial state values are described below. In addition, the first embodiment has been described as deleting the invalid address GTH generated by the offset values from the comparator 222. As another example, however, the pseudorandom generator 8N1 corresponding to the last region generates a low address (GTH) by an offset value, so that such an invalid address is not fundamentally generated. In this case, the erase function of the comparator 222 described above is unnecessary.

Hereinafter, an interleaving apparatus according to a second embodiment of the present invention which does not fundamentally generate the invalid address will be described in detail.

The core idea of the OCPNI is to obtain the virtual interleaver size N by adding OSV to the interleaver size L, splitting it into N _G regions, and substituting each group element using a pseudo random generator (PN Generator). Permutation). These pseudorandom generators all generate 2 ^m address configurations. However, since the last pseudorandom generator (g = N _G −1) of the pseudorandom generators generates an invalid address due to OSV, it should be removed. This is because the total number of addresses generated by the OCPNI Address Generator Block becomes L. Therefore, the present invention monitors the address generated by the last pseudorandom generator (g = NG-1) and controls logic to skip selection of the pseudorandom generator when the address is invalid by the added offset value. ).

First, it is assumed as an example that the frame size (L) = 60, the offset value (OSV) = 4, the interleaver size (N) = 64, the generated polynomial order (m) = 4, the number of areas (N _G ) = 4 4 pseudorandom generators, each with 15 cycles. And it is assumed that the sequence generated in the last pseudorandom generator is as given in Table 4 below.

Time k: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PN3 (k): 5 1 13 2 7 15 14 3 6 4 8 12 9 11 10
PN3 (k) -1: 4 0 12 1 6 14 13 2 5 3 7 11 8 10 9

As shown in Table 4, the state value PN3 (k) of the PN generator generated by the last pseudorandom generator (g = N _G −1) is used for interleaving frame data corresponding to the last group stored in the interleaver memory. It is a read address. Therefore, as described above, when OSV = 4 and m = 4, the 12, 13, 14, and 15th addresses of the last group are invalid addresses. In this case, the invalid addresses generated by the last pseudorandom generator are skipped. You can see that we can just move to the first pseudorandom generator. If the pseudorandom generator is sequentially selected from 0, the last pseudorandom generator is used as the low address of the read address by subtracting '1' from the address generated by the last pseudorandom generator. If one of, 14,15 occurs, the 0th pseudorandom generator is selected immediately instead of the last pseudorandom generator. The invalid address according to 15 (PN3 (K) -1) that the last pseudorandom generator cannot generate is ignored because it does not provide a clock signal in hardware or does not use it even if it is generated initially. On the other hand, if the pseudorandom generator is randomly selected, the last pseudorandom generator may not be selected as the last of one frame. At this time, the next pseudorandom generator is skipped without using the last address (2 ^m −1).

In consideration of the foregoing, the interleaving address generation algorithm of the OCPNI according to the second embodiment of the present invention can be expressed by Equation 2 below.

/ * OCPNI-2 Program * /

/ * N: frame length (= L + OSV) GL: area size (= 2 ^m ) N _G : number of areas * /

For (clk = 0; clk <NN _G ; clk ++)

{g = clk% NG;

READ_ADDRESS = PNg ()-1 + g * GL;

active = (READ_ADDRESS <L)? ON: OFF;

if (active == ON) {printf (% d \ n, READ_ADDRESS);}

}

for (g = 1; g <N _G ; g ++)

{READ_ADDRESS = GL * g-1;

printf (% d \ n, READ_ADDRESS);

}

Equation 2 described above is implemented in hardware as shown in FIG. 10.

Referring to FIG. 10, PN generators 11-14 generate pseudo-random sequences for changing the order of data stored in corresponding address generation regions and output the pseudo random sequences to the first multiplexer 14. Here, each pseudorandom generator is initialized to an optimal state value obtained by an algorithm described below. This will be described later in detail in the method for determining an initial state value of a pseudorandom generator. The counter 19 outputs a selection signal for selecting the output of the first multiplexer 14. If it is assumed that the number of address areas is N _G , a selection signal of 0..N _G -1 is output. The selection signal may occur sequentially or randomly. When the random occurrence occurs, the selection signal is randomly generated by any pattern obtained by a predetermined algorithm. The multiplexer 14 selects and outputs the output of the pseudorandom generator based on the selection signal provided from the counter 19. Here, the output data of the multiplexer 14 is subtracted by '1' from the subtractor 23 and input to the second multiplexer 15. That is, since the pseudorandom generators do not generate an address '0' value, the pseudorandom generator subtracts 1 from all generated values to map random addresses from zero. The area counter 16 generates a counter corresponding to the size of the address generation area and outputs the counter to the comparator 17. The comparator 17 outputs a selection signal '1' to the second multiplexer 15 when the count provided by the area counter 16 corresponds to an area size (2 ^m ) −1. The second multiplexer 15 selects and outputs the output of the first multiplexer 14 when the count generated at the area counter 16 by the selection signal is in the area size-2, and provides the comparator 17 when the area size-1 is reached. Selectively output the value of 2 ^m -1 (area size -1). The address buffer 22 stores the output data of the counter 19 in the upper address area and the output data of the second multiplexer 15 in the lower address area. The address stored in the address buffer 22 is used as an address for reading data from the interleaver memory.

An offset value detector 18 inputs the state of the last pseudorandom generator 14 and the count signal of the counter 19, and the pseudorandom generator to be selected next by the count signal is the last pseudorandom generator 14, and the pseudorandom generator A reset signal (Load Zero) is provided to the counter 19 when it is determined that the state value of 14 is an invalid state value (hereinafter referred to as an offset state value) by the added offset value. Then, the counter 19 skips the last pseudorandom generator 14 and outputs a selection signal for selecting the next pseudorandom generator. If it is designed to sequentially select the pseudorandom generator, if it is designed to output a selection signal for selecting the pseudorandom generator for the first time, and randomly select the pseudorandom generator, the next pseudorandom generator is determined according to the determined pattern. Outputs a selectable signal. The offset value detector 18 determines whether the state value currently stored by the AND-OR-Ring connection of the last pseudorandom generator is an offset state value based on the added offset value, and outputs a reset signal Load_Zero. Here, the AND-OR-RIng connection of the last pseudorandom generator is determined by the shift register cell number m and the offset value OSV.

The AND-OR-Ring connection of the pseudorandom generator always has a certain rule when OSV is a constant, so the implementation is very simple. For example, assuming that m = 4 and OSV = 4, the AND-OR-Ring connection is as shown in FIG. 12. Referring to FIG. 12, the lower two register cells are OR-ringed, and the remaining upper two register cells are AND-ringed. This means that when m = 4, the sequence generated by the pseudorandom generator is 1 to 15, and since the offset value is 4, the last pseudorandom generator is allowed to skip 13 OSV-1s corresponding to 13,14,15. -OR-Ring connection is configured. The reset signal (Load-Zero signal) is generated by multiplying a signal obtained by inverting the output of the AND gate, the output of the OR gate, and the output of the counter 19. If the pseudorandom generator is randomly selected, the last pseudorandom generator may not be selected as the end of one frame, and thus the last created value 2 ^m -1 is skipped without using.

The first logical operator 20 inputs the count value output from the symbol clock SYM_CLK and the counter 19, and all the pseudorandom generators 11 when the count value is logical 0 and the symbol clock is a rising edge. Generates a clock to update the status value to -14. The second logical operator 21 inputs the count value output from the symbol clock and the counter 19, and the clock for the next counting to the area counter 16 when the count value is logical 0 and the symbol clock is a falling edge. To provide.

A process of generating a read address according to the configuration of FIG. 10 will be described.

The pseudorandom generators 11-12 generate a pseudorandom sequence by shifting a stored register cell value each time a clock is provided by the first logical operator 20, and the first multiplexer 14 generates a pseudorandom sequence by the selection signal provided by the counter 19. Outputs the state of the pseudorandom generator. The pseudorandom sequence output from the first multiplexer 14 is reduced by 1 in the subtractor 23 and input to the second multiplexer 15. The pseudorandom sequence reduced by '1' is an area count signal of the area counter 16. It is passed as it is until it reaches the value of 2 ^m -1, which is the size of the address generation area, and transferred to the lower area of the address buffer 22. On the other hand, when the area count signal reaches the size 2 ^m −1 value of the address generation area, the 2 ^m −1 value is transferred to the lower area of the address buffer 22. The count value output from the counter 716 is stored in an upper region of the address buffer 22. The value stored in the address buffer 22 is used as an address for reading data stored in the memory. Wherein the offset value detector 18 inputs the state of the last pseudorandom generator 14 and the count value of the counter 19, detects an offset state value from the last pseudorandom generator 14, and the counter value is determined in relation to a predetermined order. When the pseudorandom generator 13 selected immediately before the last pseudorandom generator 14 is indicated, the reset signal Load_Zero is output to the counter 19. Then, the counter 19 omits the selection of the last pseudorandom generator 14 so that the detected offset state is not output by the first multiplexer 14, and sends a selection signal to the first multiplexer 14 to select the pseudorandom generator 11. Output On the other hand, the count value of the counter 19 (the same value as the selection signal) is provided to the first logical operator 20 and the second logical operator 21. Here, the first logical operator 20 receives the counter value and the symbol clock, and provides a clock to the pseudorandom generators when the counter value is '0' and the symbol clock is a rising edge. The pseudorandom generators then update the state by the clock. The second logic operator 16 inputs the counter value and the symbol clock to provide a clock to the area counter 16 when the counter signal is '0' and the symbol clock is a falling edge, and the area counter 16 is provided. Operates by the clock to provide a counter value to the comparator. Here, the area counter 16 counters the selection period of the pseudorandom generators. The comparator 17 compares the counter value provided by the area counter 16 with a preset value 2 ^m −1, and outputs a selection signal to the second multiplexer 15 when the counter value is 2 ^m −1 to output the selection signal to the 2 ^m. -1 provides the lower address area of the address buffer 22. That is, when the number of selection periods of the pseudorandom generators is less than 2 ^m by the selection signal of the comparator 17, the second multiplexer 15 provides a pseudorandom sequence of which '1' is reduced to the lower address area of the address buffer 22. and, the number of pseudo-random generator in the selection period of 2 ^m -1 when provides the 2 ^m -1 in the lower address region.

As described above, the second embodiment configures a simple control logic that can omit selection of each offset state of the last pseudorandom generator 14 so that an invalid address due to the added offset does not occur at first. Therefore, as in the first embodiment, logic (comparing part 222, selector 223 and operator 224) for deleting the invalid address already generated is not necessary.

7 is a timing diagram illustrating in detail the above-described read address generation process. It is assumed here that the frame size (L) = 60, the offset value (OSV) = 4, the interleaver size (N) = 64, the generated polynomial order (m) = 4, the number of regions (NG) = 4.

Referring to FIG. 7, SYM_CLK represents a symbol clock, SEL_MUX represents a selection signal for selecting a pseudorandom generator, PN [0] represents a state value of the first pseudorandom generator, and PN [1] represents a second. The state value of the pseudorandom generator, P [2] represents the state value of the third pseudorandom generator, PN [3] represents the state value of the last pseudorandom generator, Load_Zero is the SEL_MUX is '2' and the PN [ 3] is a signal that resets the SEL_MUX to skip selection of the last pseudorandom generator PN [3] when the value is invalid by the offset. UP-Counter represents the area counter, Address_Read represents the read address, the first clock represents the clock for the PN generators to update the status value, and the second clock represents the region to counter the number of selection periods of the PN generators. Indicates the clock provided to counter 16.

As shown, when the Load_Zero signal is enabled, the SEL_MUX is reset and in response thereto, the first clock signal and the second clock signal are enabled so that the pseudorandom generators are not selected. The state of the pseudorandom generators is updated by one clock, and the UP_Counter is counted by the second clock. That is, the last pseudorandom generator skips and uses the register value of the first pseudorandom generator to generate a read address. As a result, the final read address is 0 + a, 16 + b, 32 + c, 48 + d, 0 + e, 16 + f, 32 + g, (skipping h), 0 + i, 16+ j, 32 + k ... If the final state of the up-counter is 15, which is 2m-1, the derived addresses become 0 + 15, 16 + 15, and 32 + 15 regardless of the states of PN (0) to PN (3).

Hereinafter, a process of generating a read address according to a second embodiment of the present invention will be described in detail with reference to FIG. 13.

First, a virtual address area N is obtained by adding an offset value OSV to the size L of an input frame in step 1301. In step 1303, the virtual address area is divided into a plurality of NG address generation areas. do. Thereafter, in step 1305, a random address is generated using the PN generator for each address generation region. In step 1307, random addresses generated in the respective address generation areas are randomly selected. Here, random addresses generated in the respective areas may be sequentially selected. In this process, the OSV detector 18 checks whether the random sequence generated by the pseudo random generator corresponding to the last region is an invalid value by the added offset value. In this case, if it is determined that the value is invalid, the process proceeds to step 1311. If the random address generated in the last region is not selected, the process proceeds to step 1313. Meanwhile, in step 1313, it is checked whether the current area count corresponds to 2 ^m −1, where m represents the number of states of the PN generator. If the area count does not correspond to 2 ^m −1, a read address is generated by 'READ_ADDRESS = PNg ()-1+ (g * GL)' in step 1315, and the area count corresponds to 2 ^m −1. In step 1317, the read address is generated by 'READ_ADDRESS = GL * g + (2 ^m −1)'.

As described above, the OCPNI according to the second embodiment of the present invention greatly improves the implementation complexity. Accordingly, the parameters according to each rate of the CDMA2000 forward additional channel (F-SCH) also need only a PN generator polynomial, an initial state value, and an OSV. The GTH (Equation 1) required by Equation 1 is required. Group reference value) is not required.

Hereinafter, the variables basically determined in designing the OCPNI according to the second embodiment will be described. The basic parameters are the number of group (NG) and the order of PN generator polynomial (m) according to the given interleaver depth. Since it is difficult to find the optimal N _G and m for each frame size of CDMA2000 at the time of initial design, it is determined by a predetermined algorithm. The parameters thus obtained are shown in Table 1 and Table 2 above. For example, in case of rate set 1 of CDMA2000, N _G = 6 was determined for all frame sizes, and m was determined based on this. This is basically to prevent the random property in each group from decreasing when N _G is too large. That is, when N _G = 384 = 6 × 2 ⁵ and N _G = 6, since m = 5, data is randomly read from 2 ⁵ = 32 addresses per group, which is set to the minimum group size. It is done. In addition, since OCPNI is a two-dimensional (2D) PN interleaver, the distance quality was also satisfactory to some extent.

However, in the case of the first embodiment, when the frame size FL is small, as the Eb / No increases, the BER / FER is gradually improved, and the BER / FER curve of the weaving encoder whose slope is K = 9 ( Simulation results are smaller than Curve. In other words, if Eb / No continues to increase, the performance of the turbo coder is expected to be worse than that of the weaving encoder. This phenomenon is related to the weight spectrum of the turbo coder. Therefore, in the second embodiment, three things are considered for the optimization of the OCPNI.

As described above, OCPNI has variables such as N _G and m. Along with this, a generator polynomial is used to operate the PN generator in each group, the choice of which can be another variable. Finally, the variables related to the initial state values of each PN generator are so many combinations that it is difficult to find the optimal initial state values by full serch.

In conclusion, to improve the minimum weight and overall weight spectrum, 1) determine N _G , 2) select the polynomial, and if the minimum weight is not satisfactory, 3) the initial PN generator belonging to the group corresponding to the minimum weight Adjust the status value. In general, a few iterations in this manner will yield a better turbo interleaver. This is because the combination of parameters is so large that it is not effective for computer search. First, define the following functions and variables, and find the optimal interleaver using the following algorithm.

W: Weight Distribution Vector

D (.): Decision Criteria Function

D (W) = 1 if W is satisfactory

D (W) = 0 if Wis not

1.Initialize PN generator PNi with initial seed vector Seedi ∈ {0,1} for i = 0, ..., NG-1

Choose arvitrary primitive polynomial G (x) of order M

Choose information sequence I's that are expected to generate the minimum weight code

2.For a given Turbo Encoder E, computer W

3.If D (W) == 1, go to 6

4.Find PN generator PNk associated with minimum weight of W

5.Change Seedk such that weight (Seedk, Seedi) == 1 and go to 2

6. stop

In order to reduce the search time in the algorithm as shown in Equation 3, first select the best G (x) in a given state and then use the above algorithm. In general, it is possible to find an interleaver that satisfies a given condition after 3-4 times. Of course, the best G (x) also depends on the initial seed, but it is preferable to select G (x) first because the number of generated polynomials is much smaller than the type of state. Therefore, the selection of G (x) is regarded as the coarse estimation process of the interleaver. The designed OCPNI has better weight properties than the above experiment and intuition, which generally guarantees better BER / FER performance.

Hereinafter, a specific example of optimizing the initial register value will be described.

For example, suppose that you optimize the seed for four PN generators. Since m = 5 and N _G = 4, initialize Seed as follows.

Area 0: 0 1 0 1 0

Zone 1: 1 0 1 0 1

Zone 2: 0 0 1 1 0

Zone 3: 1 1 0 0 1

The weight distribution of the OCPNI turbo interleaver thus generated is calculated, and it is assumed that a weight distribution diagram as shown in Table 5 is generated.

weight 22 32 33 62 62 62 63 address 44 92 8 76 111 124 56 group One 2 0 2 3 3 One

In this case, if the minimum distance currently required is about 60, the initial state value of the PN generator of the group whose weight is 22, 32, 33 should be corrected. That is, the initial state values of the PN generators corresponding to the regions 1, 2, and 0 must be corrected. In general, since the PN generator does not affect the weight corresponding to the other region, it is possible to eliminate the case where the weight is less than 60 by modifying the initial state value.

In the above case, it is assumed that the weight distribution diagram as shown in Table 6 is obtained by adjusting the initial state value of region 1 as follows.

Area 0: 0 1 0 1 0

Zone 1: 1 0 1 1 1

Zone 2: 0 0 1 1 0

Zone 3: 1 1 0 0 1

weight 32 33 62 62 62 63 address 92 8 76 111 124 56 group 2 0 2 3 3 One

In this case, since the minimum distance is 32, the initial state value of the corresponding area 2 is adjusted. Repeating this process yields an OCPNI turbo interleaver with a minimum distance of 62. In conclusion, the weight distribution obtained is shown in Table 7 below.

Area 0: 0 1 0 1 0

Zone 1: 1 0 1 1 1

Zone 2: 0 0 1 0 0

Zone 3: 0 1 0 0 1

weight 62 62 62 63 address 76 111 124 56 group 2 3 3 One

The process of optimizing the initial state values of the PN generators is shown in the accompanying drawings in FIG. 14.

Referring to FIG. 14, first, in step 1401, the PN generator of each region is initialized using an arbitrary state value, a generation polynomial of each PN generator is obtained, and a predetermined input information word (predetermined input word) is determined to determine the minimum weight. Select). Thereafter, the OCPNI interleaver operates in operation 1403, and a codeword hamming weight of the turbo encoder output in operation 1405 is obtained. In operation 1407, the distribution of weights is obtained to determine a minimum weight. In step 1409, the controller determines whether the obtained minimum weight satisfies a set threshold. In this case, if the minimum weight satisfies the threshold, the process proceeds to step 1411 and checks whether the search has been performed for all cases of the predetermined input information word. In this case, if the search is completed in all cases, the process is terminated. Otherwise, the process returns to step 1401 again, selects the other predetermined input information word for determining the minimum weight, and then performs the following process again. On the other hand, if the minimum weight does not satisfy the set threshold in step 1409, find a corresponding area in step 1413, change the initial state value of the PN generator corresponding to the area in step 1415, and then go back to step 1403. Go back and repeat the process below. Here, the predetermined input information word refers to a shift form of an information string composed of 2 ^m −1 bits in the case of an m-bit PN generator.

Parameters of the OCPNI according to the second embodiment obtained as described above are shown in Tables 8 and 9 below.

Rateset1 @ 19.2kbps @ 38.4kbps @ 76.8kbps @ 153.6kbps @ 307.2kbps Interleaver size L 376 760 1528 3064 6136 Offset Value (OSV) 8 8 8 8 8 N = L + OSV 384 768 1536 3072 6144 m 6 7 8 9 10 N _g 12 12 12 12 12

Initial parameter 11101 111000 1100101 01010111 100100110 00101 001010 1111010 01101001 101011010 11001 110000 1110101 01110111 11100110 11100 111010 1100001 01011111 110110110 00111 100111 1011011 00101011 101011110 10001 001101 1010100 00110100 111100000 10101 000101 1000100 00010101 100100010 11000 110010 1110001 01111111 111110110 00100 001000 1011110 01100001 111001010 00001 000010 1001010 00001001 110011010 11010 001011 1011000 00101101 111010110 01100 110101 1111111 01100011 100001110 PN generator p (x) [110111] [1011011] [10011101] [101100011] [1000010001] [AND]-[OR] -ring
codition
For NG-1'th PN
Generator [11]-[111] [111]-[111] [1111]-[111] [111111]-[111] [111111]-[111]

[111]-[111] in the [AND]-[OR] -Ring means that PN [5: 3], which is the PN generator cell at the corresponding position, is AND-Ring and PN {2: 0] is OR-Ring connected. .

Rateset2 @ 28.8kbps @ 57.6kbps @ 115.2kbps @ 230.4kbps @ 460.8kbps Interleaver size L 568 1144 2296 4600 9208 Offset Value (OSV) 8 8 8 8 8 N = L + OSV 576 1152 2304 4608 9216 m 6 7 8 9 10 N _g 18 18 18 18 18 Initial parameter 01100 100110 0101011 11110101 001101101 01001 011010 1110001 00111001 101100100 11111 000101 0001010 01010100 000001001 11111 101110 1010110 01000111 101011000 11111 111010 0101011 11010101 010001101 11100 001110 1101101 00111001 101100100 11100 100000 0001111 11001101 000011101 10000 010001 1010110 01000111 100111000 01110 011100 0101000 10010011 011000001 11111 000101 0111011 11010011 001001101 11100 010011 0001111 00000111 100001110 11001 010001 0001010 10100111 001011001 10010 000111 1111000 00101111 1100001000 11111 011101 1111110 10101001 001101101 01110 011101 1110001 00111001 110000110 11001 010001 0001111 00101110 000011101 11111 010001 1010110 01100101 110001000 01100 001110 0000100 11010011 100111111 PN generator p (x) [111011] [1100111] [11001011] [111100111] [110110110] [AND]-[OR] -ring
codition
For NG-1'th PN
Generator [11]-[111] [111]-[111] [1111]-[111] [11111]-[111] [111111]-[111]

For example, when the interleaver size L is 376 in Table 8, the OCPNI read address is obtained as shown in Table 10 below.

28 36 88 123 134 176 212 247 259 288 345 363 24 52 90 109 147 190 220 235 257 310 332 357 26 60 89 102 137 183 216 229 256 315 336 354 25 56 76 115 132 171 218 226 278 301 350 373 12 58 80 105 148 165 217 245 283 294 343 362 16 57 94 100 156 162 204 234 269 307 331 369 30 33 87 116 152 181 208 241 262 297 325 360 23 48 75 124 154 170 222 232 275 292 322 370 11 62 69 120 153 177 215 242 265 308 341 5 55 66 122 140 168 203 253 260 316 330 366 2 43 85 121 144 178 197 238 276 312 337 367 21 37 74 108 158 189 194 239 284 314 328 359 10 34 81 112 151 174 213 231 280 313 338 355 17 53 72 126 139 175 202 227 282 300 349 353 8 42 82 119 133 167 209 225 281 304 334 352 18 49 93 107 130 163 200 224 268 318 335 374 29 40 78 101 149 161 210 246 272 311 327 14 50 79 98 138 160 221 251 286 299 323 365 15 61 71 117 145 182 206 237 279 293 321 358 7 46 67 106 136 187 207 230 267 290 320 371 3 47 65 113 146 173 199 243 261 309 342 361 1 39 64 104 157 166 195 233 258 298 347 356 0 35 86 114 142 179 193 228 277 305 333 372 22 91 125 143 169 192 244 266 296 326 27 32 77 110 135 164 214 252 273 306 339 13 54 70 111 131 180 219 248 264 317 329 6 59 83 103 129 188 205 250 274 302 324 19 45 73 99 128 184 198 249 285 303 340 364 9 38 68 97 150 186 211 236 270 295 348 368 4 51 84 96 155 185 201 240 271 291 344 20 41 92 118 141 172 195 289 346 375 31 63 95 127 159 191 223 255 287 319 351

Tables 11a and 11b described below show weight distributions of the OCPNI according to the first embodiment and the OCPNI according to the second embodiment.

Rate set 1 L Weight Distribution 376 (1) 14 22 30 30 30 34 34 34 34 34 34 36 38 38 41 45 46 46 48 49 ... (2) 26 30 30 30 30 34 35 38 41 42 42 42 43 44 44 47 50 50 50 50 ... 760 (1) 23 26 26 29 30 30 30 30 34 34 34 34 34 34 34 34 34 34 38 45 ... (2) 50 52 52 58 59 61 63 69 70 71 78 78 78 78 78 78 78 78 78 78 ... 1528 (1) 34 34 34 34 34 34 34 34 34 34 40 46 50 54 54 58 58 58 58 58 ... (2) 57 57 58 58 58 58 58 58 58 58 58 58 58 60 64 74 74 77 78 78 ... 3064 (1) 26 30 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 54 ... (2) 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 69 78 98 98 ... 6136 (1) 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 51 58 58 ... (2) 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 ...

Rate set 2 568 (1) 26 26 30 30 30 30 34 41 43 46 46 46 46 46 46 46 46 46 46 46 ... (2) 77 82 82 82 87 88 90 94 97 100 100 101 102 102 102 ... 1144 (1) 21 30 30 30 30 46 46 46 46 46 46 46 46 46 46 50 50 ... (2) 97 10 102 102 102 102 102 102 102 102 102 102 102 ... 2296 (1) 30 34 45 46 46 46 46 46 46 46 46 46 46 46 46 46 46 ... (2) 107 112 116 119 121 122 127 131 132 135 139 140 ... 4600 (1) 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 ... (2) 154 154 154 154 154 154 154 154 154 154 154 154 174 ... 9208 (1) 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 ... (2) 174 220 226 226 226 226 226 226 226 226 226 226 226 ...

As can be seen from Table 11, it can be seen that the performance of OCPNI according to the second embodiment is more than two times better in weight distribution than the OCPNI according to the first embodiment.

In conclusion, (Offset Controlled Interleaver PN) OCPN may know the relevant michimyeo having a decisive influence on the performance of a number N _G, also the raw transient generator polynomial (Primitive Polynomial). If the N _G is too large, since the size of each group is reduced, random property is gradually reduced, so that an appropriate determination of N _G is required. For example, when N _G becomes N, this shows the performance of Offset Controlled Interleaver (OCI), and the performance of the OCI is generally inferior to that of OCPNI. Finally, the consideration is to find the optimal initial state value for a given N _G and primitive generation polynomial.

The foregoing has been described based on the CDMA2000. For example, if the OCPNI according to the present invention is applied to the turbo interleaver for UMTS, the following parameters can be obtained. The parameters described in Table 12 (an example) and Table 13 (another example) below are the parameters for obtaining the best performance.

Interleaver size L 320 640 1280 2560 3840 5120 OSV 0 0 0 0 0 0 N = L + OSV 320 640 1280 2560 3840 5120 m 5 6 7 7 8 8 NG 10 10 10 20 15 20 seed for
PN generator 01100 010100 1000100 1010001 00100110 00100110 11001 001010 1110111 0011000 01101000 01101000 01100 010100 1111101 1010001 10100111 10100111 10000 001010 0000111 0100010 01001001 10011010 01100 011001 1111101 1001011 11100100 10100100 00110 100101 1000100 1001011 01100000 01000000 01010 000001 1001101 1001011 11000110 11000110 00011 110011 1010001 0101110 00111010 00111010 01100 110100 1000100 0011100 10110010 10010010 00001 110011 1101001 0001110 00101010 10111001

seed for
PN generator 0001110 10111001 01000010 1100010 00010101 01110101 0001100 01101000 00011100 1010011 01000000 01000000 0100010 10001000 11011000 0101111 11010111 0101110 00011010 0101100 10010111 0101111 00101111 0011110 01110100 PN generator P (x) 111011 1011011 11001011 11001011 1110011 111100111

Interleaver size L 320 320 640 640 1280 2560 5120 Offset Value (OSV) 0 0 0 0 0 0 0 N = L + OSV 320 320 640 640 1280 1280 5120 m 6 4 7 5 6 8 9 NG 5 20 5 20 20 10 10

seed for
PN generato 111101 1011 0001010 01011 010110 11101110 110001101 110100 1011 0011110 00101 111001 01101000 111100110 011001 1111 10001101 10100 001100 10000100 101011001 110011 1001 1000011 01111 111111 10010110 011010011 110100 1011 1010110 01111 011100 01001110 101101010 1011 01111 101001 11001101 001101101 1011 01111 111010 01011001 000100010 1011 01010 011010 10101100 101000100 0001 00101 111010 10010101 101110011 1001 00001 000101 00001101 110101100 0110 11110 101011 0111 10011 111000 0100 01101 010010 0111 00111 010000 1011 10100 011111 0010 01010 100100 1011 00101 010100 0010 11110 000100 1010 01101 011111 0001 10001 11000 1011011 11001 11001011 110111 1011011 111100111 1101101101 PN generator
p (x)

The weight distribution generated when using the above parameters is shown in Table 14.

Interleaver size Minimum Weight / NG (-> number of gruop 320 48 / 5,50 / 10,36 / 20 640 50 / 5,78 / 10.78 / 10 1280 90 / 10,74 / 20 2560 90 / 10,102 / 20 3840 130/15 5120 130 / 10,170 / 20

As described above, the UMTS turbo interleaver does not add an offset value (OSV) because the frame size is all divided by 2m. However, since the actual frame size to be used in the course of the current UMTS standard has not been determined, in other words, the above-described examples are frame sizes that are set for verification. You must add

As described above, the present invention proposes a method of minimizing the use of memory required for random interleaving while satisfying random properties, distance properties, and weight properties when interleaving input data. In addition, the proposed offset control interleaver method of the present invention solves the problem that the conventional PN interleaving method cannot express the interleaver size as a power of 2, and is very inefficient in terms of memory utilization when the interleaver size is large. In the interleaver design for IMT-2000, the interleaver size of each logical channel is not represented by a power of 2, and the size of the interleaver is also very large. In the conventional interleaving method, the interleaving rule according to the size of each interleaver should be stored in the control unit (CPU or HOST) of the transceiver. Therefore, a separate storage space other than the interleaver buffer was required in the CPU (host) memory, but this problem was solved. That is, the complexity of hardware implementation is greatly reduced by implementing an interleaver that can be enumerated. In addition, the interleaver / deinterleaver transmission method for transmitting and receiving is very simple and uses a minimum of memory. That is, only the L-bit interleaver memory, which is the frame size, is required. Finally, it satisfies all of the characteristics of the turbocoder interleaver, showing similar or better performance than the random interleaver. This guarantees performance above average performance.

Claims (24)

An apparatus for generating L addresses smaller than ^2m × N _G virtual addresses for reading the data from an interleaver memory having L data stored therein, Respectively it includes N _G of PN generator containing m pieces of memory and in response to the clock pulses of the first clock signal, one of the PN generators of OSV-1 satisfying the OSV = 2 ^m × N _G -L Given offset state values and generate 2 ^m -OSV nonzero states, each of the remaining PN generators generates 2 ^m -1 nonzero states, A selection circuit that periodically selects the PN generators in a predetermined order in response to a selection signal and outputs a state generated from the selected PN generator; After detecting each offset state from the one PN generator, generating the selection signal to omit selection to the one PN generator in the predetermined order so that the detected offset state is not output by the selection circuit, Means for generating upper address bits associated with each selection of said PN generators in response to clock pulses of a second clock signal having a period shorter than a clock pulse period of said first clock signal; To lower when the number of selection periods of the PN generators is smaller than 2 ^m generates the low order address bits obtained by subtracting one from each state output from the selection circuit, and corresponds to 2 ^m -1 2 ^m when the number of the selection period Means for generating address bits, Wherein each of said L addresses consists of address bits of said phase and lower address bits associated therewith and comprises an address buffer for storing said addresses.
The method of claim 1, And the OSV is a minimum value that converts the size of the input data into a binary number and adds at least one consecutive number of '0's in the least significant bit.
The method of claim 1, And the selection circuit outputs a selection signal for sequentially selecting the PN generators.
The method of claim 1, And the selection circuit outputs a selection signal for randomly selecting the PN generators.
The method of claim 1, The method of claim 1, And an initial state value of the PN generators is set to a state value that satisfies a minimum weight obtained by turbo encoding a predetermined input word and a predetermined threshold value.

An apparatus for generating L addresses smaller than ^2m × N _G virtual addresses for reading the data from an interleaver memory having L data stored therein, The interleaver memory for sequentially storing the L input data; Adding an offset value to the input data size of the virtual address size is to have the service to an integer multiple of 2 ^m, each 2 ^m the integral number of address generation areas having the size in the address generation areas of addresses corresponding to the offset value It consists of an address generator that generates the excluded addresses, And read out the input data from the interleaver memory with the addresses generated from the address generation areas.
The method of claim 6, wherein the address generator, NG PN generators each containing m memories, one of which has OSV-1 given offset states and 2 ^m -OSV zeros satisfying OSV = 2 ^m x N _G -L Non-states, each of the remaining PN generators generates 2 ^m −1 nonzero states, A selection circuit for selecting the PN generators in a predetermined order in response to a selection signal and outputting a state generated from the selected PN generator; After detecting each offset state from the one PN generator, generating the selection signal to omit selection to the one PN generator in the predetermined order so that the detected offset state is not output by the selection circuit, Means for generating upper address bits associated with each selection of said PN generators; To lower when the number of selection periods of the PN generators is smaller than 2 ^m generates the low order address bits obtained by subtracting one from each state output from the selection circuit, and corresponds to 2 ^m -1 2 ^m when the number of the selection period Means for generating address bits, Wherein each of said L addresses consists of said best address bits and associated lower address bits and comprises an address buffer for storing said addresses.
The method of claim 6, And the OSV is a minimum value that converts the size of the input data into a binary number and adds at least one consecutive number of '0's in the least significant bit.
The method of claim 6, And the selection circuit outputs a selection signal for sequentially selecting the PN generators.
The method of claim 6, And the selection circuit outputs a selection signal for randomly selecting the PN generators.
The method of claim 6, And an initial state value of the PN generators is set to a state value which satisfies a minimum weight obtained by turbo encoding a predetermined information word and a predetermined threshold value.
A method for generating L addresses smaller than 2 ^m x N _G virtual addresses for reading the data from an interleaver memory having L data stored therein, Generate OSV-1 given offset states and 2 ^m -OSV nonzero states that satisfy OSV = 2 ^m × NG-L from one of the N _G PN generators, and 2 ^m − from each of the remaining PN generators. The process of generating one non-zero state, A selection signal having a selection period for omitting the selection of the one PN generator in a predetermined selection order for the PN generators so that the detected offset state is not selected after detecting each offset state from the one PN generator; Process of generating, Selecting the PN generators according to the selection signal and sequentially generating the non-zero states; Subtracting 1 from each of the sequentially generated non-zero states, When the number of the selection periods is smaller than 2 ^m provides each of the subtracted states as the low order address bits, and providing 2 ^m when the number of the selection cycle the lower address bits corresponding to the state of the 2 ^m -1, and Generating upper address bits related to a selection signal associated with each of the lower address bits; And reading the L pieces of data from the interleaver memory with the addresses consisting of the lower address bits and the upper address bits.
The method of claim 12, The OSV is a minimum value that converts the size of the input data into a binary number so that the number of consecutive '0' in the least significant bit is at least one or more.
The method of claim 12, And the predetermined order of selection is an order of sequentially selecting the PN generators.
The method of claim 12, Wherein the predetermined order of selection is a sequence of randomly selecting the PN generators.
The method of claim 12, And an initial state value of the PN generators is set to a state value which satisfies a minimum weight obtained by turbo encoding a predetermined information word and a predetermined threshold value.

A method of interleaving input data having a size not an integer multiple of 2 ^m (m> 1), Sequentially storing the input data in a memory; The process of adding the offset value to the input data size of the virtual address size providing an integral multiple (N _G) of 2 ^m and, Generating addresses having the integer number of address generation regions each having a size of 2 ^m and excluding addresses corresponding to the offset value in the address generation regions; And reading the input data from the memory with the addresses generated from the address generation regions.

The method of claim 17, wherein the address generation process, From one of the PM generator corresponding to each of the address generation areas, including offset states corresponding to the offset value generating 2 ^m -1 different states is not zero and, 2 ^m -1 different from zero, each of the other PN generators To generate non-states, A non-zero state of the PN generators by a selection signal having a selection period for omitting the selection of the one PN generator of the predetermined selection order for the PN generators after detecting each offset state from the one PN generator The process of selecting them, Subtracting '1' in the selected state to provide lower address bits, and generating upper address bits corresponding to a selection signal associated with each of the lower address bits; And generating the addresses consisting of the lower address bits and the higher address bits.
19. The method of claim 18, wherein the upper address generation process, When the number of the selection periods is smaller than 2 ^m provides each of the subtracted state into the lower address bits, and provides the lower address bits in response to the condition of the number of the selection period 2 ^m -1 ^m 2 area the And generating upper address bits corresponding to the selection signal associated with each of the lower address bits.
The method of claim 17, The OSV is a minimum value that converts the size of the input data into a binary number so that the number of consecutive '0' in the least significant bit is at least one or more.
The method of claim 18, And the predetermined order of selection is an order of selecting PN generators sequentially.
The method of claim 18, Wherein the predetermined order of selection is a sequence of randomly selecting PN generators.
The method of claim 18, And an initial state value of the PN generators is set to a state value which satisfies a minimum weight obtained by turbo encoding a predetermined information word and a predetermined threshold value.
In the turbo encoding device, A first component encoder for encoding input data having a size not an integer multiple of 2 ^m (m> 1), Storing sequentially the input data in the interleaver memory and by adding an offset value to the input data size of the virtual address size is to have the service to an integer multiple of 2 ^m, each 2 ^m the integral number of address generation areas having the size of the address An interleaver for generating addresses except for addresses corresponding to the offset value in generation regions, and reading the input data from the interleaver memory with the generated addresses; And a second component encoder for encoding the read data from the interleaver.