KR100329337B1 - Method for forming polyimide layer on copper layer - Google Patents
Method for forming polyimide layer on copper layer Download PDFInfo
- Publication number
- KR100329337B1 KR100329337B1 KR1019990036438A KR19990036438A KR100329337B1 KR 100329337 B1 KR100329337 B1 KR 100329337B1 KR 1019990036438 A KR1019990036438 A KR 1019990036438A KR 19990036438 A KR19990036438 A KR 19990036438A KR 100329337 B1 KR100329337 B1 KR 100329337B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- polyimide layer
- polyimide
- forming
- copper
- Prior art date
Links
- 229920001721 polyimide Polymers 0.000 title claims abstract description 94
- 239000004642 Polyimide Substances 0.000 title claims abstract description 88
- 239000010949 copper Substances 0.000 title claims abstract description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 98
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 238000010030 laminating Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 239000009719 polyimide resin Substances 0.000 description 6
- 230000002265 prevention Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229920005575 poly(amic acid) Polymers 0.000 description 5
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 4
- 239000005751 Copper oxide Substances 0.000 description 4
- 229910000431 copper oxide Inorganic materials 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000001029 thermal curing Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
Abstract
본 발명은 표면에 구리 배선이 노출된 반도체 장치의 상부에 폴리이미드(polyimide) 층을 형성하는 방법에 관한 것으로서, 구리 배선이 노출된 반도체 장치의 표면에 보호층을 형성하는 제 1 단계; 보호층 상부에 폴리이미드층을 형성하기 위한 재료를 적층하는 제 2 단계; 폴리이미드층 형성 재료를 경화 또는 부분 경화하여 폴리이미드층을 형성하는 제 3 단계; 제 2 단계 및 제 3 단계를 적어도 2회 반복하는 제 4 단계를 포함하는 구리 배선 상에 폴리이미드층을 형성하는 방법을 제공함으로써, 구리 배선내의 구리 원소가 폴리이미드층에 확산되어 산화물을 형성하는 것을 감소시킬 수 있는 효과가 있다.The present invention relates to a method for forming a polyimide layer on top of a semiconductor device in which copper wiring is exposed on a surface, the method comprising: forming a protective layer on a surface of a semiconductor device in which copper wiring is exposed; Laminating a material for forming a polyimide layer on the protective layer; A third step of curing or partially curing the polyimide layer forming material to form a polyimide layer; A method of forming a polyimide layer on a copper wiring comprising a fourth step of repeating the second and third steps at least twice, wherein the copper element in the copper wiring diffuses into the polyimide layer to form an oxide. There is an effect that can reduce.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 더욱 상세하게는 반도체 장치의 구리 배선상에 폴리이미드층을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor element, and more particularly, to a method for forming a polyimide layer on a copper wiring of a semiconductor device.
주지하다시피, 알루미늄(Al) 및 그 합금 박막은, 높은 전기 전도도, 건식 식각에 의한 패턴 형성의 우수성, 실리콘 산화막과의 우수한 접착성 및 저렴한 가격으로 인해서, 반도체 장치의 금속 배선으로 널리 사용되어져 왔다.As is well known, aluminum (Al) and its alloy thin films have been widely used as metal wirings for semiconductor devices because of their high electrical conductivity, excellent pattern formation by dry etching, good adhesion to silicon oxide films, and low cost. .
그러나, 반도체 장치의 집적도가 증가함에 따라서 금속 배선의 선폭이 감소되고 있는데, 이러한 선폭 감소는 알루미늄(Al)의 일렉트로 마이그레이션(Electromigration)이나 스트레스 마이그레이션(stressmigration) 등을 심화시켜서 단선 유발 가능성을 증가시킨다. 즉, 고집적화 되어가는 반도체 장치에서는 알루미늄(Al)을 금속배선으로 사용할 경우 단선될 가능성이 커서, 반도체 장치의 신뢰성을 확보하기 어렵게 된다.However, as the degree of integration of semiconductor devices increases, the line width of metal wirings decreases. This reduction in line width increases the electromigration or stress migration of aluminum (Al), thereby increasing the possibility of disconnection. In other words, in the semiconductor device, which is becoming highly integrated, when aluminum (Al) is used as the metal wiring, it is likely to be disconnected, making it difficult to secure the reliability of the semiconductor device.
더욱이, 반도체 장치가 고집적화되어감에 따라서 배선의 선폭이 감소됨과 아울러 배선간의 간격도 좁아지므로, 비아홀 또는 컨택홀의 크기도 점점 작아져서, 홀의 종횡비(aspect ratio)가 증가되고 있다. 홀의 종횡비가 증가되면, 홀 내에서 금속을 매립할 때 단차 피복성(step coverage)이 저하되므로, 국부적으로 금속 배선이 얇게 형성되고, 이 부분에서 알루미늄(Al) 배선의 단선 발생 확률은 더욱 커지게된다.Furthermore, as semiconductor devices become more integrated, the line width of the wiring is reduced and the spacing between the wirings is narrowed, so that the size of the via hole or the contact hole is smaller, and the aspect ratio of the hole is increased. If the aspect ratio of the hole is increased, the step coverage decreases when the metal is buried in the hole, so that the metal wiring is locally thinned, and the probability of disconnection of the aluminum (Al) wiring is increased. do.
따라서, 종래의 반도체 장치의 금속 배선 재료로 널리 사용되던 알루미늄(Al)을 대체할 금속 재료가 요구되는 바, 이러한 알루미늄(Al)을 대체할 금속재료로서 구리(Copper : Cu)가 고려되고 있다. 즉, 구리(Cu)의 경우 알루미늄(Al)에 비해서 비저항이 낮고 일렉트로 마이그레이션이나 스트레스 마이그레이션 특성이 우수하므로, 그와 같은 구리를 반도체 장치의 금속 배선으로 채용함으로써, 고집적화 되어가는 반도체 장치의 신뢰성을 증진시킬 것으로 기대되고 있다.Therefore, since a metal material is required to replace aluminum (Al), which has been widely used as a metal wiring material of a conventional semiconductor device, copper (Copper: Cu) is considered as a metal material to replace such aluminum (Al). That is, copper (Cu) has a lower specific resistance than aluminum (Al), and has excellent electromigration and stress migration characteristics. Therefore, by adopting such copper as a metal wiring of a semiconductor device, the reliability of a semiconductor device that is highly integrated is improved. It is expected to be.
한편, 반도체 장치에서는 칩(chip) 표면을 웨이퍼 상태에서 피복한 후 알파-소립자(α-particle)로부터의 보호와 응력 완충(stress buffer)을 위해서, 반도체 장치의 상부 전면에 폴리이미드 수지(polyimide isoindro quiazoline doine)를 도포한 다음, 그 도포된 폴리이미드 수지를 열처리에 의해서 경화시켜 도 1에 도시된 바와 같이 폴리이미드층(40)을 형성한다. 이때, 도 1에서 설명을 생략하는 참조번호 10은 반도체 기판의 상부에 집적회로장치가 형성된 집적 회로 구조체이고, 참조번호 20은 스크래치(scrach) 등으로부터 집적 회로 구조체(10)를 보호하기 위한 보호층(passivation layer)이며, 참조번호 30은 집적 회로 구조체를 와이어 본딩(wire bonding)하기 위한 구리 패드(copper pad)이다.Meanwhile, in a semiconductor device, a surface of a chip is coated in a wafer state, and then polyimide isoindro is formed on the entire upper surface of the semiconductor device for protection from alpha-particles and stress buffer. After applying quiazoline doine), the applied polyimide resin is cured by heat treatment to form a polyimide layer 40 as shown in FIG. In this case, reference numeral 10, which is not described in FIG. 1, refers to an integrated circuit structure in which an integrated circuit device is formed on a semiconductor substrate, and reference numeral 20 denotes a protective layer for protecting the integrated circuit structure 10 from scratches and the like. (passivation layer), reference numeral 30 denotes a copper pad for wire bonding an integrated circuit structure.
그러나, 상술한 바와 같이 구리 배선을 사용하는 반도체 장치에서, 알파선 방지막으로 폴리이미드층을 형성하게 될 경우, 도 2에 도시된 바와 같이, 폴리이미드 수지를 도포하는 동안 폴리이미드 수지에 포함된 폴리아믹산(polyamic acid)과 반응해서 구리 배선내의 구리 원소가 녹아나오고, 그와 같이 녹아나온 구리 원소는 폴리이미드내에 확산되어, 폴리이미드 수지를 경화하기 위한 열 경화 공정(thermal curing)동안 구리 산화물(copper oxide precipitates), 즉, Cu2O를 형성한다. 즉, 도 2에 점으로 표시된 바와 같이, 폴리이미드 내에 구리 산화물이 형성되는 문제가 있었다.However, in the semiconductor device using copper wiring as described above, when the polyimide layer is formed with the alpha ray prevention film, as shown in FIG. 2, the polyamic acid contained in the polyimide resin during the application of the polyimide resin Reacts with (polyamic acid) to dissolve the copper element in the copper wiring, and the melted copper element diffuses into the polyimide, thereby causing copper oxide during thermal curing to cure the polyimide resin. precipitates), ie Cu 2 O. That is, there was a problem that copper oxide was formed in the polyimide, as indicated by dots in FIG. 2.
상술한 바와 같이 구리 원소가 폴리이미드층내에 확산되어 산화물을 형성하는 것을 방지하기 위해서는, 폴리이미드와 구리 배선 사이에 구리 원소의 확산을 방지할 수 있는 장벽층을 형성할 수도 있을 것이나, 이와 같은 확산 장벽층을 형성하기 위해서는 확산 장벽층을 형성하기 위한 별도의 장비 및 확산 장벽층을 형성하기 위한 재료의 소요로 인해서 반도체 장치의 원가 상승은 불가피할 것이다.As described above, in order to prevent the copper element from diffusing into the polyimide layer to form an oxide, a barrier layer may be formed between the polyimide and the copper wiring to prevent diffusion of the copper element. In order to form the barrier layer, an increase in the cost of the semiconductor device will be inevitable due to the separate equipment for forming the diffusion barrier layer and the material required for forming the diffusion barrier layer.
본 발명은 상술한 문제점을 해소하기 위해서 안출된 것으로서, 구리 배선을 사용하는 반도체 장치의 제조시, 장비의 증설없이 폴리이미드 층내에서 구리 산화물이 형성되는 것을 감소시킬 수 있도록 구현한 구리 배선상에 폴리이미드층을 형성하는 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In the manufacture of a semiconductor device using copper wiring, the polyimide on the copper wiring can be reduced to reduce the formation of copper oxide in the polyimide layer without additional equipment. Its purpose is to provide a method for forming a mid layer.
상술한 목적을 달성하기 위해서, 본 발명에서는, 표면에 구리 배선이 노출된 반도체 장치의 상부에 폴리이미드(polyimide) 층을 형성하는 방법에 있어서, 구리 배선이 노출된 반도체 장치의 표면에 보호층을 형성하는 제 1 단계; 보호층 상부에 폴리이미드층을 형성하기 위한 재료를 적층하는 제 2 단계; 폴리이미드층 형성 재료를 경화 또는 부분 경화하여 폴리이미드층을 형성하는 제 3 단계; 제 2 단계 및 제 3 단계를 적어도 2회 반복하는 제 4 단계를 포함하는 것을 특징으로 하는 구리 배선 상에 폴리이미드층을 형성하는 방법을 제공한다.In order to achieve the above object, in the present invention, in the method of forming a polyimide layer on top of a semiconductor device in which copper wiring is exposed on the surface, a protective layer is provided on the surface of the semiconductor device where the copper wiring is exposed. Forming a first step; Laminating a material for forming a polyimide layer on the protective layer; A third step of curing or partially curing the polyimide layer forming material to form a polyimide layer; It provides a method for forming a polyimide layer on a copper wiring comprising a fourth step of repeating the second step and the third step at least twice.
도 1은 구리 배선상에 폴리이미드층이 형성된 일반적인 반도체 장치의 일예를 도시한 예시도,1 is an exemplary view showing an example of a general semiconductor device in which a polyimide layer is formed on a copper wiring;
도 2는 도 1에 도시된 구리 배선과 폴리이미드 사이의 계면을 촬상한 사진,FIG. 2 is a photograph of an interface between the copper wiring and the polyimide shown in FIG. 1;
도 3은 본 발명의 바람직한 실시예에 따른 구리 배선상에 폴리이미드층을 형성하는 과정을 순차적으로 도시한 공정 단면도.3 is a cross-sectional view sequentially illustrating a process of forming a polyimide layer on a copper wiring according to a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10, 110 : 집적 회로 구조체 20, 120 : 보호층10, 110: integrated circuit structure 20, 120: protective layer
30, 130 : 구리 배선 40 : 폴리이미드층30, 130: copper wiring 40: polyimide layer
140 : 제 1 폴리이미드 조성층 140' : 제 1 폴리이미드층140: first polyimide composition layer 140 ': first polyimide layer
150 : 제 2 폴리이미드 조성층 150' : 제 2 폴리이미드층150: second polyimide composition layer 150 ': second polyimide layer
이하, 첨부된 도 3을 참조해서, 본 발명의 바람직한 일실시예에 따라서 구리 배선 상에 폴리이미드층을 형성하는 방법을 상세히 설명한다.Hereinafter, with reference to the accompanying Figure 3, a method of forming a polyimide layer on a copper wiring according to a preferred embodiment of the present invention will be described in detail.
이때, 본 발명의 핵심 기술 사상은, 『구리 배선이 노출된 반도체 장치의 상부에 폴리이미드층을 형성할 때, 전체 폴리이미드층의 일부 두께를 미리 형성한 다음, 나머지 두께를 기형성된 폴리이미드층의 상부에 적층하는 다층 형성 방법에 의해서, 기형성된 하부의 폴리이미드층을 반응 장벽층으로 활용함으로써, 장비 및 부가 재료의 추가없이 폴리이미드층내에서 구리 산화물이 형성되는 것을 감소』시키는 데 있는 바, 후술하는 설명은 그와 같은 핵심 기술 사상에 의거해서 이해되어야 할 것이다.At this time, the core technical idea of the present invention is, “When the polyimide layer is formed on the semiconductor device where the copper wiring is exposed, the polyimide layer is formed by forming some thicknesses of the entire polyimide layer in advance and then preforming the remaining thickness. By using the multilayer forming method of laminating on the upper side, by utilizing the preformed lower polyimide layer as the reaction barrier layer, it is possible to reduce the formation of copper oxide in the polyimide layer without the addition of equipment and additional materials. The following description should be understood based on such core technical idea.
먼저, 후술하는 설명에서 참조하게될 도 3은, 본 발명의 바람직한 일실시예에 따라서 구리 배선상에 폴리이미드층을 형성하는 방법에 대해서 순차적으로 도시한 공정 단면도로서, 종래의 도면과 구별하기 위해서 100번대의 참조번호를 부여하였다.First, FIG. 3, which will be referred to in the following description, is a cross-sectional view sequentially showing a method of forming a polyimide layer on a copper wiring according to a preferred embodiment of the present invention. 100 reference numbers have been assigned.
도 3a를 참조하면, 표면에 구리 배선이 형성된 반도체 장치의 상부에 폴리이미드 수지를 형성하고자 하는 폴리이미드층의 전체 두께 중 5∼25% 두께 범위, 예를 들어, 전체 10㎛로 형성하고자 하는 경우 0.5∼2.5㎛의 두께 범위로 적층해서, 제 1 폴리이미드 조성층(140)을 형성한다. 이때, 반도체 장치는, 실리콘 기판상에 집적 회로 소자가 형성된 집적 회로 구조체(110)의 상부에 그 구조체(110)를 외부에 와이어 본딩하기 위한 구리 배선(130), 즉, 구리 패드가 형성되어 있고, 그 구리 배선(130)의 일부를 포함하는 집적 회로 구조체(110)의 전면에는, 그 구조체(110)를 스크래치(scrach) 등으로 방지하기 위한 보호층(120)이 형성되어 있을 것이다.Referring to FIG. 3A, a thickness of 5 to 25% of the total thickness of the polyimide layer to be formed on the surface of the semiconductor device on which the copper wiring is formed is formed, for example, 10 μm in total. The first polyimide composition layer 140 is formed by laminating in a thickness range of 0.5 to 2.5 μm. In this case, the semiconductor device includes a copper wiring 130, that is, a copper pad, for wire bonding the structure 110 to the outside on an integrated circuit structure 110 having an integrated circuit element formed on a silicon substrate. The protective layer 120 may be formed on the entire surface of the integrated circuit structure 110 including a part of the copper wiring 130 to prevent the structure 110 from being scratched.
따라서, 본 실시예에서는, 도 3a에 도시된 바와 같이, 제 1 폴리이미드 조성층(140)이 구리 배선(130) 및 보호층(120)의 상부 전면에 형성될 것이다. 이때, 제 1 폴리이미드 조성층(140)은 후속하는 열공정에 의해서 제 1 폴리이미드층(140')으로 형성하기 위한 것으로서, 그와 같은 제 1 폴리이미드층(140')은 구리 배선(130) 내의 구리 원소가 제 1 폴리이미드층(140')의 상부에 도포되는 폴리이미드층의 용제(solution)와 반응하는 것을 방지하기 위한 반응 방지층으로서 작용하기 위한 것이므로, 그 두께 범위는 반응 방지 역할을 수행할 수만 있다면, 보다 얇게 형성하는 것이 바람직할 것이다.Therefore, in the present embodiment, as shown in FIG. 3A, the first polyimide composition layer 140 will be formed on the upper front surface of the copper wiring 130 and the protective layer 120. At this time, the first polyimide composition layer 140 is for forming the first polyimide layer 140 'by a subsequent thermal process, and the first polyimide layer 140' is a copper wiring 130 Since the copper element in the c) acts as a reaction prevention layer for preventing the copper element from reacting with the solution of the polyimide layer applied on the upper part of the first polyimide layer 140 ', the thickness range serves to prevent the reaction. If only it could be done, it would be desirable to form thinner.
도 3b를 참조하면, 상술한 바와 같이 형성된 제 1 폴리이미드 조성층(140)은, 열 경화 공정(thermal curing), 예를 들어, 베이크(bake) 공정 등에 의해서 경화 또는 부분 경화되어 제 1 폴리이미드층(140')을 형성한다. 그러한 열경화 공정에 의해서 경화되어 이루어진 제 1 폴리이미드층(140')은, 후속하는 공정에 의해서 제 1 폴리이미드층(140')의 상부에 적층될 폴리이미드 수지 내의 폴리아믹산(polyamic acid)에 의해서, 구리 금속 내의 금속 원소가 녹아서 폴리이미드 내로 확산되는 것을 방지하게 될 것이다.Referring to FIG. 3B, the first polyimide composition layer 140 formed as described above may be cured or partially cured by a thermal curing process, for example, a bake process, and the like. Form layer 140 '. The first polyimide layer 140 'cured by such a thermosetting process is applied to polyamic acid in the polyimide resin to be laminated on the first polyimide layer 140' by a subsequent process. This will prevent the metal elements in the copper metal from melting and diffusing into the polyimide.
도 3c를 참조하면, 상술한 제 1 폴리이미드 조성층(140)을 형성하던 공정과 동일한 공정에 의해서, 제 1 폴리이미드층(140')의 상부에 폴리이미드 수지를 적층해서 제 2 폴리이미드 조성층(150)을 형성한다. 이때, 제 2 폴리이미드 조성층(150)의 두께는, 형성하고자 하는 전체 폴리이미드중에서 제 1 폴리이미드층(140')을 제외한 나머지 두께로 형성하는 것이 바람직할 것이다. 본 실시예에서는, 구리 배선(130)의 상부에 폴리이미드층을 2층(dual layer)으로 형성하는 경우를 예로 들었으므로, 제 2 폴리이미드 조성층(150)을 형성하고자 하는 전체 폴리이미드중에서 제 1 폴리이미드층(140')을 제외한 나머지 두께로 적층하지만, 다른 실시예에서는, 그 두께의 일부만을 적층해서 다수층으로 형성할 수 있을 것이다.Referring to FIG. 3C, a second polyimide composition is formed by stacking a polyimide resin on top of the first polyimide layer 140 ′ by the same process as that of forming the first polyimide composition layer 140 described above. Form layer 150. At this time, it is preferable that the thickness of the second polyimide composition layer 150 is formed to have the remaining thickness except for the first polyimide layer 140 'among all the polyimide to be formed. In this embodiment, the case where the polyimide layer is formed as a dual layer on the upper portion of the copper wiring 130 has been exemplified, so that the second polyimide composition layer 150 may be formed of the entire polyimide to be formed. One layer of polyimide layer 140 'is laminated to the remaining thickness, but in other embodiments, only a portion of the thickness may be laminated to form a plurality of layers.
도 3d를 참조하면, 제 1 폴리이미드 조성층(140)을 제 1 폴리이미드층(140')으로 형성하는 공정과 동일한 공정, 즉, 열 경화 공정에 의해서 제 2 폴리이미드층(150')을 형성한다. 이때, 제 1 폴리이미드층(140')이 이미 경화 또는 부분 경화되어 있는 상태이므로, 제 2 폴리이미드 조성층(150)에 포함된 폴리아믹산(polyamic acid)과 구리 배선(130)은 접촉되지 않을 것이고, 그 결과, 구리 배선(130)내에 포함된 구리 원소의 확산은 제 1 폴리이미드층(140')으로만 한정될 것이다. 상술한 바 있지만, 그와 같은 이유로 인해서, 제 1 폴리이미드층(140')을 보다 얇게 형성되는 것이 바람직할 것이다.Referring to FIG. 3D, the second polyimide layer 150 ′ is formed by the same process as the process of forming the first polyimide composition layer 140 as the first polyimide layer 140 ′, that is, a thermal curing process. Form. In this case, since the first polyimide layer 140 ′ is already cured or partially cured, the polyamic acid included in the second polyimide composition layer 150 and the copper wiring 130 may not be contacted. As a result, diffusion of the copper element contained in the copper wiring 130 will be limited to only the first polyimide layer 140 '. Although described above, for that reason, it will be preferable to form the first polyimide layer 140 'thinner.
상술한 예에서는, 2번에 걸쳐서 폴리이미드층을 2층으로 형성하는 경우를 예로 들었지만, 그와 같은 경우에는 제 2 폴리이미드층(150')에 포함된 폴리아믹산(polyamic acid)과 구리배선(130)의 접촉을 최소화하기 위해서, 제 1 폴리이미드층(140')의 두께를 최소화하는데 어느 정도 한계가 있다. 즉, 구리 원소가 확산되는 범위를 어느 두께 이하로 감소시키는데에는 한계가 있다.In the above-described example, the case where two layers of the polyimide layer are formed in two layers is used as an example, but in such a case, the polyamic acid and the copper wiring (included in the second polyimide layer 150 ′) In order to minimize the contact of 130, there is a limit to the extent to minimize the thickness of the first polyimide layer 140 ′. In other words, there is a limit to reducing the diffusion range of the copper element to a certain thickness or less.
그러나, 제 1 폴리이미드층(140')의 상부에 형성되는 폴리이미드층을 보다 다수의 층으로 형성한다면, 제 1, 2, 3, …폴리이미드층과 같이, 구리 배선의 상부에서부터 순차적으로 형성되는 각 폴리이미드층이 그 상부에 형성되는 폴리이미드층에 대해서 반응 방지막으로서 동작하므로 제 1 폴리이미드층, 즉, 구리 원소가 확산되는 범위를 최소화할 수 있으며, 적층하는 공정시간이 감소되어 상층의 용제가 하층으로 침투하여 구리 패드와 접촉해서 반응할 시간을 감소 또는 제거할 수 있을 것이다.However, if the polyimide layer formed on the first polyimide layer 140 'is formed of more layers, the first, second, third,... Like the polyimide layer, since each polyimide layer formed sequentially from the top of the copper wiring acts as a reaction prevention film with respect to the polyimide layer formed thereon, the first polyimide layer, that is, the range in which the copper element is diffused The process time for lamination can be minimized and the upper layer solvent can penetrate into the lower layer to reduce or eliminate the time for reaction in contact with the copper pad.
따라서, 상술한 예에서는, 폴리이미드층을 2개층으로 형성하는 것을 예로 들었지만, 다수번의 공정이 소요되는데 따르는 손실과 구리의 확산을 방지할 수 있는 정도를 참조해서, 폴리이미드를 형성할 층의 개수를 한정하는 것이 바람직할 것이다.Therefore, in the above-described example, the formation of the polyimide layer in two layers has been taken as an example, but the number of layers to form the polyimide is described with reference to the degree of preventing the diffusion and the diffusion of copper required by a plurality of processes. It will be desirable to limit
상술한 본 발명에 따르면, 종래의 폴리이미드층 형성 장비내에서, 구리 원소의 반응 방지층을 형성할 수 있으므로, 즉, 폴리이미드층의 일부를 반응 방지층으로 이용하므로, 장비의 추가 및 반응 방지층의 형성에 이용된 재료의 소요없이 구리 원소가 폴리이미드층내에서 산화물로 형성되는 것을 감소시킬 수 있는 효과가 있다.According to the present invention described above, in the conventional polyimide layer forming equipment, since the reaction prevention layer of copper element can be formed, that is, a part of the polyimide layer is used as the reaction prevention layer, thus the addition of equipment and the formation of the reaction prevention layer There is an effect that can reduce the formation of copper elements into oxides in the polyimide layer without the need for the material used for the.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990036438A KR100329337B1 (en) | 1999-08-31 | 1999-08-31 | Method for forming polyimide layer on copper layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990036438A KR100329337B1 (en) | 1999-08-31 | 1999-08-31 | Method for forming polyimide layer on copper layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010019811A KR20010019811A (en) | 2001-03-15 |
| KR100329337B1 true KR100329337B1 (en) | 2002-03-22 |
Family
ID=19609314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990036438A KR100329337B1 (en) | 1999-08-31 | 1999-08-31 | Method for forming polyimide layer on copper layer |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100329337B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101607802B1 (en) | 2012-04-27 | 2016-03-30 | 도쿄엘렉트론가부시키가이샤 | Film-forming method and film-forming device |
-
1999
- 1999-08-31 KR KR1019990036438A patent/KR100329337B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101607802B1 (en) | 2012-04-27 | 2016-03-30 | 도쿄엘렉트론가부시키가이샤 | Film-forming method and film-forming device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010019811A (en) | 2001-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6756675B1 (en) | Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal | |
| KR100419813B1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2943805B1 (en) | Semiconductor device and manufacturing method thereof | |
| WO2000044043A1 (en) | Semiconductor device and method of manufacturing the same | |
| JPH08293523A (en) | Semiconductor device and its manufacture | |
| JP3177968B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP5474534B2 (en) | Passivation and contact surrounded by polyimide and method of manufacturing the same | |
| US8269347B2 (en) | Semiconductor chip, electrode structure therefor and method for forming same | |
| JP2000188357A (en) | Semiconductor device and manufacture thereof | |
| KR100539040B1 (en) | Semiconductor integrated circuit device | |
| KR19990052264A (en) | Semiconductor device with multi-layer pad and manufacturing method thereof | |
| JP3106493B2 (en) | Semiconductor device | |
| US20090184428A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100329337B1 (en) | Method for forming polyimide layer on copper layer | |
| JP4675147B2 (en) | Semiconductor device | |
| JP3725527B2 (en) | Semiconductor device | |
| JP2005005564A (en) | Pad structure | |
| KR100374300B1 (en) | Copper layer for semiconductor fabrication method | |
| JP2008159796A (en) | Semiconductor device | |
| CN101127336B (en) | Semiconductor device, manufacturing method thereof, circuit substrate and electric device | |
| KR100346596B1 (en) | Method for forming bonding pad in semiconductor device | |
| TWI283443B (en) | Post-passivation process and process of forming a polymer layer on the chip | |
| KR100460071B1 (en) | Chip size package | |
| JP2003347338A (en) | Semiconductor device | |
| KR100410708B1 (en) | Semiconductor device and method of making the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120221 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |