KR100327384B1 - System and method for detecting synchronous signal - Google Patents
System and method for detecting synchronous signal Download PDFInfo
- Publication number
- KR100327384B1 KR100327384B1 KR1020000040636A KR20000040636A KR100327384B1 KR 100327384 B1 KR100327384 B1 KR 100327384B1 KR 1020000040636 A KR1020000040636 A KR 1020000040636A KR 20000040636 A KR20000040636 A KR 20000040636A KR 100327384 B1 KR100327384 B1 KR 100327384B1
- Authority
- KR
- South Korea
- Prior art keywords
- synchronous
- signal
- packet data
- synchronous signal
- information signal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/10—Arrangements for initial synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE: A system and a method for detecting a synchronous signal are provided to generate the same synchronous information signal in the case of an externally applied synchronous signal or synchronous signals having various values and lengths included in packet data to transfer the synchronous information signal to the system of the following stage. CONSTITUTION: Packet data is received from the outside. A synchronous information signal applied in synchronization with the start point of the packet data is generated for the synchronous signal of the packet data. The packet data and the generated synchronous information signal are selectively output according to the synchronous signal of the packet data. The synchronous signal corresponds to one of the first synchronous signal that has a predetermined signal form and is inputted from the outside and the second synchronous signal that has a predetermined length and value and is included in the packet data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000040636A KR100327384B1 (en) | 2000-07-14 | 2000-07-14 | System and method for detecting synchronous signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000040636A KR100327384B1 (en) | 2000-07-14 | 2000-07-14 | System and method for detecting synchronous signal |
Publications (1)
Publication Number | Publication Date |
---|---|
KR100327384B1 true KR100327384B1 (en) | 2002-03-13 |
Family
ID=37478399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000040636A KR100327384B1 (en) | 2000-07-14 | 2000-07-14 | System and method for detecting synchronous signal |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100327384B1 (en) |
-
2000
- 2000-07-14 KR KR1020000040636A patent/KR100327384B1/en not_active IP Right Cessation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2377566A (en) | A phase detector | |
AU2002233528A1 (en) | Synchronous to asynchronous to synchronous interface | |
AU6365500A (en) | Method and apparatus for adjusting control signal timing in a memory device | |
MXPA03002064A (en) | Circuit arrangement and a method for detecting an undesired attack on an integrated circuit. | |
WO2002095942A3 (en) | Dual-edge triggered dynamic logic | |
AU2002235193A1 (en) | System and method for device-to-device pervasive digital output | |
WO2003039061A3 (en) | Clock domain crossing fifo | |
EP0909031A3 (en) | Synchronous delay circuit system | |
TW373179B (en) | Semiconductor memory device | |
EP1172954A3 (en) | Method, module and module program for synchronisation | |
EP0800326A3 (en) | Synchronous and asynchronous recovery of signals in an ATM network | |
TW200513824A (en) | Synchronizer apparatus for synchronizing data from one clock domain to another clock domain | |
TW200518021A (en) | Apparatus and method for processing signals | |
EP1139242A3 (en) | Non-synchronized multiplex data transport across synchronous systems | |
WO2002063766A3 (en) | Method and apparatus for detecting valid signal information | |
KR100327384B1 (en) | System and method for detecting synchronous signal | |
WO2003034236A3 (en) | Data synchronization on a peripheral bus | |
WO2001065479A3 (en) | Data carrier having means for synchronization with a received data stream | |
EP1126730A3 (en) | Method for phase change detection of a signal/tone | |
GB2366169A (en) | A method and an arrangement for preventing metastability | |
TW371344B (en) | Circuit for generating internal column address suitable for burst mode | |
CA2239317A1 (en) | Method and apparatus for synchronizing signals | |
WO2002084462A3 (en) | Voltage multiplier for low voltage microprocessor | |
SE9501176D0 (en) | Device and method of an integrated circuit | |
WO2001046874A3 (en) | Correlation of behavioral hdl signals |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130128 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20140124 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20150213 Year of fee payment: 14 |
|
LAPS | Lapse due to unpaid annual fee |