KR100326807B1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- KR100326807B1 KR100326807B1 KR1019940039063A KR19940039063A KR100326807B1 KR 100326807 B1 KR100326807 B1 KR 100326807B1 KR 1019940039063 A KR1019940039063 A KR 1019940039063A KR 19940039063 A KR19940039063 A KR 19940039063A KR 100326807 B1 KR100326807 B1 KR 100326807B1
- Authority
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- South Korea
- Prior art keywords
- gate electrode
- active region
- width
- source
- drain
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
Description
본 발명은 반도체소자에 관한 것으로서, 특히, 모스 전계효과 트랜지스터(Metal-Oxide-Semiconductor Field Effect Transistor)에서 채널 폭을 일정하게 하고 소오스/드레인 영역을 확장하고 소오스/드레인 영역 콘택을 적어도 두개 이상 형성하여 콘택 저항을 감소시켜 소자 동작의 신뢰성 및 공정수율을 향상시킬 수 있는 반도체소자에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to constant channel width, extending source / drain regions, and forming at least two source / drain region contacts in a metal-oxide-semiconductor field effect transistor. The present invention relates to a semiconductor device capable of improving contact reliability and process yield by reducing contact resistance.
반도체 소자의 고집적화에 따라 상하의 배선이나 캐패시터등을 연결하는 콘택 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)는 증가한다. 따라서, 다층의 도전선을 구비하는 반도체 소자에서 콘택을 형성하기 위해서는 제조 공정에서의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다. 또한 콘택홀 크기의 감소는 반도체 제조장비의 고정밀성을 요구하게 되는데, 현재의 장비로는 어느 정도, 예를들어 0.4㎛ 이하의 미세패턴 형성이 어렵다.As the integration of semiconductor devices increases, the size of the contact itself connecting the upper and lower wirings and the capacitors and the distance between the peripheral wirings are reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in order to form a contact in a semiconductor device having a plurality of conductive wires, accurate and exact alignment in a manufacturing process is required, thereby reducing process margin. In addition, the reduction of the contact hole size requires a high precision of the semiconductor manufacturing equipment, it is difficult to form a fine pattern to some extent, for example 0.4 ㎛ or less.
상기 콘택홀은 간격 유지를 위하여 설계시 게이트 마스크와 콘택 마스크는 일정한 설계규칙에 따라 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기변화(critical dimension variation) 및 마스크간의 정합(registration)등과 같은 요인들을 고려하여야 한다.The gate mask and the contact mask are designed to maintain the gap, and the misalignment tolerance when the mask is aligned according to a predetermined design rule, the lens distortion during the exposure process, the mask fabrication and the photolithography process. Factors such as critical dimension variation of the time and registration between masks should be considered.
따라서 상기와 같은 여러가지 사항들을 고려하면 콘택홀 자체의 크기 및 간격이 넓어져 소자의 고집적화가 어려워진다.Therefore, in consideration of the various matters described above, the size and spacing of the contact hole itself are widened, making it difficult to integrate the device.
제 1 도는 종래 기술에 따른 반도체소자의 레이 아웃도로서, 하나의 콘택이 형성되어 있는 경우의 예이다.1 is a layout view of a semiconductor device according to the prior art, which is an example in which one contact is formed.
먼저, 반도체기판(1)상에 한방향으로 연장된 게이트전극(2)이 형성되어 있으며, 상기 게이트전극(2) 양측의 반도체기판(1)에 소오스/드레인 전극이 되는 활성영역(3)이 채널과 동일한 폭을 갖고 형성되어 있다.First, a gate electrode 2 extending in one direction is formed on the semiconductor substrate 1, and an active region 3 serving as a source / drain electrode is formed on the semiconductor substrate 1 on both sides of the gate electrode 2. It is formed to have the same width as.
또한 상기 활성영역(3)과 상측의 배선을 연결하는 콘택홀(4)이 형성되어 있다.In addition, a contact hole 4 connecting the active region 3 and the upper wiring is formed.
상기와 같은 종래 기술에 따른 모스 전계효과 트랜지스터는 소오스/드레인 전극의 콘택이 하나씩 형성되어있어, 콘택 저항이 증가되어 소자동작의 신뢰성이떨어지는 문제점이 있다.In the MOS field effect transistor according to the related art as described above, since the contacts of the source / drain electrodes are formed one by one, there is a problem in that the contact resistance is increased and the reliability of device operation is deteriorated.
이러한 문제점을 해결하기 위하여 두개의 콘택을 형성하기도 하는데, 여러개의 콘택을 형성하기 위해서는 활성영역이 넓거나, 주변의 다른 소자와의 간격이 어느정도 이상이 되어야하고, 미세한 콘택을 인접하게 형성하므로, 공정여유도가 감소되어 공정수율이 떨어지는 문제점이 있다.In order to solve this problem, two contacts may be formed, but in order to form a plurality of contacts, the active area should be wide or at least a certain distance from other devices in the vicinity, and fine contacts are formed adjacent to each other. There is a problem that the yield is reduced because the margin is reduced.
본발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본발명의 목적은 채널폭 보다 넓게 활성영역을 형성하고, 다수개의 콘택홀을 형성하여 콘택홀 형성시의 공정여유도를 증가시키고, 콘택 저항을 감소시켜 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자를 제공함에 있다.The present invention is to solve the above problems, the object of the present invention is to form an active region wider than the channel width, to form a plurality of contact holes to increase the process margin when forming contact holes, and to improve the contact resistance The present invention provides a semiconductor device capable of reducing the process yield and improving the reliability of device operation.
상기와 같은 목적을 달성하기 위한 본발명에 따른 반도체소자의 특징은, 반도체기판상에 형성되어 있는 게이트전극과, 상기 게이트전극 하부의 채널 폭보다 큰 폭으로 형성하되, 공정여유도가 허용하는 범위내의 폭으로 게이트전극 양측의 반도체기판에 형성되는 소오스/드레인 형성 영역인 활성영역과, 상기 소오스/드레인과 상측의 도전배선을 전기적으로 연결시키는 다수개의 콘택홀이 구비되는 것이다.A semiconductor device according to the present invention for achieving the above object, the gate electrode formed on the semiconductor substrate, and a width larger than the channel width of the lower portion of the gate electrode, but the process margin An active region, which is a source / drain formation region formed on semiconductor substrates on both sides of the gate electrode, and a plurality of contact holes for electrically connecting the source / drain and the upper conductive wirings are provided.
이하, 본발명에 따른 반도체소자에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제 2 도는 본발명에 따른 반도체소자의 레이아웃도이다.2 is a layout diagram of a semiconductor device according to the present invention.
먼저, 반도체기판(1)상에 일정방향으로 연장되어 있는 게이트전극(2)이 형성되어 있으면, 상기 게이트전극(2) 양측의 반도체기판(1)에는 소오스/드레인 전극이되는 활성영역(3)이 형성되어 있다.First, when a gate electrode 2 extending in a predetermined direction is formed on the semiconductor substrate 1, the active region 3 serving as a source / drain electrode is formed in the semiconductor substrate 1 on both sides of the gate electrode 2. Is formed.
여기서 도시되어있지는 않으나, 상기 게이트전극(2)은 게이트산화막과 소자분리 절연막에 걸쳐 형성되어 있으며, 상기 게이트전극(2) 하부의 채널의 폭 보다 상기 활성영역(3)의 폭이 양방향으로 크게 형성되어 있다.Although not shown here, the gate electrode 2 is formed over the gate oxide layer and the isolation layer, and the width of the active region 3 is larger in both directions than the width of the channel under the gate electrode 2. It is.
또한 상기 활성영역(3)의 상측에는 두개의 콘택홀(4)이 형성되어 있다.In addition, two contact holes 4 are formed above the active region 3.
상기와 같은 모스 전계효과 트랜지스터는 채널폭은 고정시킨 후, 채널 양측에서 공정여유도가 허용하는 방향으로 활성영역을 연장하여 다수개의 콘택을 형성할 수 있는 공정 여유를 확보하여 콘택 저항을 감소시킨 것이다.In the MOS field effect transistor as described above, the contact resistance is reduced by securing a process margin for forming a plurality of contacts by extending the active region in a direction allowing process margins on both sides of the channel. .
상기에서는 게이트전극(2)과 동일한 방향으로 활성영역(3)을 연장하였으나, 게이트와 수직한 방향으로 연장할 수도 있으며, 두개의 콘택홀(4)이 아닌 세개 이상을 형성할 수도 있다.The active region 3 extends in the same direction as the gate electrode 2, but may extend in a direction perpendicular to the gate, and may form three or more instead of two contact holes 4.
또한 활성영역(3)을 좌우 대칭으로 연장하지 않고, 어느 한쪽 방향 또는 서로 어긋나게 하여 좌우의 폭이나 길이를 비대칭으로 연장할 수도 있다.In addition, the width or length of the left and right sides may be asymmetrically extended by deviating from the lateral symmetry of the active region 3 without lateral symmetry.
그리고, 상기 게이트전극(2)과 활성영역(3)의 소오스/드레인 영역 사이에 공정여유도가 허용하는 크기의 간격을 주어 공정 마진을 증가시킬 수도 있다.In addition, a process margin may be increased between the gate electrode 2 and the source / drain regions of the active region 3 by a size that allows a process margin.
이상에서 설명한 바와 같이, 본발명에 따른 반도체소자는 게이트전극 양측에 형성되는 활성영역을 채널폭 보다 크게 형성하되, 공정 및 설계여유가 허용하는 방향으로 활성영역을 연장하여 형성하고, 상기 활성영역을 상측 도전배선과 연결하는 콘택홀을 다수개 형성하였으므로, 소오스/드레인 전극의 콘택저항이 감소되고, 콘택홀 형성을 위한 공정 여유도가 증가되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the semiconductor device according to the present invention, the active region formed on both sides of the gate electrode is formed to be larger than the channel width, but the active region is formed by extending the active region in a direction that permits process and design margin, and the active region is formed. Since a plurality of contact holes are formed to connect the upper conductive wirings, the contact resistance of the source / drain electrodes is reduced, and the process margin for forming contact holes is increased, thereby improving process yield and device operation reliability. have.
제 1 도는 종래 기술에 따른 반도체소자의 레이 아웃도.1 is a layout view of a semiconductor device according to the prior art.
제 2 도는 본발명들에 따른 반도체소자들의 레이 아웃도.2 is a layout view of semiconductor devices according to the present inventions.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판 2 : 게이트전극1: semiconductor substrate 2: gate electrode
3 : 활성영역 4 : 콘택홀3: active area 4: contact hole
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039063A KR100326807B1 (en) | 1994-12-29 | 1994-12-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039063A KR100326807B1 (en) | 1994-12-29 | 1994-12-29 | Semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR960026957A KR960026957A (en) | 1996-07-22 |
| KR100326807B1 true KR100326807B1 (en) | 2002-08-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019940039063A KR100326807B1 (en) | 1994-12-29 | 1994-12-29 | Semiconductor device |
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| KR (1) | KR100326807B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100713499B1 (en) * | 2006-04-12 | 2007-05-02 | 삼성전자주식회사 | Portable terminal with sliding module |
-
1994
- 1994-12-29 KR KR1019940039063A patent/KR100326807B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100713499B1 (en) * | 2006-04-12 | 2007-05-02 | 삼성전자주식회사 | Portable terminal with sliding module |
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| KR960026957A (en) | 1996-07-22 |
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