KR100326313B1 - Combine linear amplifier and method - Google Patents

Abstract

PURPOSE: A combine linear amplifier and method is provided to combine outputs of linear amplifiers while preventing signal loss and of generating a stable output by interrupting a linear amplifier in use when an abnormal state arises and uniformly distributing a power of a signal to an interrupted linear amplifier into normal linear amplifiers. CONSTITUTION: A power divider module(100) divides the power of an input RF signal. A linear power amplifier module(200) amplifies the RF signal, and a power combiner module(300) combines the power of signals from the linear power amplifier module. In the power divider module(100), transmission lines(Tl21,Tl31) are connected in series between a node(N1) and a switch(SWl1), and transmission lines(Tl22,Tl32) are connected in series between the node(N1) and a switch(SWl2). Transmission lines(Tl23,Tl33) are connected in series between the node(N1) and a switch(SWl3), and transmission lines(Tl24,Tl34) are connected in series between the node(N1) and a switch(SWl4). The switches(SWl1-SWl4) are connected between corresponding transmission lines(TI31-TI34) and linear amplifiers(LPA1-LAP4) respectively. The characteristic impedance of the transmission line(Tl1) is Z1, the characteristic impedance of respective transmission lines(Tl21-Tl24) is Z2, and the characteristic impedance of respective transmission lines(Tl31-Tl34) is Z3. Transmission lines(Tl1,T21-Tl24,T31-T34) of the power divider module(100) has wavelength/4 and use a microstrip line using Teflon substrate.

Description

Synthetic Linear Amplifier and Method

The present invention relates to a high power amplification apparatus and method, and more particularly, to an apparatus and method capable of synthesizing and outputting the outputs of a plurality of linear amplifiers.

In general, a digital mobile communication system must be provided with a high power amplifier (HPA) in order to amplify and transmit a TX RF signal. In addition, such high power amplifiers operate in the vicinity of saturation regions having non-linear characteristics that can amplify up to the maximum power level. When two or more carrier waves are input to a high output amplifier and commonly amplified, intermodulation distortion (IMD) components are generated due to nonlinear characteristics near the saturation region.

Therefore, the input RF signal can be amplified in a linear region by backing off a few dB, and the noise of the intermodulation component can be reduced, but the output power is lowered. Using a linearizer complementing the nonlinear characteristics in the vicinity of the saturation region of the high output amplifier with a power amplifier can significantly reduce the intermodulation signal that may occur when co-amplifying multiple carriers in the saturation region. . In the exemplary embodiment of the present invention, the amplifier including the linearizer and the power amplifier is referred to as a linear power amplifier (LPA).

At this time, the linear amplifier used in the digital mobile communication system requires a very high output amplifier (HPA). Therefore, in order to amplify the input RF signal to a desired output level, it is common to use a plurality of low power linear amplifier outputs. Such a power synthesizer is disclosed as "Planar Electrically Symmetric n-way Hybrid Power Dividers / Combiners (IEEE Transactions on Microwave Theory and Techniques, vol. MTT-28, No.6, June 1980, pp.555-563). .

The n-way RF power synthesizer includes an n-way Wilkinson type combiner and an n-way radial type combiner. Here, the configuration of the n--way Wilkinson power combiner is composed of a resistance to λ _0/4 transmission line, the n--way power combiner radial λ _0/2 - consists of a λ _0/4 transmission line.

만큼의 출력전력이 감소된다. 여기서 n은 전력증폭기의 수이고 m은 불량 전력증폭기의 수가 된다. 이때 전력 합성을 위해 장착되는 전력증폭기의 수가 작은 RF증폭기인 경우 하나의 전력증폭기라도 불량한 상태가 발생되면 목적하는 증폭 효율을 달성할 수 없으며, 이런 경우 상기와 같은 증폭기는 매우 비효율적인 전력합성기가 되는 문제점이 발생된다. 따라서 상기와 같이 소전력 RF증폭기들을 이용하여 대전력 RF증폭기를 구성하는 경우에는 불량 증폭기의 수가 없어야 한다.When the n-way RF power synthesizers synthesize signals of n power sources having the same amplitude and phase characteristics, the output power is reduced by the number of power amplifiers in which an error occurs. That is, when an abnormality occurs in the m power amplifiers in a state where a large power amplifier is implemented using n power amplifiers, the synthesized output power amplifier signal is generated in proportion to the number of the power amplifiers in a bad state. And as the number of failed amplifiers increases

Output power is reduced. Where n is the number of power amplifiers and m is the number of bad power amplifiers. In this case, in the case of an RF amplifier having a small number of power amplifiers mounted for power synthesis, even if a single power amplifier generates a bad state, the desired amplification efficiency cannot be achieved. In such a case, the amplifier becomes a very inefficient power synthesizer. Problems arise. Therefore, when a large power RF amplifier is configured using the small power RF amplifiers as described above, there should be no number of bad amplifiers.

In addition, in the case of synthesizing the output of n linear amplifiers using the n-way power synthesizer as described above, the power of the received RF signal is divided by n, and then the distributed n RF signals are amplified through n linear amplifiers. Afterwards, the composite output should be performed. At this time, when an abnormality occurs in any linear amplifier constituting the power synthesizer, it affects the overall output, and thus affects the output of the entire transmitter. Therefore, each of the linear amplifiers must be able to detect the current amplifier condition and notify or eliminate the occurrence of an abnormal condition.

It is therefore an object of the present invention to provide an apparatus and method capable of synthesizing a plurality of linear amplifier outputs while preventing signal loss.

Another object of the present invention is to synthesize a linear linear amplifier which can generate a stable output by blocking the linear amplifier in operation when an abnormal state occurs in the synthesized linear amplifier and equally distribute the power of the signal applied to the blocked linear amplifier to the normal linear amplifier And providing a method.

It is still another object of the present invention in a linear linear amplifier comprising a power splitter, a plurality of linear amplifiers, and a power synthesizer to diagnose the magnetic condition of the linear amplifier and to block the output of the linear amplifier when the abnormal condition is detected. It is to provide an apparatus and method that can be.

Synthetic linear amplification apparatus of the present invention for achieving the above object, has a configuration that is connected to each of the output line and the line connected between one input terminal and a plurality of output terminals, respectively, the power of the input RF signal A power distribution module for distributing and outputting the output terminals to the output terminals, lines connected between the plurality of input terminals and one output terminal, and a switch connected to each of the input terminals, and synthesizing the power of the input RF signals It is connected between the output power synthesis module, the output terminal of the power distribution module and the input terminal of the power synthesis module, linearly amplifies the RF signal distributed in the power distribution module and outputs it to the power synthesis module, and detects an internal abnormality. It is characterized in that the linear amplifier configured to block the passage of the RF signal by turning off the switch.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the configuration of a synthesized linear amplifier according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a synthesized linear amplifier for synthesizing the outputs of four linear amplifiers in FIG.

3 is a diagram illustrating a configuration of a linear amplifying apparatus in the configuration of FIGS. 1 and 2.

4 is a diagram illustrating a configuration of a predistorter in FIG. 3.

FIG. 5 is a diagram illustrating a configuration of an automatic level controller in FIG. 4. FIG.

FIG. 6 is a diagram illustrating a configuration of a power detector in FIG. 5. FIG.

7A to 7G are diagrams showing characteristics of a signal spectrum for explaining the operation of the linear amplifying apparatus according to the embodiment of the present invention in FIG.

8 is a diagram illustrating a configuration of a signal detector in FIG. 3.

FIG. 9 is a diagram illustrating a configuration of an abnormality detector in FIG. 3. FIG.

10 is a diagram illustrating a configuration of a control unit in FIG. 3.

11A-11E illustrate a state inspection and control process of a composite linear amplifier according to a second embodiment of the present invention.

12A, B, C, and D are flowcharts for explaining a state inspection and control process of a composite linear amplifier according to a second embodiment of the present invention.

1 is a diagram illustrating a configuration of a synthesized linear amplification apparatus according to an embodiment of the present invention, a power divider module 100 for distributing power of an input RF signal, and the power divided RF signals. A linear power amplifier module 200 for amplifying corresponding RF signals, and a power combiner module 300 for synthesizing and outputting power of signals output from the linear amplifier module, respectively. It is composed.

2 shows an example of the configuration of a four-way synthetic linear amplifier in which four linear amplifiers LPA1-LPA4 are connected in a synthetic linear amplifier according to an embodiment of the present invention.

Looking at the configuration of the power distribution module 100, the transmission line TI1 is connected to the input terminal and the node NI. Transmission lines TI21 and TI31 are connected in series between the node NI and the switch SWI1. Transmission lines TI22 and TI32 are connected in series between the node NI and the switch SWI2. Transmission lines TI23 and TI33 are serially connected between the node NI and the switch SWI3. Transmission lines TI24 and TI34 are connected in series between the node NI and the switch SWI4. The switches SWI1-SWI4 are connected between input terminals of the corresponding linear amplifiers LPA1-LPA4, respectively, and are controlled by the corresponding linear amplifiers LPA1-LPA4. Here, the characteristic impedance of the transmission line TI1 is Z1, the characteristic impedance of the transmission line TI21-TI24 connected in parallel with the node NI has the same value of Z2, and the characteristic impedance of the transmission line TI31-TI34 has the same value of Z3. In addition, the transmission lines TI1, TI21-T24, and T31-T34 of the power distribution module 100 may have a wavelength of λ / 4, and may use a microstrip line using a Teflon substrate.

Looking at the configuration of the power synthesis module 300, the switches SWO1-SWO4 are connected between the output terminals of the corresponding linear amplifiers LPA1-LPA4, respectively, and are controlled by the corresponding linear amplifiers LPA1-LPA4. Transmission lines TO31 and TO21 are connected in series between the switch SWO1 and the node NO. Transmission lines TO32 and TO22 are connected in series between the switch SWO2 and the node NO. Transmission lines TO33 and TO23 are connected in series between the switch SWO3 and node NO. Transmission lines TO34 and T024 are connected in series between switch SWO4 and node NO. Transmission line TO1 is connected to the output terminal and node NO. Here, the characteristic impedance of the transmission line TO1 is Z1, the characteristic impedance of the transmission line TO21-TO24 connected in parallel with the node NO has the same value of Z2, and the characteristic impedance of the transmission line TO31-TO34 has the same value of Z3. In addition, the transmission lines TO1, TO21-TO24, and TO31-TO34 of the power distribution module 100 have a wavelength of λ / 4, and may use a microstrip line using a Teflon substrate. In addition, the switch SW01-SW04 is an RF switch, RF switch "MMS-12-F-PC" manufactured and sold by K & L of the United States can be used.

The linear amplifiers LPA1-LPA4 constituting the linear amplifier module 200 are connected between the switches SWI1-SWI4 and the switches SWO1-SWO4, respectively. Each of the linear amplifiers LPA1-LPA4 checks its own state at regular intervals and controls to switch off the corresponding switches SWI and SWO when an abnormality is detected.

In the configuration of the synthesized linear amplifier shown in FIG. 2, the power distribution module 100 and the power synthesis module 300 have an inverse configuration. In the embodiment of the present invention will be described with respect to the power distribution module 100.

First, when the switches SWI1 to SWI4 are all turned on, the input signal RFi is applied to the node NI via the transmission line TI1. At this time, since there is no open switch in the node NI, the power of the RFi signal applied to the node NI is equally divided into 1/4 and input to the corresponding linear amplifiers LPA1-LPA4. Then, the linear amplifiers LPA1-LPA4 linearly amplify and output the RF signals which are respectively distributed and input. Then, the power synthesis module 300 synthesizes and outputs the RF signals amplified and output to the linear amplifiers LPA1 to LPA4.

Secondly, the operation when the arbitrary switch of the SWI1-SWI4 is turned off will be described. It is assumed here that the switch SWI1 is opened. When the switch SWI1 is off, the transmission lines TI21 and TI31 connected to the switch SWI1 appear to be open when viewed from the node NI. This is because the transmission lines TI21 and TI31 are each? / 4 wavelength transmission lines, and therefore, when the switch SWI1 is turned off, the transmission line becomes a half wavelength line at the center frequency. Therefore, when the switch SWI1 is turned off, since the RF signal is totally reflected and generated in the node NI, the loss of the RF signal does not occur.

At this time, since the switches SWI2-SWI4 are on, the RF signal power of the node NI is equally distributed and the linear amplifiers LPA2-LPA4 are input. At this time, the RF signal flowing into the transmission line should be adjusted to the same amplitude and phase as possible. This means that if the amplitude and the phase of each input signal are the same, the impedance becomes infinite, so the isolation between the input terminals is good, and thus, the power-distributed RF signals are transferred to the output terminal side to prevent power loss. The values of the characteristic impedances Z1, Z2, and Z3 of the transmission lines should be set to appropriate values according to the operating frequency range and the number of input signals, and set such that Z2 ≥ Z3 ≥ Z1.

Therefore, the linear amplifiers LPA1-LPA4 turn on corresponding switches SWI1-SWI4 and SWO1-SWO4 in a steady state. Then, the power distribution module 100 divides the power of the input RFi signal into 1/4 and applies the linear amplifiers LPA1 to LPA4. Therefore, the linear amplifiers LPA1-LPA4 linearly amplify and output RF signals that are each divided by 1/4. Then, the power synthesis module 300 synthesizes the power of the RF signal amplified and output from the linear amplifiers LPA1-LPA4 and outputs the final amplified signal RFo.

Therefore, when an abnormal state occurs in the arbitrary linear amplifier LPA, the synthesized linear amplifier according to the embodiment of the present invention turns off the corresponding RF switch of the power distribution module 100 and the power synthesis module 300 to power the signal applied to the linear amplifier LPA. To block. The power distribution module 100 and the power synthesis module 300 operate to maintain the overall signal power uniformly by equally distributing and synthesizing the power of the signal applied to the linear amplifiers to the linear amplifiers LPAs that operate normally.

The linear amplifier LPA1-LPA4 is mainly used in a digital mobile communication system because it must be a multi-channel amplifier capable of simultaneously amplifying several different RF signals. Therefore, the linear amplifier detects intermodulation noise of a linear compensation circuit to reduce distortion of a signal due to nonlinear operating characteristics of an amplifier, and undesired noise due to intermodulation when amplifying a plurality of signals with a single amplifier. And control functions.

In addition, the linear amplifiers LPA1-LPA4 should detect the abnormality of the amplifier in the state of performing the linear amplification operation, and should turn off the corresponding switch SWI and SWO when the abnormal state is not able to perform the amplification function. .

3 to 11 are views for explaining the operation of the linear amplifier and the self-diagnosis of the abnormal state according to an embodiment of the present invention.

The linear amplifier LPA1-LPA4 implements a linearization method that can remove intermodulation components of the power amplifier output using a pilot tone, and generates a predistortion component in the input signal, thereby interpolating components of the power amplifier output. Predistortion method that suppresses the signal, feedback the intermodulation component, negative feedback method that suppresses the intermodulation component included in the output of the power amplifier, extracts only the intermodulation component, and then combines the output of the power amplifier in the reverse phase There is a feedforward method for suppressing intermodulation components. In the embodiment of the present invention, it is assumed that the linear amplifiers LPA1-LPA4 use a combination of the predistortion method and the feedforward method.

3 is a configuration of each of the linear amplifiers LPA1-LPA4 constituting the linear amplifier module 200 of FIGS. 1 and 2, and shows a configuration of the linear amplifier in which the predistortion method and the feedforward method are mixed as described above.

Referring to FIG. 3, the first variable attenuator 211 controls the attenuation of the RF signal gain incident by the attenuation control signal ATT1. A first variable phase shifter 212 inputs the output of the first variable attenuator 211 and controls the phase of the RF signal incident by the phase control signal PIC1.

A predistortor 213 inputs the RF signal and generates a predistortion signal in advance by predicting harmonics, which are intermodulation components that may be generated by a high power amplifier 214 at a rear stage. The power amplifier 214 power amplifies and outputs the RF signal output from the predistorter 213. The second delay unit 215 inputs an RF signal output from the power amplifier 214 and outputs the delayed signal for a time when the intermodulation signal is applied. Such a configuration becomes a main path of the linear amplifier LPA according to the embodiment of the present invention.

A power divider 216 divides and outputs an RF signal incident on the main path. The distributor 216 may use a directional coupler. The first delay line 217 compensates for the delay time of the RF signal generated during the predistortion and amplification of the main path. The divider 218 is located at the output of the power amplifier 214 and distributes and outputs the output of the power amplifier 214. The distributor 218 may use a directional coupler. The signal canceler 219 inputs an RF signal output from the first delay unit 217 and an amplified RF signal output from the power amplifier 214. The canceller 219 detects the intermodulation signal generated in the power amplification process by canceling the RF signal component output by the first delay unit 217 at the output of the power amplifier 214. The embodiment of the present invention shows an example in which the canceller 219 is implemented as a subtractor.

The second variable attenuator 220 inputs the intermodulation signal output from the canceller 219 and controls the gain of the intermodulation signal input by the attenuation control signal ATT2 output from the controller 237. The second variable displacement controller 221 inputs a mixed modulation signal output from the second variable attenuator 220 and controls a phase of the mixed modulation signal input by the phase control signal PIC2 output from the controller 237. An error amplifier 222 amplifies and outputs the intermodulation signal output from the second variable phase shifter 221. A combiner 223 couples the output of the error amplifier 222 to the output of the second delay 215. The coupler 223 may use a directional coupler.

The above configuration corresponds to a sub-path for generating a signal for suppressing the intermodulation signal generated in the power amplification process of the main path.

The divider 231 is positioned at an input terminal and distributes an input RF signal to output a first signal SF1. The splitter 232 is located at the output terminal of the power amplifier 214 and distributes the power amplified RF signal to output a second signal SF2. The divider 233 is located at the output of the canceller 219, and distributes the intermodulation signal detected by the canceller 219 to output the third signal SF3. The divider 234 is disposed at the output terminal and distributes the final RF signal to output the fourth signal SF4. The distributors 231-234 may use directional couplers. A selector 235 inputs the signals SF1-SF4 output from the distributors 231-234 and selects and outputs a corresponding signal SF controlled by the first selection signal SEL1 (Switching Control Data) output from the controller 237. do.

The signal detector 236 detects the strength of the signal SF output from the selector 235 by the control data PCD (PLL Control Data) output from the controller 237 and converts the RSSI signal into a DC voltage (Received Signal Strength Indicator signal). Outputs The control unit 237 generates a first selection signal SEL1 for selecting the corresponding signal SF in the selector 235 and generates a control data PCD for determining a frequency for detecting the strength of the signal SF selected in the signal detector 236.

The alarm detector 238 detects and outputs an abnormal condition in the linear amplifier LPA. The fault detector 238 includes an over power alarm (OVP) of a linear amplifier, a high power alarm (TEMP), a standing wave ratio alarm (VSWR), a power supply fault (DC fail alarm: DCF), It consists of detectors that detect loop fail alarm (LOP), low power alarm (LWP) of linear amplifier, fan fail alarm (FAN) status and so on. The abnormality detector 238 selects the detection signal ADT by the second selection signal SEL2 of the controller 237 and outputs the detection signal ADT to the controller 237.

The controller 237 controls the overall operation of the linear amplifier LPA, and also diagnoses the state of the linear amplifier LPA and blocks the passage of the signal applied to the linear amplifier LPA when it is determined to be an abnormal state.

First, the controller 237 performs a control function of the linear amplifier LPA. To analyze the value of the RSSI signal output from the signal detector 236, and to adjust the gain and phase of the corresponding signal SF according to the analyzed result. Attenuation control signals ATT1-ATT3 and phase control signals PIC1-PIC3 for controlling corresponding variable attenuators and variable phase shifters are generated. First, when the controller 237 selects the output of the power amplifier 214 output from the splitter 232, the controller 235 controls the signal detector 236 to detect the RSSIs of the harmonic signals of the amplified RF signal, and then determines the magnitude thereof, and then outputs the predistorter 213. Generating an attenuation control signal ATT3 and a phase control signal PIC3 for adjusting the attenuation and phase of the intermodulation signal. Secondly, when the output of the canceller 219 is selected, the controller 237 controls the signal detector 236 to detect RSSIs of the RF signals included in the canceled intermodulation signal to determine the size, and then to the input terminal of the linear amplifier. Attenuation control signal ATT1 and phase control signal PIC1 for adjusting the attenuation and phase of the incident RF signal are generated. Third, when the amplified signal is finally output, the controller 237 controls the signal detector 236 to detect RSSIs of intermodulated signals included in the final output signal to determine a magnitude thereof, and then outputs the intermodulator. Attenuation control signal ATT2 and phase control signal PIC2 for attenuation and phase adjustment of the signal are generated.

Secondly, when the controller 237 diagnoses and controls the state of the linear amplifier LPA, the controller 237 sequentially outputs the second selection signal SEL2 to the fault detector 238 at a predetermined time interval and sequentially inputs detection signals output from the fault detector 238. By determining the state of the input detection signals, it is determined whether or not an abnormality occurs. At this time, when it is determined that the abnormal state is driven, the corresponding alarm timer is driven, and the switch control signal SWC for turning off the RF switch of the power distribution module 100 and the power synthesis module 300 when the abnormal state is maintained so that the value of the alarm timer becomes the set time. Occurs.

First, the operation of linearly amplifying the RF signal to which the linear amplifier LPA is input will be described. The linear amplifier LPA according to the embodiment of the present invention eliminates intermodulation signals that may be generated in the amplification process by using a predistortion method and a feedforward method. In an embodiment of the present invention, the predistorter 213 primarily removes the intermodulation signal output from the power amplifier 214. To this end, the predistorter 213 anticipates and generates harmonics that may be generated when the power amplifier 214 is amplified, and is generated in the power amplifier 214 at the time when the power amplifier 214 is applied to the power transistor of the power amplifier 214. Adjust the phase to output harmonics and out of phase.

In the case of using the predistortion method as described above, the intermodulation signal generated in the linear amplifier cannot be completely removed. Therefore, the linear amplifier according to the embodiment of the present invention applies a feedforward method to suppress the intermodulation signal after the first suppression of the intermodulation signal in the predistorter 213. The linear amplifier using the feedforward method cancels the pure RF signal component from the output of the power amplifier 214 to extract the intermodulation signal, and combines the extracted intermodulation signal with the power amplifier 214 to cancel the intermodulation component. . Therefore, when the feedforward method is used, the intermodulated signal component included in the amplified signal at the final output terminal of the linear amplifier is suppressed to output only pure RF signal components.

Therefore, the linear amplifier LPA according to the embodiment of the present invention first suppresses the intermodulation signal generated in the amplification process of the power amplifier 214 by using the predistortion method, and the horn included in the output of the first suppressed power amplifier 214. Secondary suppression of the modulated signal using the feedforward method. For convenience of explanation, the operation of suppressing the intermodulation signal by the predistortion method will be described first, and the operation of suppressing the intermodulation signal by the feed forward method will be described.

7A to 7G are diagrams illustrating characteristics of signals generated according to the respective sub-operations in FIG. 3, and assume the case of two tones. 7A illustrates an incident RF signal. 7B is a harmonic signal of the RF signal generated by the harmonic generator 314 in the predistorter 213. FIG. FIG. 7C is a signal whose phase is adjusted so that the magnitude of harmonics is adjusted by the variable attenuator 315 in the predistorter 213 and is incident to the power amplifier 214 by the variable phase 316 in an antiphase. FIG. 7D illustrates an amplified RF signal including a mixed modulated signal by amplifying the predistorted signal incident on the power amplifier 214 as shown in FIG. 7C. FIG. 7E is a mixed modulated signal extracted by canceling the signal component of FIG. 7A from the amplified RF signal of FIG. 7D in the canceller 219. FIG. 7F is a signal adjusted by adjusting the magnitude of the intermodulation signal as shown in FIG. 7E and out of phase with the output of the power amplifier 215 on the main path. 7G is a final output signal suppressing the intermodulation signal by combining the amplified RF signal as shown in FIG. 7D and the extracted intermodulation signal as shown in FIG.

FIG. 4 is a diagram illustrating an internal configuration of the predistorter 213 in FIG. 3. Referring to FIG. 4, the divider 312 is located at the input terminal to distribute and output an RF signal. The Automatic Level Control (ALC) 313 maintains a constant level of the incident RF signal so that a constant harmonic can be generated regardless of the level change of the incident RF signal. The harmonics generator 314 inputs the RF signal adjusted in the automatic level controller 313 to generate third, fifth, seventh, and higher harmonics of the RF signal. The variable attenuator 315 inputs a harmonic signal output from the harmonic generator 314 and controls the gain of the harmonic component by the attenuation control signal ATT3 output from the controller 237. The variable phase 316 inputs a harmonic signal output from the harmonic generator 314 and adjusts the phase of the harmonic component by the phase control signal PIC3 output from the controller 237. The delay unit 311 delays the RF signal incident to the main path during the time period during which the predistortion signal is generated. A combiner 317 is located between the output of the delayer 311 and the input of the power amplifier 214 and couples the predistortion signal to the delayed RF signal.

Referring to FIG. 4, the harmonic generator 314 may include a coupler and a shottkey diode. Then, when the RF signal is incident on the Schottky diode, the Schottky diode generates higher harmonics according to the level of the incident RF signal. Therefore, the level of the RF signal incident on the Schottky diode should be set to a level capable of best suppressing the intermodulation signal included in the output of the power amplifier 214. To this end, an automatic level controller 313 is positioned at the front of the harmonic generator 314 so that an RF signal of a constant level is always incident.

The automatic level controller 313 controls and outputs an RF signal having a predetermined level regardless of the level change of the RF signal incident on the linear amplifier. FIG. 5 is a diagram showing the configuration of the automatic level controller 313. A variable attenuator 412 is connected between the distributor 312 and the harmonic generator 314. FIG. A divider 414 is positioned at an input of the harmonic generator 314 to distribute and output a level-adjusted RF signal applied to the harmonic generator 314. The power detector 415 then converts the RF signal into a DC voltage and outputs it to a level controller 416. Then, the level controller 416 controls the variable attenuator 412 according to the DC voltage output to the power detector 415 so that the RF signal of a predetermined level can be incident on the harmonic generator 314.

In this case, the power detector 415 of FIG. 6 should be able to detect a multi-carrier. That is, the power detector 415 should be able to input the RF signal of the multi-carrier and convert it to a DC voltage. FIG. 6 is a diagram illustrating a configuration of the power detector 415. An RF transformer 451 inputs an RF signal to generate two signals having a 180 ° phase difference, and two signals output from the transformer 451 are transmitted on the transmission line. It is converted to DC level through Schottky diodes 454 and 455 through 452 and 453, and then composite rectified through capacitor 456 and resistor 457 and output as DC voltage.

Referring to FIGS. 5 and 6, the operation of controlling the level of the incident RF signal is performed. The 180 ° transformer 451 of the power detector 415 generates two signals that are separated and output in half-cycle units of the incident RF signal. Schottky diodes 454 and 455 convert two signals incident through transmission lines 452 and 453 to DC levels, respectively. Therefore, it is possible to detect a value close to the average power of the multi-carrier, thereby accurately converting the level of the RF signal incident on the harmonic generator 314 to a DC voltage.

Then, the level controller 416 generates a control signal according to the DC voltage level of the RF signal output from the power detector 415 and applies it to the variable attenuator 412. The level controller 313 may be implemented using an operational amplifier or the like. At this time, the control signal output from the level controller 313 generates a control signal to increase the attenuation control when the voltage value is large according to the DC voltage of the detected RF signal, and to reduce the attenuation control when the voltage value is small. Then, the variable attenuator 412 variably attenuates the RF signal to have a constant level irrespective of the level of the incident RF signal and enters the harmonic generator 314.

At this time, if the variation level of the incident RF signal is 10dB, the operating area of the automatic level controller 313 should be designed to control the level to at least 10dB or more. In addition, the RF output level of the automatic level controller 313 must be set such that the harmonic generator 314 can be generated as a predistortion signal capable of maximally suppressing the intermodulation signal generated by the power amplifier 214. Therefore, the harmonic generator 314 inputting the output of the automatic level controller 313 always enters an RF signal of a constant level, thereby stably generating harmonics. Since the harmonics output from the harmonic generator 314 are combined with the RF signal and incident on the power amplifier 214, the power amplifier 214 can suppress the generation of the intermodulation signal in the process of amplifying the RF signal.

In addition, the harmonics generated as described above should be adjusted to the magnitude and antiphase of harmonics that may be generated in the amplification operation when incident on the power amplifier 214. The variable attenuator 315 and the variable phase 316 shown in FIG. 4 adjust the magnitude of harmonics generated by the magnitude of the intermodulation signal that the power amplifier 214 can generate in the amplification operation, and enter the adjusted harmonics in reverse phase. Adjust the phase so that it can be.

The control unit 237 controls the selector 235 to select an output of the power amplifier 214 output from the divider 232, and controls the detector 236 to determine the signal strength RSSI of the intermodulation signal at the output of the power amplifier 214 such as 7d. To be detected. Attenuation control signal ATT3 and phase control for controlling the power amplifier 214 to smoothly suppress the intermodulation signal by comparing and analyzing the RSSI value of the intermodulation signal output from the detector 236 and the RSSI value in the previous state. Generate signal PIC3.

Then, the variable attenuator 315 adjusts the magnitude of the predistortion signal generated by the harmonic generator 315 by the attenuation control signal ATT3, and the variable phase 315 is a power amplifier 214 by the phase control signal PIC3. Adjust the phase so that it can be incident in antiphase. As described above, the harmonic signal generated by the harmonic generator 314 is adjusted in magnitude and phase, and the combiner 317 couples the intermodulation signal to an input terminal of the power amplifier 314. In this case, the delayer 311 delaying the incident RF signal as shown in FIG. 7A delays the RF signal until the predistortion signal is coupled to the input terminal of the power amplifier 214. Then, it can be seen that the predistortion signal is combined with the RF signal at the input of the power amplifier 214. In this case, as shown in FIG. 7C, the position where the intermodulation signal coupled to the RF signal is adjusted out of phase is preferably the input terminal of the power transistor of the power amplifier 214.

As described above, the predistorter 213 generates a predistortion signal in advance by predicting the intermodulation signal to be generated by the power amplifier 214, and attenuation and phase of harmonics so that the intermodulation signal can be suppressed to the maximum in the power amplifier 214. Control to enter the power amplifier 214. At this time, the predistorter 213 mainly removes the third harmonic generated at the highest level among the harmonics that may be generated by the power amplifier 214. The effect of removing the premodulation method of the intermodulation signal can be greatly reduced by applying the feedforward method. This has the advantage that the feedforward scheme can be improved by a few dB with predistortion because the adjustment is very precise and difficult.

Secondly, after the first suppression of the intermodulation signal that may be generated by the power amplifier 214 by the predistortion method as described above, the second operation to suppress the intermodulation signal that was not suppressed by the feedforward method will be described. . The process of removing the intermodulation signal of the power amplifier 214 in the feedforward method can be largely divided into two steps. One is to extract the pure intermodulation signal component by canceling the RF signal component incident to the output of the power amplifier 214, and the other is intermodulation included in the signal finally output from the power amplifier 214 After correcting the magnitude and phase to completely remove the signal, cancel the intermodulation signal components at the output of the power amplifier 214.

First, the first step operation of the feedforward method will be described. The splitter 216 on the auxiliary path distributes the incident RF signal as shown in FIG. 7A, and the first delayer 217 delays the RF signal distributed by the splitter 216 for the predistortion and RF amplification time, and then cancels the offset signal. To 219. Then, the RF signal components of FIG. 7A output from the first delay unit 217 and the amplified signals of FIG. 7D distributed by the divider 218 cancel each other to extract the pure intermodulation signal components of FIG. 7E. Output

As described above, the canceller 219 is a core configuration of the feedforward method, and its function is to detect only the intermodulated signal component at the output of the power amplifier 214. The canceller 219 may be configured in the form of a subtracter or an adder. When the canceller 219 is configured as a subtractor, the two RF signals to be input should be adjusted to have a phase so that they are in phase. When the adder is configured as an adder, the two RF signals to be input should be adjusted so as to have an inverse phase. The embodiment of the present invention shows an example in which the canceller 219 is configured as a subtractor. In this case, the subtractor has a coupler therein, and one input signal of the two input signals is incident to the combiner in phase and the other signal is converted into an antiphase to enter the combiner. When the RF signal as shown in FIG. 7A and the amplified RF signal as shown in FIG. 7D are incident on the subtractor type canceller 219, two RF signal components of the in-phase are converted into an antiphase inside the canceller 219, and then a combiner (here RF signals can be canceled out, leaving only intermodulation components.

At this time, the level and phase of two RF signals incident on the canceller 219 must be exactly matched. To this end, the group delay of the amplified RF signal output from the power amplifier 214 of the main path and the RF signal input through the auxiliary path must be exactly matched in the band, and the characteristics of the flatness of the delay are improved. Should be good. That is, the phase distortion of the RF signal to be canceled should be suppressed as much as possible.

As described above, if the level and the phase of the output of the power amplifier 214 and the RF signal component output from the first delay unit 217 do not exactly match, the RF signal component is not canceled out correctly in the canceller 219. To solve this problem, the first variable attenuator 211 of FIG. 3 adjusts the level of the RF signal incident by the attenuation control signal ATT1 output from the controller 237, and the second variable displacement unit 212 outputs the controller 237. The phase of the RF signal incident by the phase control signal PIC1 is adjusted. Therefore, the first variable attenuator 211 and the first variable displacement unit 212 perform a function of adjusting the RF signal of the main path and the RF signal of the auxiliary path to the same level and phase. The canceller 219 cancels the two RF signal components that are input at the same level and in phase.

In order to control the levels and phases of the two RF signals as described above, the controller 237 outputs a first selection signal SEL1 for selecting the third signal SF3 to the selector 235, and the detector 236 The control data PCD for detecting the RSSI of the RF signal component is output. The selector 235 selects and inputs a third signal SF3 which is an output of the canceller 219 distributed by the divider 223, and the detector 236 generates an RSSI obtained by converting an RF signal component of the third signal SF3 into a DC voltage. . Then, the controller 237 compares the RSSI of the RF signal component with the previous RF signal RSSI, and then generates an attenuation control signal ATT1 and a phase control signal PIC1 for canceling the RF signal component in the canceller 233.

Then, the first variable attenuator 211 attenuates the RF signal incident by the decay rate determined by the attenuation control signal ATT1, and the first phase variable 212 adjusts the phase of the RF signal incident by the phase control signal PIC1. . At this time, the attenuation control signal ATT1 and the phase control signal PIC1 are generated by comparing and analyzing the RSSI of the RF signal outputting the canceller 219 and the RSSI of the previous RF signal, and thus, the first variable attenuator 211 and the first variable shifter 212. 7 controls the RF signal as shown in FIG. 7D and the two RF signals as shown in FIG. 7A to have the same level and the same phase.

The reason for canceling the RF signal component in the canceller 219 is to suppress the RF signal greatly and extract only the intermodulated signal component, so as not to affect the error amplifier 222 at the rear stage. That is, if the output of the canceller 219 fluctuates and the RF signal cannot be effectively removed, an RF signal of a relatively large level is incident on the error amplifier 222, thereby causing the error amplifier 222 to be damaged.

Secondly, the operation of the second step in the feedforward method will be described. Here, as described above, the intermodulation signal output from the canceller 219 is adjusted through the second variable attenuator 220, the second variable phase shifter 221, and the error amplifier 222, and is incident on the main path to output the power amplifier 214. The intermodulation signal component included in is removed. In this case, the intermodulation signal coupled by the combiner 223 should be out of phase with the amplified output signal.

Here, in order to correct the intermodulation signal detected by the canceller 219 to be equal to the level of the intermodulation signal included in the signal output on the main path and to be out of phase, the control unit 237 outputs the final output distributed by the distributor 234. A first selection signal SEL1 for selecting the fourth signal SF4, which is a signal, is generated, and a control data PCD for detecting RSSI of harmonics, which are intermodulation signals, is output from the fourth signal SF4. The selector 235 selects and outputs the fourth signal SF4 output from the divider 234 by the first selection signal SEL1, and the detector 236 detects the RSSI of the harmonics of the fourth signal SF4 by the control data PCD. The control unit 237 is applied. The controller 237 compares the RSSI of the intermodulated signal included in the final output signal with the RSSI of the pre-modulated signal, and then suppresses the mixed modulated signal included in the final output signal according to the analysis result. And a phase control signal PIC2.

Accordingly, the second variable attenuator 220 inputting the output of the canceller 219 adjusts the level of the intermodulation signal incident by the attenuation control signal ATT2, and the second phase adder inputs the signal output from the second variable attenuator 220. The toilet 221 adjusts the phase of the intermodulation signal incident by the phase control signal PIC2. In this case, the second phase variable transformer 221 controls the phase of the mixed modulated signal to be out of phase in the combiner 223 by the phase control signal PIC2. Then, the error amplifier 222 connected between the second variable phase shifter 221 and the combiner 223 amplifies and outputs the mixed modulated signal whose level and phase are adjusted as described above.

As described above, the linear amplification apparatus uses a predistortion method and a feedforward method to suppress intermodulation signals included in an amplified signal. The procedure for suppressing the intermodulation signal first suppresses the intermodulation signal that may be generated in the power amplifier 214 by predistortion, and then detects the intermodulation signal included in the output of the power amplifier 214 by the feedforward method. The intermodulation signal is then combined with the final output signal to remove the intermodulation signal. It is difficult to design and manufacture the power amplifier 214 and the error amplifier 222, and it is difficult to accurately tune the power amplifier 214 and the error amplifier 222 to remove the intermodulation signal using only the feedforward method. After suppression, the feedforward method removes the remaining intermodulation signals, which facilitates the design and manufacture of the linear amplifier.

Next, the process of suppressing the intermodulation signal using the predistortion method and the feedforward method as described above with reference to the control unit 237 will be described in detail.

8 is a diagram showing an internal configuration of the detector 236 according to the embodiment of the present invention. The attenuator 711 attenuates and outputs the signal SF output from the selector 235. Filter 712 is a wide bandpass filter that filters signals in a transmission band. The phase lock loop (PLL) 713 and the oscillator 714 generate a corresponding local frequency LF1 by the control data PCD output from the controller 237. The local frequency LF1 determines a frequency for detecting the RSSI of the selected signal SF. A mixer 715 generates an intermediate frequency (IF) by mixing the signal output from the filter 712 and the local frequency LF1. The filter 716 is an intermediate frequency filter, and filters the difference signal | SF-LF1 | of two frequencies at the output of the mixer 715 and outputs it to IF1. The intermediate frequency amplifier 717 amplifies and outputs the intermediate frequency IF1. Oscillator 719 generates a fixed local frequency LF2. A mixer 718 generates an intermediate frequency IF2 by mixing the IF1 signal output from the intermediate frequency amplifier 717 and the local frequency LF2. The filter 720 filters the difference signal | IF1-LF2 | of two frequencies at the output of the mixer 718 and outputs it to IF2. A log amplifier 721 converts the intermediate frequency IF2 output from the filter 720 into a DC voltage and outputs the RSSI signal.

Referring to the operation of FIG. 8, the selector 235 selects and outputs a corresponding signal SF among the first signals SF1-4th signal SF4 by the first selection signal SEL1 of the controller 237. Filter 712 of detector 236 then filters and applies the signal SF to mixer 715. The PLL713 and the oscillator 714 generate a local frequency LF1 for selecting harmonics or RF signals of the signal selected by the control data PCD of the controller 237. The mixer 715 mixes and outputs the two signals SF and LF1, and the filter 716 filters the frequency corresponding to the difference between the two signals and outputs the result to IF1. The above configuration determines the frequency for detecting the RSSI in the selected signal SF and performs the frequency down conversion function of the first step.

Then, the mixer 715 mixes the local frequency LF2 output from the oscillator 719 and the IF1, and the filter 720 filters the frequencies corresponding to the difference between the two signals IF1 and LF2 in the mixed signal and outputs the IF2. The above configuration performs the frequency down conversion function of the second step. The log amplifier 721 receives the IF2 and converts the DC voltage into a DC voltage. The signal becomes RSSI.

9 is a diagram showing an internal configuration of an abnormality detector 238 for detecting an abnormal state of the linear amplifier LPA according to an embodiment of the present invention. Referring to FIG. 9, the over power detector 811 inputs the final output of the linear amplifier LPA distributed in the divider 234. The overvoltage detector 811 compares the power of the final output RF signal with a set reference value and sets the overvoltage detection signal OVP when the set value is exceeded. The temperature detector 812 has a temperature sensor, which is located around the error amplifier 222. The high temperature detector 812 senses an internal temperature of the linear amplifier LPA, and sets the high temperature detection signal TEMP when the detected temperature exceeds a set temperature. The standing wave ratio detector 813 is connected to the divider 234 and compares the difference between the output voltage of the linear amplifier LPA and the reflected voltage, and then, when the standing wave ratio exceeds the set ratio, the standing wave ratio detection signal VSWR is measured. Set it. The supply power detector 814 examines the power supply generated from the power supply unit (PSU) and sets the power detection signal DCF when a failure occurs. The loop fail detector 815 is connected to the distributor 233 and sets the loop error signal LOP when an RF signal of more than a set value is detected by checking the output of the canceller 219. The low power detector 816 inputs the outputs of the dividers 231 and 234 and sets the low power detection signal LWP when the power difference between the power of the input RF signal and the output RF signal is less than or equal to a set value. The fan fail detecter 817 examines the driving state of the fan located at the rear of the linear amplifier LPA, and generates a fan error signal FAN in the abnormal state. The error selector 818 inputs the outputs of the detectors 811-817 as described above, and selectively outputs a detection signal corresponding to the second selection signal SEL2 output from the controller 237.

10 is a diagram illustrating an internal configuration of the control unit 237 according to the embodiment of the present invention. The analog to digital converter (ADC) 914 converts the RSSI output from the signal detector 236 into digital data and outputs the digital data. ROM912 stores a program for controlling attenuation and phase in accordance with an embodiment of the present invention. The CPU911 generates a first selection signal SEL1 for selecting a signal SF and a control data PCD for selecting a frequency for selecting a desired RSSI from the selected signal SF according to the program of the ROM 912. The RSSI value output to the ADC914 is generated. Comparative analysis is performed to generate the attenuation control signal ATT and the phase control signal PIC. In addition, the CPU911 outputs the second selection signal SEL2 to the abnormality detector 238 at a predetermined time period, sequentially inputs detection signals output from the abnormality detector 238, and then checks the status of the detection signals to determine a set time. If exceeded, a switch control signal SWC is generated to turn off the RF switch of the power distribution module 100 and the power synthesis module 300. RAM913 temporarily stores various data generated while the program is being executed. The DAC915 converts the attenuation control and phase control data output from the control unit 911 into analog and outputs the attenuation control signal ATT and the phase control signal PIC. The communication unit 916 performs a function of communicating data between the linear amplifier and an external device under the control of the CPU816. The mounting detector 917 outputs a mounting detection signal to the CPU911 by inputting signals output from the power distribution module 100 and the power synthesis module 300 when the corresponding linear amplifier LPA is mounted on the power distribution module 100 and the power synthesis module 300. . The mounting sensor 917 may be a connector. In the embodiment of the present invention, when the linear amplifier LPA is mounted, the mounting sensor 917 is connected to the ground terminal of the power distribution module 100 and the power synthesis module 300. Assume Therefore, the mounting detection signal is a ground signal. In addition, the mounting detector 917 generates an open signal when the linear amplifier LPA is not mounted on the power distribution module 100 and the power synthesis module 300.

FIG. 11 is a flowchart illustrating an operation of controlling RF switches of the power distribution module 100 and the power synthesis module 300 when an abnormal state is detected in the synthesized linear amplifier according to the first embodiment of the present invention. In the first embodiment of the present invention, by monitoring the output of the detectors 811-817 at a first set time period, it is determined whether there is an error, and a corresponding alarm flag is set when an error occurs. When the alarm flag is set, it is checked whether the corresponding alarm is maintained for the second set time, and when the same alarm state is maintained for the second set time, the RF switch to be connected to the linear amplifier LPA is cut off to stop the operation of the linear amplifier LPA. After the third set time has elapsed while the linear amplifier LPA is stopped, the RF switch is connected again to restart the linear amplifier LPA, and the above operation is repeated. Is maintained, the linear amplifier LPA is completely stopped.

Referring to FIG. 11, the CPU 111 first checks the output of the mounting sensor 917 in step 1001 to determine whether the corresponding linear amplifier LPA is mounted on the power distribution module 100 and the power synthesis module 300. In this case, when the mounting sensor 917 generates an unmounted signal, the CPU911 detects this in step 1001, turns off the corresponding switch SWI and SWO in step 1003, and resets the mounting flag in step 1005. However, if it is mounted in step 1001, the CPU911 checks whether the linear amplifier LPA is first installed in step 1007. At this time, when the linear amplifier LPA is first installed, the CPU911 turns on the RF switch SWI connected to the power distribution module 100 and the RF switch SWO connected to the power synthesis module 300 in step 1009, and the mounting flag in step 1011. Set it. The CPU911 proceeds to step 1101 to check for alarm occurrence. In addition, when the mounting flag is set, the CPU911 detects it in step 1007 and proceeds to step 1101. Therefore, when the linear amplifier is first installed, the CPU911 turns on the RF switches SWI and SWO and performs a function of a normal linear amplifier.

After that, the process of checking the operation status of the linear amplifier LPA will be described. When the CPU111 reaches the first set time from the internal timer, the CPU 111 detects this in step 1101 and checks whether the switch-off flag is set in step 1103. At this time, if the switch-off flag is not set, the corresponding linear amplifier LPA is performing a normal operation, and thus, an output of the detectors 811-817 is selected to monitor an abnormality.

First, the CPU911 outputs the second selection signal SEL2 for selecting the output OVP of the overpower detector 811 in step 1113, and the abnormal selector 818 selects the output OVP of the overpower detector 811 by the second selection signal SEL2. Output to CPU911. At this time, the overpower detector 811 inputs the final output signal of the linear amplifier LPA output from the divider 234, and compares the power of the final output RF signal with a set power value and when the power exceeds the set power, the OVP signal. Set it.

Thereafter, the CPU911 analyzes the state of the OVP signal. If the OVP signal is set, the CPU911 detects that the output RF signal is an overvoltage state in step 1115 and checks whether the OVP flag is already set in step 1117. If the OVP flag is not set, the CPU911 detects that the output of the RF signal is in an overpower state for the first time in step 1117, sets the OVP flag in step 1119, and then overpowers in step 1121. The OVP counter is driven to accumulate the time detected as a state. However, if the OVP flag is set in step 1117, the CPU911 detects that the power supply has already been in an overpower state in a previous state. In step 1123, the CPUOV increases the value of the OVP counter and accumulates the time value maintained in the overpower state. Let's do it.

However, if the OVP signal is not set in step 1115, the CPU911 detects that the output of the linear amplifier LPA is not an overpower state, clears the OVP flag in step 1125, and then the OVP counter in step 1127. Clear the value of.

Therefore, referring to steps 1113-1127 of FIG. 11A, the output power of the RF signal finally output from the linear amplifier LPA is inspected, and when the set power value is greater than or equal to the set power value, the output time in the overpower state is accumulated and stored. do. However, when the RF signal is maintained at a normal range of output power, the OVP flag and the OVP counter are cleared.

In operation 1131, the CPU911 outputs a second selection signal SEL2 for selecting the output TEMP of the high temperature detector 812. The abnormality selector 818 selects the output TEMP of the high temperature detector 812 by the second selection signal SEL2. Output to CPU911. In this case, the high temperature detector 812 attaches a temperature sensor to a position close to the error amplifier 222, detects the internal temperature of the linear amplifier LPA detected by the temperature sensor, and sets the TEMP signal when the temperature is higher than a set temperature.

The CPU911 analyzes the state of the TEMP signal. If the TEMP signal is set, the CPU911 detects that the internal temperature of the linear amplifier LPA is high in step 1133 and checks whether the TEMP flag is already set in step 1135. At this time, if the TEMP flag is not set, the CPU911 detects that the internal temperature of the linear amplifier LPA has become a high temperature state for the first time in step 1135, sets the TEMP flag in step 1137, and then, in step 1139, The TEMP counter is driven to accumulate the time when the internal temperature is detected as a high temperature state. However, if the TEMP flag is set in step 1135, the CPU911 detects that the internal temperature of the linear amplifier is a high temperature even in a previous state, and increases the value of the TEMP counter in step 1141 so that the linear amplifier is hot. Accumulate a time value that remains in an abnormal state.

However, if the TEMP signal is not set in step 1133, the CPU911 detects that the internal temperature of the linear amplifier LPA is in a normal state, clears the TEMP flag in step 1143, and then the value of the TEMP counter in step 1145. Clear

Therefore, referring to the operation of steps 1131 to 1145 of FIG. 11A, after detecting the internal temperature of the linear amplifier LPA, it is checked whether the temperature is higher than the set temperature. Accumulate and store. However, when the internal temperature of the linear amplifier is maintained at a temperature in a normal range, the TEMP counter that accumulates and stores the time value maintained in the high temperature state is cleared.

The CPU911 outputs a second selection signal SEL2 for selecting the output VSWR of the standing wave ratio detector 813 in step 1151, and the abnormal selector 818 outputs the VSWR of the standing wave ratio detector 813 by the second selection signal SEL2. Select and output to CPU911. In this case, the standing wave ratio detector 813 receives a final RF signal output from the divider 234, detects a difference between an output voltage and a voltage reflected from an output terminal, and then, if the difference between the two voltages exceeds a set voltage value, the VSWR signal. Set it.

Then, the CPU911 analyzes the state of the VSWR signal. If the VSWR signal is set, the linear amplifier LPA detects that the standing wave ratio is abnormal at the output in step 1151, and checks whether the VSWR flag is already set in step 1155. . If the VSWR flag is not set, the CPU911 detects that the standing wave ratio of the linear amplifier LPA is in an abnormal state for the first time in step 1155, sets the VSWR flag in step 1157, and then, in step 1159, the standing wave ratio is abnormal. Drives the VSWR counter to accumulate the time output in the state. However, if the VSWR flag is set in step 1155, the CPU911 detects that the VSWR is in an abnormal state even in a previous state, and increases the value of the VSWR counter in step 1161 to output the standing wave ratio to an abnormal state. Accumulate the values.

However, if the VSWR detection signal is not set in step 1153, the CPU911 detects that the standing wave ratio of the linear amplifier LPA is normal, clears the VSWR flag in step 1163, and then sets the value of the VSWR counter in step 1165. Clear

Therefore, referring to steps 1151 to 1165 of FIG. 11B, after detecting the standing wave ratio of the linear amplifier LPA, it is checked whether the standing wave ratio is out of the normal range. The time output in the abnormal state is accumulated and stored, and when the standing wave ratio of the linear amplifier LPA is maintained within a normal range, the VSWR flag and the VSWR counter are cleared.

The CPU911 outputs the second selection signal SEL2 for selecting the output DCF of the power failure detector 814 in step 1171, and the error selector 818 outputs the DCF of the power failure detector 814 by the second selection signal SEL2. Select to output to CPU911. At this time, the power fault detector 814 checks the power supply of the linear amplifier LPA output from the power supply unit (PSU) and sets the DCF signal when the power supply unit (PSU) is out of the set power supply range or when a specific voltage is shorted. .

Thereafter, the CPU911 analyzes the state of the DCF signal. If the DCF detection signal is set, the CPU911 detects that the power supply supplied to the linear amplifier LPA is abnormal in step 1171, and checks whether the DCF flag is already set in step 1175. do. If the DCF flag is not set, the CPU911 detects an abnormal state of the power supplied to the linear amplifier LPA in step 1175, sets the DCF flag in step 1177, and then supplies the abnormal supply power in step 1179. Drive DCF counter to accumulate time value. However, if the DCF flag is set in step 1175, the CPU911 detects that the power supply is abnormal even in the previous state, and in step 1181, the value of the DCF counter is updated to supply the supply power to an abnormal state. Accumulate time values.

However, if the DCF detection signal is not set in step 1173, the CPU911 detects that the power supplied to the linear amplifier LPA is in a normal state, clears the DCF flag in step 1183, and then, in step 1185, the DCF counter Clear the value.

Therefore, when the operation of steps 1171 to 1185 of FIG. 11B is performed, it is checked whether the power voltage supplied to the linear amplifier LPA is out of the set range. This time is accumulated and stored, and when the power supply voltage of the linear amplifier LPA is supplied in a normal range and when a specific power supply is normally supplied, the value of the DCF counter is cleared.

Fifth, the CPU911 outputs the second selection signal SEL2 for selecting the output LOP of the loop error detector 815 in step 1191, and the error selector 818 outputs the loop error detector 815 by the second selection signal SEL2. Select to output to CPU911. At this time, the loop fault detector 815 inputs the output of the canceller 219 distributed in the divider 233, and detects the magnitude of the non-offset RF signal included in the output of the canceller 219. If so, the LOP is set to indicate a loop fault condition.

The CPU911 analyzes the state of the LOP signal in step 1193. If the LOP detection signal is in the set state, the CPU911 detects that the RF signal is not canceled by the canceller 219, and checks whether the LOP flag is already set in step 1195. do. At this time, if the LOP flag is not set, the CPU911 detects that the loop error has occurred for the first time in step 1195, sets the LOP flag in step 1197, and then the time at which the loop gain state continues in step 1199. Drive LOP counter to accumulate values. However, if the LOP flag is set in step 1195, the CPU911 detects that the loop is in an abnormal state even in a previous state, and increases the value of the LOP counter in step 1201 to determine a time value at which the loop abnormal state is maintained. Accumulate.

However, if the LOP signal is not set in step 1193, the CPU911 detects that the loop is normally performed by canceling the RF signal in the canceller 219. After clearing the LOP flag in step 1203, the LOP in step 1205 is performed. Clear the counter value.

Therefore, in operation 1191 to step 1205 of FIG. 11C, the output of the canceller 219 is examined to determine whether the RF signal is normally canceled. When the offset of the RF signal is out of the set range, it is determined that the loop is abnormal and the loop abnormality is continued. Time is accumulated and the RF signal is normally canceled, and the loop is determined to be normal and the LOP counter is cleared.

Sixth, the CPU911 outputs the second selection signal SEL2 for selecting the output LWP of the low power detector 816 in step 1211, and the fault selector 818 selects the output LWP for the low power detector 816 based on the second selection signal SEL2. To the CPU911. At this time, the low power detector 816 detects the voltage difference between the input RF signal and the output RF signal distributed by the dividers 231 and 234, and if the voltage difference between the two RF signals does not have a value within a set range, the gain of the linear amplifier LPA is decreased. The LWP signal is set to indicate that it is not in a steady state.

The CPU911 analyzes the state of the LWP signal. If the LWP signal is set, the CPU911 detects that an abnormal state of the overall gain of the linear amplifier LPA has occurred in step 1213, and checks whether the LWP flag is already set in step 1215. do. At this time, if the LWP flag is not set, the CPU911 detects that the gain abnormal state of the linear amplifier LPA is first generated in step 1215, sets the LWP flag in step 1217, and then sets the linear amplifier in step 1219. It drives the LWP counter to accumulate the time value at which the LPA over-gain condition occurs. However, if the LWP flag is set in step 1215, the controller detects that the LWP flag is in an abnormal state even in a previous state. In step 1221, the value of the LWP counter is increased to accumulate a time value for the abnormal state.

However, if the LWP signal is not set in step 1213, the CPU911 considers that the gain of the linear amplifier LPA maintains its normal state, and after clearing the LWP flag in step 1223, the value of the LWP counter in step 1225. Clear

Therefore, referring to operation 1211-1225 of FIG. 11C, when the voltage difference between the input RF signal and the output RF signal of the linear amplifier LPA is out of the set range, the sensor detects an abnormal state of the overall gain of the linear amplifier LPA and the gain is abnormal. This duration is accumulated and stored, and when the voltage difference between the two RF signals is within a setting range, the LWP counter is cleared by determining that the overall gain of the linear amplifier LPA is normal.

Seventh, the CPU911 outputs the second selection signal SEL2 for selecting the output FAN of the fan error detector 817 in step 1231, and the error selector 818 outputs the fan error detector 817 according to the second selection signal SEL2. Select to output to CPU911. At this time, the fan error detector 817 inputs a fan driving signal located in the linear amplifier LPA and checks the state of the fan driving signal to set the FAN signal when the fan driving is not normally performed.

The CPU911 analyzes the state of the FAN signal. If the FAN signal is set, the CPU911 detects that an abnormal state has occurred in the fan driving in step 1233 and checks whether the FAN flag is already set in step 1235. At this time, if the FAN flag is not set, the CPU911 detects that an abnormality has occurred in the fan drive for the first time in step 1235, sets the FAN flag in step 1237, and then drives the fan abnormally in step 1239. Drive FAN counter to accumulate time value. However, if the FAN flag is set in step 1235, the fan is detected to be in an abnormal state even in a previous state. In step 1241, the value of the FAN counter is increased to accumulate a time value at which the abnormal state continues. .

However, if the FAN signal is not set in step 1233, the CPU911 detects that the fan is normally driven, and in step 1243, clears the FAN flag, and then clears the value of the FAN counter in step 1245.

Therefore, referring to operation 1231-1245 of FIG. 11D, the driving signal of the fan for cooling the heat of the linear amplifier LPA is analyzed to accumulate and store the time that the fan is driven in an abnormal state when the fan driving abnormal state occurs. When the fan is driven normally, the FAN flag and the FAN counter are cleared.

As described above, each of the linear amplifier LPAs constituting the composite linear amplifier has an overpower, high temperature, standing wave ratio abnormality, supply power abnormality, loop abnormality, and overall gain abnormality within the corresponding unit for each first set time. Check the status of fan operation abnormality. At this time, in order to display the relevant status for the occurrence of the abnormal status, the relevant abnormal flag is set and the time for which the abnormal status is maintained is accumulated and stored in the corresponding alarm counter.For the normal items, the flag and counter of the relevant status are stored. Clear it.

As described above, the linear amplifiers LPAs check and process the occurrence of abnormal conditions, and then check the values of the respective flags and counters to turn on / off corresponding RF switches of the power distribution module 100 and the power synthesis module 300. Perform the action.

Referring to the above process, the CPU911 reads flags indicating the presence of an abnormal state in step 1251 to analyze the results of processing in steps 1111 to 1245 in step 1251. In this case, the OVP flag is first read, and then in step 1253, the OVP flag is set. In this case, if the OVP flag is set, the process proceeds to step 1259. If the OVP flag is clear, the process proceeds to step 1255 to check whether the flag currently read is the last flag. In this case, if it is not the last flag, the process proceeds to step 1257 and the next flag is read and the state of the flag read in step 1253 is checked. Therefore, the state of the flag is checked while reading sequentially from the first OVP flag to the last FAN flag.

At this time, if the set flag indicating that the abnormal state is checked in the process of performing the operation, the CPU911 recognizes this in step 1253 and reads the value of the counter corresponding to the corresponding flag in step 1259. At this time, the counter is in a state of accumulating and storing the time value of the corresponding abnormal state as described above. After reading the counter value, the CPU911 checks whether the value of the counter corresponding to the flag indicating the abnormal state is the second set time value in step 1261. Here, the second set time value is a time set to stop the operation of the linear amplifier LPA, and is set to about 7 seconds in the embodiment of the present invention. If the cumulative time stored in the abnormal counter maintains the value within 7 seconds, the process returns to step 1255 and the state of the next flag is checked.

However, when the accumulated time value stored in the counter is the second set time value in step 1261, the CPU911 generates a switch control signal SWC for cutting off an RF signal input / output to the corresponding linear amplifier LPA in step 1263, and the communication unit 916. Outputs alarm information generated at At this time, the alarm information output through the communication unit 916 is applied to the operator side and processed. When the switch control signal SWC is generated, the corresponding RF switch SWI of the power distribution module 100 is turned off and the corresponding RF switch SWO of the power synthesis module 300 is turned off. Therefore, the linear amplifier LPA in which the abnormal condition is generated automatically stops the amplification operation because the passage of the RF signal is blocked.

In this case, as described above with reference to FIG. 2, the power distribution module 100 has an output terminal connected to the linear amplifier LPA in which an abnormal state is generated. Thus, the power of the RF signal input to the node NI is in a linear amplifier LPA in an abnormal state. It is applied evenly to the remaining linear amplifiers LPA except for. In addition, since the input terminal connected to the linear amplifier LPA in which the abnormal condition occurs in the power synthesis module 300 is open, the output path of the linear amplifier in the abnormal state is blocked, and only signals output from the linear amplifiers in the normal state are Composite output.

Therefore, as described above, if any linear amplifier LPA constituting the composite linear amplifier occurs, the corresponding linear amplifier LPA automatically blocks the RF path connected to it, and the synthetic linear amplifier is a normal linear amplifier LPA. After evenly distributing the power of the RF signal, the linear amplification operation is performed and the amplified signal is synthesized again. In this case, since the RF amplification signal is generated without loss of signal power in the distribution and synthesis process, it can be seen that the synthesized linear amplifier can amplify and output the RF signal having a predetermined size.

After activating the switch control signal SWC as described above, the CPU911 sets a switch-off flag to indicate that the switch control signal SWC is turned off in order to block the current RF signal in step 1265, and 1267. Activate the switch-off timer in step. The switch-off flag is a flag indicating that the amplification operation is interrupted because the passage of the RF signal is interrupted when the current linear amplifier LPA is abnormal. The switch-off timer is a timer for accumulating and storing a time value at which the amplification operation is stopped. When the RF switch is cut off, the CPU911 accumulates and stores flags indicating abnormal states such as OVP, TEMP, VSWR, DCF, LOP, LWP, FAN, and the duration of the abnormal state in steps 1269 and 1271. Clear all timers.

In steps 1251 to 1271 of FIG. 11D, after checking each state at a first set time period, if a specific abnormal state continues for a second set time, the RF switch is turned off to stop the operation of the corresponding linear amplifier. It sets the switch off flag for and drives a switch off timer that accumulates the cutoff time of the RF switch. At this time, the linear amplifier LPA having an abnormal state is restarted after a set time elapses, in order to determine whether or not the previous abnormal state is temporary. Therefore, the switch off timer is a timer for determining a time to restart after the RF switch is shut off. In addition, the reason for clearing the flags and timers after the RF switch is blocked as described above is to detect the presence of an abnormal state when restarting again.

However, if the switch-off flag is set in step 1103, the RF switch of the linear amplifier LPA corresponding to the power distribution module 100 and the power synthesis module 300 is turned off. In this case, the CPU911 checks whether the switch SWI and SWO have passed the third set time. This is to check whether the abnormal state of the linear amplifier LPA is temporary or fatal by stopping the driving of the linear amplifier LPA by turning off the switches SWI and SWO and restarting the linear amplifier LPA again after a certain time. Accordingly, the CPU911 reads the switch off timer value in step 1285, and then checks whether the value of the switch off timer has passed the third set time in step 1287. If the value of the switchoff timer has not passed the third set time, the process proceeds to step 1289 to update and return the value of the switchoff timer.

Once the switchoff flag is set as described above, the CPU911 turns off the switch SWI-SWO until the value of the switchoff timer becomes a value of the third set time. In this case, when the value of the switch-off timer reaches the third set time in step 1287, the CPU911 reads a value of a switch-off counter in step 1291. Here, the switch-off counter is a counter for accumulating and storing the number of times of switching off. When the number of times of the switch is greater than or equal to a predetermined number of times, the linear amplifier LPA controls to stop further driving because a fatal abnormality has occurred. Therefore, when the value of the switch-off counter exceeds the set number N, the CPU911 detects this in step 1293, sets to stop the operation of the linear amplifier LPA in step 1305, and controls the communication unit 916 to control the corresponding linear. Notify the occurrence of abnormal condition of the amplifier.

However, when the value of the switchoff counter is not N in step 1293, the CPU911 turns on the switch control signal SWC in step 1295 and outputs release information of the corresponding alarm through the communication unit 916. Therefore, by automatically outputting the abnormal state detection and release state of the synthesized linear amplifier through the communication unit 916, the operator can determine whether the abnormal state of the device. In addition, when the switch control signal SWC is turned on, it means that the linear amplifier LPA is restarted after the third set time has elapsed while the operation is stopped due to the abnormal state of the linear amplifier LPA. In this case, the RF switch SWO and SWI of the power distribution module 100 and the power synthesis module 300 are turned on by the switch control signal SWC, and the corresponding linear amplifier LPA forms a passage through which the RF signal can be input and output. In step 1297 and 1299, the CPU911 clears the switch-off flag and the switch-off timer and increases the value of the switch-off counter to prepare for the next state. In operation 1303, the CPU911 returns after activating the switch-on flag and the switch-on timer.

When the first set time has not elapsed in step 1101, the CPU911 reads the switch-off counter value in step 1311, and then checks the value of the switch-off counter in step 1313. At this time, if the value of the switch-off counter is not "0", it means that there is a state in which the operation of the linear amplifier LPA is stopped in the previous state. In this case, it is necessary to clear the value of the switch-off counter if the switch-on time is constant. That is, even if the normal function is restored after the accumulated number of times of switching off in the switchoff counter is accumulated and stored, the corresponding number of times is still stored in the switchoff counter. Therefore, in the embodiment of the present invention, if the linear amplifier LPA maintains the normal state for more than the fourth predetermined time, it is determined that the linear amplifier LPA operates normally and the value of the switch-off counter is cleared. The fourth set time is set to have a larger value than the third set time. Therefore, if the value of the switch-off counter is not 0 in step 1313, the value of the switch-on timer is updated in step 1315, and is the value of the switch-on timer a fourth set time value in step 1317? Check it. At this time, if the value of the switch-on timer exceeds the fourth set time value, the CPU911 clears and returns the switch-off counter value in step 1319.

The operation of the abnormality detector 238 having the above configuration is summarized in Table 1 below.

TABLE 1

As described above, the synthesized linear amplifier according to the embodiment of the present invention checks the outputs of the detectors as shown in Table 1 in the first setting period, and sets the flag of the corresponding detector when an abnormal state signal is generated in any detector. Activates a timer to store the duration of the. The above process is repeated to check the output of each detector, and then the states of the flags are sequentially checked. At this time, if there is no flag set in the inspection process, since the linear amplifier LPA performs a normal operation, it returns and waits until the next first set time. At this time, the linear amplifier LPA is in a state of waiting for the detection operation, and a passage for inputting an RF signal with the power distribution module 100 and the power synthesis module 300 is formed. Accordingly, the power distribution module 100 distributes power to the input RF signal so as to correspond to the number of linear amplifiers LPA, and each linear amplifier LPA outputs power after linearly amplifying the RF signal. Then, the power synthesis module 300 synthesizes and outputs the amplified RF signals output from the linear amplifiers LPAs.

However, if any flag among the flags of the detectors is set in the checking process, the timer values of the corresponding detectors are sequentially read to check whether the second set time value has elapsed. At this time, if the second set time value has not passed, the timer value is updated and then waits until the first set time is reached. However, when the timer value of the detector has passed the second set time, it is determined that the abnormal state of the linear amplifier LPA is a serious state, so that the corresponding linear amplifier LPA switches SWI of the power distribution module 100 and the power synthesis module connected thereto. And SWO off. Then, the power distribution module 100 is open to the input terminal of the RF signal connected to the linear amplifier, thereby distributing the power of the RF signal to be input to the linear amplifier LPA, and inputs to the linear amplifier LPA that is normally driven. In addition, since the input terminal connected to the linear amplifier LPA having an abnormal state is opened, the power synthesis module 300 outputs power amplified RF signals output from the normal linear amplifier LPAs. At this time, the linear amplifier LPA in the abnormal state in the linear amplifier module 200 is blocked by the passage of the RF signal, the linear amplification operation is stopped, since the normal linear amplifier LPA inputs a higher level RF signal by the power distribution module 100 As a result, the linear amplified output of the RF signal has a larger gain. Therefore, the power of the final RF signal synthesized and output from the power synthesis module 300 has the same value as the power of the RF signal in a normal state.

When the linear amplifier is stopped due to an abnormal state as described above, the linear amplifier stops the operation for a third set time, and then turns on the switches SWI and SWO of the power distribution module 100 and the power synthesis module 300 again. The same detection operation is performed again. This is to check whether the abnormal state of the linear amplifier LPA is temporary or fatal. Therefore, the linear amplifier LPA performs a detection operation again and checks whether an abnormal state occurs. In this case, when the abnormal state is maintained for more than the second predetermined time, the linear amplifier LPA blocks the RF signal input / output path of the linear amplifier LPA again and the third set time is Wait until it elapses. This operation is repeated N times, and if the abnormal state persists until N times, the linear amplifier LPA stops further detection operation and notifies the outside.

However, if it is determined that the state of each detector is in the normal state during the detection process, the linear amplifier LPA checks the value of the counter to check whether the linear amplifier LPA is stopped in the previous state. At this time, when the operation is stopped, the linear amplifier LPA checks the normal driving time, clears the value of the counter when the fourth set time elapses, and transitions back to the normal driving state.

Here, the first set time may use a timer interrupt signal that is repeatedly generated at a predetermined period. In this case, the set time may be set to "fourth set time> third set time> second set time> first set time". . In the embodiment of the present invention, it is assumed that the second set time is set to 7 seconds and the third set time is set to 1 minute.

12A, B, C, and D are flowcharts illustrating a state inspection and control process of the linear amplifier LPA according to the second embodiment of the present invention.

12a, b, c, and d, the CPU 111 first checks the output of the mounting sensor 917 in step 1402 to determine whether the corresponding linear amplifier LPA is mounted on the power distribution module 100 and the power synthesis module 300. In this case, when the mounting sensor 917 generates an unmounted signal, the CPU911 detects it in steps 1402 and turns off the switches SWI and SWO connected to the power distribution module 100 and the power synthesis module 300 in steps 1404 and 1406 and returns. However, if it is mounted in step 1402, the CPU911 checks whether the linear amplifier LPA is first installed in step 1406. If the linear amplifier LPA is first installed, the CPU911 turns on the RF switch SWI connected to the power distribution module 100 and the RF switch SWO connected to the power synthesis module 300 in step 1408, and then proceeds to step 1410. Begin the operation of the linear amplifier LPA. However, if it is not initially installed in step 1406, the process returns to step 1410 immediately to start the operation of the linear amplifier LPA.

The operation state inspection of the linear amplifier LPA is performed in units of time. Therefore, when the CPU911 detects that the alarm test period has been reached in step 1410, the alarm check time is initialized in step 1412, and then the output of the error detector 238 is sequentially selected to check whether there is an error. In this case, it is assumed that the inspection time is performed in a 200 msec cycle. Therefore, the CPU911 repeatedly executes the routine as shown in FIGS. 12A, B, C, and D at a 200 msec period.

The CPU911s of the linear amplifiers LPAs constituting the synthesized linear amplifying apparatus sequentially input the outputs of the abnormality detector 238 having the configuration as shown in FIG. 9 to determine whether there is an abnormality. The CPU911 selects the output of the overvoltage detector 811 in step 1422 to 1428 and checks whether there is an overvoltage of the linear amplifier LPA. Check whether there is an abnormality of standing wave ratio of the linear amplifier LPA by selecting the output of the standing wave detector 813 in steps 1442-1448, and selecting the output of the power abnormality detector 814 in steps 1452-1458. Examine the linear amplifier LPA for power abnormality, select the output of the loop error detector 815 in steps 1462-1468, and check the loop abnormality of the corresponding linear amplifier LPA for the low power detector 816 in steps 1472-1478. Select the output of the linear amplifier LPA to check if the transmit power is low power, and select the output of the fan fault detector 817 in steps 1482 to 1488. It checks the presence of error in the cooling state of the linear amplifier over the LPA.

When an abnormal signal is detected in the process of checking the outputs of the detectors 811-817, the CPU911 turns on the alarm corresponding to the detector and drives the corresponding alarm counter. If the alarm state is maintained while the alarm counter is already driven, the CPU911 maintains driving of the corresponding alarm counter to accumulate and store an occurrence time of the alarm. This is performed in steps 1426, 1436, 1446, 1456, 1466, 1476, and 1486, which process the corresponding alarms in FIGS. 12A, 12B, 12C, and 12D, respectively. You can do something similar to

When the output of the detector is returned to normal in the process of checking the output of each of the detectors 811-817, the CPU911 initializes the value of the corresponding alarm counter. This is performed in steps 1428, 1438, 1482, 1458, 1468, 1478, and 1488, respectively, to process the corresponding alarms in FIGS. 12A, B, C, and D, respectively. You can do something similar.

As described above, when the CPU911 inputs an abnormal signal from an arbitrary detector, the corresponding alarm counter is counted and accumulated after driving the corresponding alarm counter, and the alarm counter is initialized when the detector is returned to a normal state. To delete the accumulated time.

After checking the states of the detectors by performing step 1488, the CPU911 checks whether the outputs of all the detectors are normal in step 1492. In this case, when the output of each detector maintains its normal state, the CPU911 detects this in step 1492, initializes all alarm counters in step 1494, and then connects a linear amplifier LPA to the power distribution module 100 and the power synthesis module 300. After the switch SWI and SWO are turned on, the process proceeds to step 1402.

However, when the output of the arbitrary detector outputs an abnormal signal in step 1492, the CPU911 reads the alarm counter value of the abnormal state in step 1502, and compares the value of the alarm counter read in step 1504 with the reference time value. do. Here, the reference time value is a time for turning off the switches SWI and SWO when the alarm generation time elapses for a predetermined time, and is preferably set to about 7 seconds as in the first embodiment. If the value of the alarm counter is less than the reference time in step 1514, the CPU911 proceeds to step 1506 and checks whether there is another alarm in an abnormal state. At this time, if there is another alarm, the CPU911 proceeds to step 1502 and repeats the operation of comparing the alarm counter value with the reference time value, and if not, returns to step 1402 and waits until the next inspection period.

However, if the value of the alarm counter is greater than the reference time value in step 1504, this means that an error condition that is fatal to the corresponding linear amplifier LPA is exceeding a set time. In this case, the CPU911 controls the communication unit 916 in step 1508 to transmit the alarm of the corresponding abnormal state to the operator side. In step 1510, the CPU911 initializes the values of all the alarm counters, and in step 1512, turns off the switches SWI and SWO connected to the power distribution module 100 and the power synthesis module 300, and cuts the input / output of the corresponding linear amplifier LPA. Terminate the routine.

In this case, the linear amplifier LPA is separated from the synthesized linear amplifier. Therefore, the power distribution module 100 is equally distributed and applied to the linear amplifiers normally operated. Then, the linear amplifiers in the operating state are further distributed and amplified and output the input signals, and the power synthesizer 300 synthesizes and outputs the signals output from the linear amplifiers. Therefore, it can be seen that the output of the synthesized linear amplifier performs the same power amplification function even when an abnormality occurs in the arbitrary linear amplifier in the synthesized linear amplifier.

In the state checking and control method of the composite linear amplifier according to the first embodiment, if the alarm is maintained for a predetermined time, the linear amplifier is stopped after the operation of the linear amplifier is restarted, and the operation is repeated for a predetermined number of times. If the linear amplifier continues to be abnormal during the operation, the linear amplifier is completely stopped. However, the method of checking and controlling the condition of the composite linear amplifier according to the second embodiment is performed when the corresponding linear amplifier is maintained for a predetermined time. It is a method to stop the operation of the amplifier. At this time, in the second embodiment, a method using one counter may be used without separately providing counters for accumulating and storing the abnormal state duration of each state. In other words, it is very unlikely that several types of abnormal conditions will occur simultaneously in the linear amplifier. Therefore, it is necessary to simply check whether there is an alarm when checking each alarm condition and accumulate the alarm occurrence time using one counter. In this case, two or more alarms may be generated. However, this case is extremely rare. Therefore, the linear amplifier operation can be controlled by determining whether the linear amplifier is abnormal by a simple method.

As described above, the composite linear amplifier according to the embodiment of the present invention blocks linear input / output paths when the linear amplifiers periodically check their state and detect an abnormal state. In this case, the power distribution module and the power synthesis module are applicable. The linear amplifier is determined to be open and the power of the RF signal is distributed and synthesized. Therefore, even if an error occurs in any linear amplifier in the synthesized linear amplifier, the same RF signal can be synthesized and amplified. In addition, the linear amplifiers constituting the synthesized linear amplifier can perform a linear amplification function according to their own status by self-diagnosing their own condition, and also has the advantage of notifying the external operator of the linear amplifier status.

Claims (11)

In a synthetic linear amplifier, Lines connected between one input terminal and a plurality of output terminals, and a switch is connected to each output terminal, the power distribution module for distributing the power of the input RF signal to the output terminal, respectively; A power synthesis module having lines configured to be connected between a plurality of input terminals and one output terminal, and a switch connected to each input terminal, for synthesizing and outputting power of input RF signals; Connected between the output terminal of the power distribution module and the input terminal of the power synthesis module, linearly amplifies the RF signal distributed in the power distribution module and outputs the RF signal to the power synthesis module. Consists of linear amplifiers that block the passage of the signal, The power distribution module, A first input line connected between the RF signal input terminal and a common input node and having a Z1 characteristic impedance; Second input lines connected in parallel to the common input node and having Z2 characteristic impedance; Third input lines each connected to the second input lines and having a Z3 characteristic impedance; An RF switch connected between the third input lines and the linear amplifiers and controlled by the linear amplifier, And each of the first to third input lines has a length of λ / 4, and when the RF switch is turned off, a corresponding output terminal is opened and totally reflected to the common input node. The method of claim 1, wherein the power synthesis module, RF switches connected to the output terminals of the linear amplifiers and controlled by the linear amplifiers; Third output lines connected to the corresponding RF signal and having a Z3 characteristic impedance; Second output lines connected to the corresponding third output lines and a common output node and having a Z2 characteristic impedance; A first output line connected to the common output node and having a Z1 characteristic impedance, And the first to third output lines each have a length of λ / 4, and when the RF switch is turned off, a corresponding input terminal is opened and totally reflected to the common output node. The method of claim 2, wherein the linear amplifiers, A feedforward linear amplifier includes detectors for detecting a corresponding abnormal state therein, and analyzes an output of the detectors to turn off RF switches of the corresponding power distribution module and the power synthesis module when the abnormal state is detected. Synthetic linear amplifier. The method of claim 3, wherein the detectors, An overvoltage detector for inputting an output of a linear amplifier and detecting an overvoltage abnormal state by comparing the output voltage with a set output voltage; A high temperature detector having a temperature sensor and detecting an abnormal state of a high temperature by comparing an internal temperature and a set temperature of the linear amplifier detected by the temperature sensor; A standing wave ratio detector configured to input an output of the linear amplifier and detect an abnormal state of standing wave ratio by detecting a difference between an output voltage and a reflected voltage of the linear amplifier; A power supply abnormality detector for inputting a supply power supply of the linear amplifier and detecting the supply power supply to detect a supply power supply abnormality state when the supply power supply is out of a set power supply range; A loop fault detector for inputting an output of an RF cancel circuit and detecting a loop fault condition in which an RF signal output from the cancel circuit is greater than a set value; And a low power detector configured to input an input and an output signal of the linear amplifier, and detect a low power abnormal state that is less than or equal to a set value by detecting a voltage difference between the two signals. The apparatus of claim 4, wherein the characteristic impedance of the lines is Z2 > Z3 > Z1. In the synthesized linear amplifier comprising a power distribution module for distributing the power of the RF signal and a power synthesis module for synthesizing, A plurality of linear amplifiers are connected between corresponding output terminals of the power distribution module and each input terminal of the power synthesis module, and RF switches are connected to the input and output terminals of the linear amplifiers, respectively, and the linear amplifiers operate in a self-operating state. Diagnose and cut off the corresponding RF switch when an abnormal condition occurs, The linear amplifier, An overpower detector configured to input an output of a linear amplifier and detect an overpower abnormal state by comparing the output voltage with a set output voltage; A high temperature detector having a temperature sensor and detecting a high temperature abnormal state by comparing an internal temperature and a set temperature of the linear amplifier detected by the temperature sensor; A sperm wave ratio detector for inputting the output of the linear amplifier and detecting an abnormal state of standing wave ratio by detecting a difference between the output voltage and the reflected voltage of the linear amplifier; A power supply abnormality detector for inputting a supply power supply of the linear amplifier and detecting the supply power supply to detect a supply power supply abnormality state when the supply power supply is out of a set power supply range; A loop fault detector for inputting an output of an RF cancel circuit and detecting a loop fault condition in which an RF signal output from the cancel circuit is greater than a set value; A low power detector configured to input an input and an output signal of the linear amplifier and detect a low power abnormal state that is equal to or less than a set value by detecting a voltage difference between the two signals; And turning off the corresponding RF switch when an abnormal state is detected by analyzing the outputs of the detectors. The method of claim 6, wherein the power distribution module, A first input line connected between the RF signal input terminal and a common input node and having a Z1 characteristic impedance; Second input lines connected in parallel to the common input node and having Z2 characteristic impedance; Third input lines each connected to the second input lines and having a Z3 characteristic impedance; An RF switch connected between the third input lines and the linear amplifiers and controlled by the linear amplifier; And each of the first to third input lines has a length of λ / 4, and when the RF switch is turned off, a corresponding output terminal is opened and totally reflected to the common input node. The method of claim 6 or 7, wherein the power synthesis module, RF switches connected to the output terminals of the linear amplifiers and controlled by the linear amplifiers; Third output lines connected to the corresponding RF switch and having a Z3 characteristic impedance; Second output lines connected to the corresponding third output lines and a common output node and having a Z2 characteristic impedance; A first output line connected to the common output node and having a Z1 characteristic impedance, And the first to third output lines each have a length of λ / 4, and when the RF switch is turned off, a corresponding input terminal is opened and totally reflected to the common output node. In the transmission signal amplification control method of a communication system, A power distribution process for equally distributing and outputting the output power in an amount corresponding to the number of output stages of the transmitted RF signal; A plurality of linear amplification modules input the power-distributed transmit RF signal, each of which self-diagnoses its own state, interrupts the input and output paths in an abnormal state, and stops the linear amplification operation. Linearly amplifying and outputting an RF signal; The linearly amplified RF signals are composed of a power synthesis process for synthesizing and transmitting power. And the number of output stages in the power distribution process is equal to the number of input paths of the linear amplification module in the plurality of linear amplification modules. The method of claim 9, wherein the self-diagnosis process of the linear amplification module, Determining whether there is an abnormal state of transmission power in a first set time unit, accumulating an abnormal state duration time at an abnormal state, and initializing a cumulative time if normal; In the process, after the abnormal state holding time increases the number of stops when the second set time exceeds, the linear amplification operation is interrupted for a third set time by interrupting the input and output paths of the linear amplification module. Going back to the process, And checking the number of stops after the third set time elapses, and when the set number is exceeded, the linear amplification operation is completely terminated. Otherwise, the linear amplification control method of the communication system comprises reverting to the abnormality determination process. . The method of claim 9, wherein the self-diagnosis process of the linear amplification module, Determining whether there is an abnormality of the transmission power in a first set time unit, accumulating an abnormal state duration time when the abnormal state is normal and initializing the accumulated time when the normal state is normal; In the process, if the abnormal state holding time increases the number of stops when the second preset time is exceeded, interrupts the linear amplification operation by interrupting the input and output paths of the linear amplification module, otherwise returning to the abnormality determination process. A method for synthesizing linear amplification of a transmission signal of a communication system, characterized in that consisting of: a.

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