KR100324056B1 - Pixel control circuit for spatial light modulator - Google Patents

Abstract

There is provided a spatial light modulator 10 having a reduced control circuit compared to conventional devices. The set of pixel elements 11 divides the memory cells 12 such that each memory cell 12 has the same fanout as the other memory cells 12. Each pixel element 11 in the set is switched on or off via a reset line 13 which is separated from the reset line of other pixel elements 11 in the set. The frame data is loaded into the divided bit frames during the set time period so that each divided bit frame includes only the data for the pixel elements 11 in one reset line 13. Thus, the same memory cell 12 can be used to transfer data to all pixel elements 11 at that fanout since only one pixel element 11 in the fanout is switched at a time.

Description

Pixel Control Circuit for Spatial Light Modulator

The present invention relates to a spatial light modulator, in particular a deformable mirror device and circuitry for controlling the on and off states of individual pixel elements.

The spatial light modulator (SLM) consists of an array of electronically addressable pixel elements and control circuits associated therewith. Typical applications are for image displays in which the light from each pixel is magnified and projected onto the display screen by the light system. The type of modulation depends on how the modulator couples with the optical system.

A commonly used SLM type is a deformable mirror device, which is a tiny micro-mechanical mirror in which each pixel element can move individually in response to electrical input. Incident light may be reflected from each pixel and modulated in direction, phase or amplitude.

In many applications, SLMs are binary in that each pixel element can have one of two states. The fact that the device can be turned off means that it does not transmit light. Alternatively, the fact that the device can be turned on means that it transmits light at maximum intensity. Various pulse width modulation techniques can be used to enable the viewer to sense medium levels of light. These techniques are disclosed in pending US Pat. No. 07 / 678,761, entitled “DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System”, assigned to the same assignee as the present application.

In general, pulse width modulation produces integrated brightness by switching each pixel on or off for a period corresponding to a binary number in each frame. Pulse width modulation uses several designs to load the SLM, such as "bit frame" loading, where one bit per pixel is loaded for the entire frame at a time. Each pixel element has a memory cell. The entire array of memory cells is loaded at one bit per cell, and then all pixel elements are set corresponding to that bit frame of data. During the display time of the current bit frame, the data for the next bit frame is loaded. Thus, for example, for 8-bit pixel luminance quantization, the SLM is loaded eight times per frame, one pixel per frame at a time. In this way, the most significant bit is displayed for half of the frame period, the second most significant bit for one quarter of the frame period, and so on, and the least significant bit (LSB) is 1/2 ⁿ frame period for n-bit luminance quantization. Indicates the display time.

The problem with traditional pixel loading techniques is that at least one method per pixel device is present.

Mori is required. As the number of pixels per frame increases, the cost of the memory for the SLM device increases and the yield decreases. In SLM there is a need to reduce the circuitry to control the pixel elements.

The loading scheme using memory cells per pixel element also limits the minimum time that the pixel element can be set to the time required to load the bit frame into the memory array. When pulse width modulation is used, the display time for the LSB is the shortest display time. During this LSB time, data for the next frame must be loaded. This is the time period when a "peak" data rate is required. In order to satisfy this peak data rate, a predetermined pin count and the data frequency of these pins must be used. High peak data rates transition to high pin counts and / or high frequencies, which increases device and / or system cost. There is a need to reduce this peak data rate for SLM.

A first feature of the invention is a spatial light modulator (SLM) which individually controls each pixel element that can be set and reset in one of two states depending on the value of the data signal delivered to the pixel signal. The SLM has an array of pixel elements each having two possible states depending on the value of the data signal transmitted from the associated memory cell to the pixel element. The SLM also has a plurality of memory cells each in data communication with a set of pixel elements. Each memory cell stores a data value indicative of an on or off state of a set of pixel elements, and transmits a signal representing this data value to the set of pixel elements. Multiple reset lines are connected to the pixel elements such that other reset lines communicate with each pixel element in the set. Thus, the reset line can be used to reset only one pixel element of the set at a time.

The technical advantage of the present invention is that a single memory cell controls a set of multiple pixel elements. This reduces the circuit per pixel, which has the effect of reducing device cost and increasing production yield. In addition, the peak data rate at which loading must be performed is reduced because the memory cells for loading any one reset are few. This further has the effect of reducing pin count and / or data frequency requirements and lowering device and / or system cost.

Pixel array interconnect

1 is a partial block diagram of an SLM array 10 having a pixel element 11 controlled by a memory cell 12 and a reset line 13. Only a few pixels 11 with associated control circuits are shown, but a typical SLM array 10 will have thousands of such elements 11. FIG. 1 is primarily for illustrating how each memory cell 12 serves the multiple pixel element 11. Additional details regarding the interconnection between the pixel element 11, the memory cell 12 and the reset line 13 are described below with reference to FIGS. 2 to 5.

For purposes of explanation, the SLM 10 is a device known as a deformable mirror device (DMD). A DMB is an array of tiny micro-mechanical mirror elements that can be modulated to allow the observer to detect intensity changes. Has One example of a DMD is a DMD device manufactured by Texas Instruments Inc. However, the present invention is not limited to the use of the DMD for the SLM 10, but may also be used for other types of SLMs having similar characteristics, that is, addressable pixel elements operating according to data signals and reset control signals as described below. .

The pixel element 11 is operated in a bistable mode, meaning two stable states. As will be described later in connection with FIG. 3, the direction of movement is controlled by " loading " the data from the memory cell 12 via an address electrode for " driving " the pixel element 11. As will also be described later with reference to FIG. 3, the state of the pixel element 11 is changed in accordance with the drive voltage by applying a differential bias through the reset electrode. The term " reset signal " is used herein to represent a signal transmitted to the pixel element 11 to change state.

The pixel elements 11 are classified into sets of four pixel elements 11 each set in communication with a memory cell 12. The number of pixel elements 11 in the set associated with a single memory cell 12 is referred to as the " fanout " Thus, in FIG. 1, each memory cell 12 has a "fan out" of four pixels. Although the present invention can be applied to other fanout values, four fanouts are used here as an example.

Each memory cell 12 may be a conventional static random access memory (SRAM) cell. One of the advantages of many recent designs for the SLM 10 is that they can be easily integrated onto the underlying CMOS control circuitry. This description relates to memory cells 12 each having a single bit storage capacity. However, the scope of the present invention may also include "memory cells" that store more than one bit or have additional logic circuitry. For example, each memory cell 12 may have a double buffer configuration.

Four reset lines 13 control the time for which the pixel element 11 changes its state. When all the memory cells 12 for the pixel element 11 connected to the specific reset line 13 are loaded, the state of the pixel element 11 responds to the reset signal on the reset line 13 and at the same time the data loaded thereto. Will change accordingly. In other words, the pixel elements 11 retain their current state when the data supplied to them from their memory cells 12 changes and until a reset signal is received.

Each pixel element 11 in the set of four pixel elements associated with the memory cell 12 is connected to the other of the four reset lines 13. Thus, each pixel element 11 in the set can change its state from the state of other pixel elements 11 in the set at different times.

In general, each set of pixel elements 11 associated with memory cells 12 has the same number of pixel elements, which is equal to the number of reset lines 13. However, they may be the same case as on the edge of the pixel element array where the memory cells 12 are connected to a few pixel elements.

2 shows a set of four pixel elements 11, their memory cells 12 and reset lines 13 and associated interconnects. Each pixel element 11 is labeled with respect to the reset line 13 connected thereto. That is, the pixel element 11 (A) is connected to the reset line 13 (A). As noted, one of the "1" or "0" values may be passed to the pixel element 11. When memory cell 12 is switched, one of these values is transmitted to all pixel elements 11 to which memory cell 12 is connected. The signal on the reset line 13 of each pixel element 11 determines whether the pixel element 11 changes state.

3 is a cross-sectional view illustrating a single pixel element 11 in the form of a typical DMD of the SLM 10. Spatial light modulation is provided by the reflecting mirror 31 inclined in one of two directions. The two stable states of the mirror 31 are indicated by dotted lines. In the stable position, one end of the mirror 31 is moved towards one of the two landing electrodes 32. The two address electrodes 33 are connected to the output of the memory cell 12 whose fanout includes its pixel element 11. The reset voltage is applied to the conductive mirror 31 by the reset electrode 34. The address electrode 33 is used to apply a voltage difference so that one end of the mirror 31 is attracted to the electrode 33 underlying it and the other end is pushed out. The reset voltage at the electrode 34 determines whether the mirror 31 will actually rotate in response to the landing electrode 32. Thus, the mirrors 31 are " loaded " through their memory cells 12 and reset via the reset line 13. If inclined in the selected direction, the pixel element will be "on" to face the display screen, otherwise it will be inclined so that light is directed differently, such as in a trap.

4 is a partial top view of an array of pixel elements 11 through which reset line 13 is through torsion hinges 41. Each pixel element 11, indicated by dotted lines, as in FIGS. 1 and 2, is associated with a memory cell 12 having a fan out of four pixel elements 11. In this embodiment, the pixel element 11 has a conductive mirror 31 and a conductive torsion hinge 41 so that reset can be applied directly to the mirror 31 through the hinge 41 without spatial connection or insulation. In FIG. 4, each mirror 31 has a pair of hinges 41, and the pixel elements 11 are aligned such that the hinges 41 follow the horizontal line, and the connection to the reset line 13 is a horizontal line thereof. Is made easy to follow.

5 shows another arrangement of the SLM 10. As in FIG. 4, the fanout of each memory cell 12 is a vertically spaced set of pixel elements 11. However, the reset connection follows the orthogonal reset line 13. As in Figures 2 and 3, each pixel element 11 is labeled for a reset line 13 to which it is connected. That is, the pixel element 11 (A) is connected to the reset line 13 (A). This arrangement will be used for the SLM 10 because the hinge 41 of the pixel element is advantageous for aligning the pixel element 11 such that it follows an orthogonal line.

Operation of the invention

For pulse width modulation, the operation of the SLM 10 is generally consistent with existing pulse width modulation techniques in that an n-bit value indicates the luminance of each pixel element 11 during the frame period. Each bit of the n-bit value represents the time during which the pixel element 11 is on or off. The number of bits of the n-bit value is referred to herein as the "bit depth."

For example here, it is assumed that each pixel element 11 displays light for one frame according to a bit depth of 5 bits. Thus, for example, four pixel elements 11 in a set associated with a single memory cell 12 have the following data during a single frame.

First pixel A B C D E

Second pixel F G H I J

3rd pixel K L M N O

4th pixel P Q R S T

Where {A B C D E} represents a 5-bit binary value. The value of each bit is "1" or "0" representing one of two possible states for the pixel element 11.

If "1" in the LSB position represents the "on" value of one hour unit, then "1" in the MSB position is 16 hours with intermediate bits ranging downwards as 8, 4 and 2 hour units are required. Will indicate the unit. If bit 4 is an MSB and bit 0 is an LSB, the time is represented by each "1" of the bit value.

Bit 4 (MSB) 16 Hour Unit

Bit 3 8 Hour Unit

Bit 2 4 time unit

Bit 1 2 time unit

Bit 0 (LSB) 1 time unit

Therefore, the larger the 5-bit value, the longer the pixel element 11 is turned on during the frame, and the pixel element 11 becomes brighter than the other pixel element 11 during that frame.

Further details of the pulse width modulation technique are described in US Pat. No. 07 / 678,761, which is mentioned in the background section of this patent application and used herein by reference.

The pulse width modulation technique described herein takes advantage of the fact that some on or off times are long compared to the switching rate capability of the memory cell 12. An important premise of the present invention is that a single memory cell 12 can be used for multiple pixel elements 11 if the data loading is sequenced such that only one of the pixel elements 11 requires resetting at the same time.

In general, the sequencing used to load each frame of data depends on the fanout and bit depth. Various sequences are possible, but a sequencing requirement is that two pixel elements 11 in the set do not have to be loaded at the same time.

In addition to the provisions in the foregoing context, some "arbitrary" provisions may apply. If a fanout of m pixel elements is assumed, this definition of HAD states that all m pixel elements 11 are loaded in the first m time unit at the beginning of the sequence. Thus, each pixel element 11 of each set is loaded into a continuous series of initial time slices. This rule results in good separation between frames with a maximum skew of m time units between the end of one frame and the beginning of the next frame. Also, the data loaded during the first m-1 time slice should not be LSB data. Finally, the data for any one pixel element 11 must start and end at the same position with respect to the frame. This is because the number of data units used for data loading for a bit depth of n bits is 2 ⁿ -1 data units.

Figure 6 shows an example of data sequencing for memory cell 12 having four fanouts and applying all of the above rules. Thus, when m = 4 and each load step takes one unit of time, the four pixel elements 11 associated with the memory cells 12 are loaded with the same data but only one pixel element 11 is reset. The pixel element associated with the first reset line 13 (A) is designated as the pixel element 11 (A), and the same also applies to the following.

The loading sequence of FIG. 6 is for the following 5-bit data frame.

Load pixel [11 (A)] into bit 4, reset 13 (A)

Load pixel [11 (B)] into bit 3, reset 13 (B)

Load pixel [11C]] into bit 2 and reset 13 (C).

Load pixel [11 (D)] into bit 3, reset 13 (D)

Skip 2 LSB time units

Load pixel [11 (C)] to bit 4, reset 13 (C)

Skip 2 LSB time units

Load pixel [11 (B)] to bit 0, reset 13 (B)

Load pixel [11 (B)] into bit 1, reset 13 (B)

Load pixel [11 (D)] to bit 1, reset 13 (D)

Load pixel [11 (B)] into bit 4, reset 13 (B)

Load pixel [11 (D)] to bit 0, reset 13 (D)

Bit 2 Load pixel [11 (D)], reset 13 (D)

Skip 1 LSB time unit

Load pixel [11 (A)] to bit 0, reset 13 (A)

Load pixel [11 (A)] into bit 2, reset 13 (A)

Load pixel [11 (D)] to bit 4, reset 13 (D)

Skip 2 LSB time units

Load pixel [11 (A)] into bit 3, reset 13 (A)

Load pixel [11 (C)] to bit 0, reset 13 (C)

Load pixel [11 (C)] to bit 1, reset 13 (C)

Skip 1 LSB time unit

Load pixel [11 (C)] into bit 3, reset 13 (C)

Skip 2 LSB time units

Load pixel [11 (B)] into bit 2, reset 13 (B)

Load pixel [11 (A)] into bit 1, reset 13 (A)

Skip 1 LSB time unit

Buffering with a frame buffer (not shown) can be used to order the data in the correct sequence. The frame of data (data filling the array of SLMs 10) is divided into four "split bit frames". For the first divided bit frame, bit 4 for each pixel element 11 (A) in each set associated with memory cell 12 is appropriate for loading during the time unit such that one quarter of the SLM 10 is loaded. Will be ordered. Then, all bits 3 for each pixel element 11 (B) will be ordered as a second divided bit frame for loading, and so on.

The overall effect of data sequencing is that for each frame the entire array of pixels 11 is reset to a group of pixels rather than all at once. Thus, the reset takes place in a "divided reset" pattern. That is, these pixel elements 11 connected to the single reset line 13 are switched at the same time.

As with conventional pulse width modulation techniques, it takes 2 ⁿ −1 LSB time units to display the entire n bit frame. However, each load step is done with a small increase in memory, thereby saving time. In the example of the present description, one quarter of the bit frame is loaded for every reset signal. In other words, four reset signals are used per bit frame. Unlike conventional pulse width modulation techniques, each bit frame can display data from other bits.

As a result of the loading technique of the present invention, the peak data rate is reduced. Also, while loading occurs more often per frame, higher value bits no longer coincide for all pixel elements 11. Thus, there is no need to wait for the display time of these higher value bits. The average data rate and peak data rate converge more closely.

The maximum fanout per memory cell 12 depends on the bit depth. When the bit depth is n, the theoretical maximum fanout is calculated as follows.

The numerator of the equation indicates that there are 2 ⁿ -1 time slices per frame. The denominator indicates that each panau is needed n times.

Computer programs are developed and used to determine appropriate sequences for varying bit depth and fanout. A program based on rules will prevent violations of the above-described rules that prevent resetting one or more pixel elements 11 in a set as well as other arbitrary rules at a time.

An improved method of the present invention combines the above-described "partial reset" and "block clearing". Block clearing has been used in conventional pulse width modulation schemes to avoid the problem of loading an entire bit frame during an LSB time unit. For block clearing, a bit frame is loaded in the entire multiple LSB time unit. A mechanism is provided on the SLM 10 to cause all pixel elements 11 to be "cleared" quickly, ie switched to an "off" state. Thus, these bit frames where the "on" time is shorter than the time required for loading can be properly loaded. The total number of time units in the frame exceeds the maximum luminance time by the number of time units used for clearing. Thus, the result of having the pixel element 11 in the "off" state during part of the loading is a reduction in the optical effect of the SLM 10. General features of block clearing are disclosed in US patent application Ser. No. 07 / 678,761.

Malfunction Tolerence

FIG. 7 shows the improvement of the SLM 10 of FIGS. 1-5, in particular relating to the interconnection between each memory cell 12 and the pixel element 11 in its fanout. A resistive element, in this case a resistor 71, is included in each data connection to reduce the effect of a malfunction in any one pixel element 11. For example, a short in one of the pixel elements 11 will not cause the rest of the pixel elements 11 in the set to malfunction.

As mentioned above, a feature of many SLMs 10 is that they are easily manufactured using integrated circuit processes. In this type of SLM 10, resistor 71 may be made of polysilicon material. Alternatively, high resistive materials can be used for electrode contact. In addition, for the extra resistive regions or devices, the overall fabrication level for pixel device electrodes such as electrode 33 in FIG. 3 is a high sheet resistance value such as titanium nitride or titanium oxynitride. It can be made of a material having a.

8 illustrates another malfunction tolerance improvement of the SLM 10. Instead of the resistor 71, a diode 81 is used as the resistive element to separate it from malfunctions in any one pixel element 11.

9 shows the third malfunction tolerance improvement. The fuse 91 is designed to "blow" if the pixel element 11 is shorted. Zener diode 92 or the same other breakdown diode provides high resistance to ground.

Another embodiment

Although the invention has been described with reference to specific embodiments, this description is not to be construed in a limited sense. Various modifications of the disclosed embodiments as well as alternative embodiments will be apparent to those skilled in the art. Therefore, it is contemplated that the appended claims cover all modifications within the true scope of the invention.

1 is a partial block diagram of an SLM array having memory cells with fanout of four pixel elements.

2 shows a memory cell with a fanout of four pixels.

3 shows a bistable operation of a mirror element of the SLM.

4 and 5 show how the reset line can be easily connected to a torsion-hinge pixel element array having conductive mirrors and hinges.

6 shows an example of a data sequence for loading a frame of data into an array of memory cells each having a fanout of four pixel elements.

7-9 illustrate an improved embodiment providing improved malfunction prevention.

Explanation of symbols for the main parts of the drawings

10: SLM Array

11: pixel element

12: memory cell

13: reset line

31: reflective mirror

32: landing electrode

33: address electrode

34: reset electrode

71: resistance

81: diode

91: Fuse

92: Zener Diodes

Claims (16)

In the spatial light modulator, Array of pixel elements arranged in a set, each of the sets having a plurality of pixel elements, each pixel element may be peaked in one of two stable states selected according to the state at the address electrode in response to a reset signal has exist, Each associated with only one and one of the sets, storing a data value corresponding to an on or off pixel device state, and a plurality of communicating the stored data value with address electrodes of each of the pixel devices in the associated set. Memory cells, A plurality of reset lines associated with the pixel elements such that another reset line is in communication with each pixel element of each set of pixel elements, and A control circuit for successively loading data from one of a plurality of divided bit frames into the respective memory cells, and applying a reset signal to one of the reset lines in each set in accordance with a pulse width modulation sequence; Spatial light modulator comprising a. 2. The spatial light modulator of claim 1, wherein each set of pixel elements comprises four pixel elements. The spatial light modulator of claim 1, wherein the pixel element is a micro-mechanical bander element. 2. The spatial light modulator of claim 1, wherein the pixel element has a conductive mirror and the reset line is directly connected to the mirror via conductive torsion hinges. The spatial light modulator of claim 1, wherein the pixel element has a conductive torsion hinge, and the reset line is connected through the hinge. The spatial light modulator of claim 1, wherein the hinges are aligned in a horizontal row. The spatial light modulator of claim 1, wherein the hinges are aligned diagonally. 2. The device of claim 1, wherein each of the pixel elements further comprises a resistor element between an address electrode of the pixel element and a memory cell associated with the pixel element to isolate the pixel element if the pixel element malfunctions. Spatial light modulator. The spatial light modulator of claim 1, wherein each address electrode of the pixel element is made of a high resistance material for isolating the pixel element when the pixel element malfunctions. The spatial light modulator of claim 1, wherein the spatial light modulator is fabricated on an integrated circuit array of the memory cells. A method of pulse width modulating a frame of multi-bit frame data used by a spatial light modulator having an array of pixel elements, said pixel element having two stable states selected in accordance with a data signal applied to an address electrode in response to a reset signal. Configurable to one of and arranged in a set, each of the sets being associated with a single memory cell and each of the pixel elements in one set associated with a different reset line; Dividing a frame of data into a plurality of divided bit frames each containing data bits for pixel elements in each set, Loading one of the plurality of divided bit frames into the memory cell, each of the memory cells receiving a data bit indicating an on or off state for only one of the pixel elements; Applying the content of each memory cell to an address electrode of the pixel element in its associated set, Switching one of the pixel elements in each set by applying a reset signal to one of the reset lines associated with one of the plurality of divided bit frames, and Repeating the loading, applying and switching steps in accordance with a pulse width modulation sequence corresponding to the bit position of each divided bit frame in each set. 12. The method of claim 11 wherein the first applying step coincides with the start of a frame time period. 13. The pulse as claimed in claim 12, wherein the pixel element connected to each reset line receives at least one divided bit frame including higher value bits before receiving the divided bit frame including the least significant bit. Width modulation method. 12. The method of claim 11, further comprising dividing a frame period corresponding to each frame of data into the same time slice, wherein each time slice corresponds to a display time for the least significant bit of data in the frame of data. Pulse width modulation method characterized in that. 12. The method of claim 11 wherein the applying step and the repeating applying step are performed such that each pixel element in the set is loaded during a successive series of initial time slices. 12. The method of claim 11, wherein said applying step is performed such that data for any one pixel element in each set starts and ends at the same position associated with each frame.