KR100323371B1 - Method And System For Interface Junction Of Basic Rate Interface In The Exchange System - Google Patents

Abstract

The present invention relates to the U-interface matching of basic subscriber matching in the switching system, and more specifically, to the control board and each BRI (Basic Rate Interface) board using SA-BUS in the Integrated Service Digital Network (ISDN) block of the switching system. An interface matching system and method for basic subscriber matching in a switching system to provide U-interface matching with separate data transmission paths.

Conventionally, since the hardware solid lines for providing the corresponding U-interface matching, the PCM subhighway matching, and the slot identification number are separately configured, the circuit configuration becomes complicated in the backplane design, and each BRI board has the SC-BUS in common. As a result, there is a risk of data collision, and there is a problem in that high-speed data transmission and reception cannot be implemented because the transmission speed of the corresponding SC-BUS is low.

The present invention connects the SA-BUS, which can stably perform U-interface matching and PCM subhighway matching, between a control board and a plurality of BRI boards in an exchange system, thereby simplifying circuit configuration and designing a high-speed backplane. Data transmission and reception can be implemented, and by providing an independent transmission data bus for each BRI board, data collisions can be prevented during communication.

Description

Method and System for Interface Junction Of Basic Rate Interface In The Exchange System}

The present invention relates to the U-interface matching of basic subscriber matching in the switching system, and more specifically, to the control board and each BRI (Basic Rate Interface) board using SA-BUS in the Integrated Service Digital Network (ISDN) block of the switching system. An interface matching system and method for basic subscriber matching in a switching system to provide U-interface matching with separate data transmission paths.

In a conventional switching system, an SMP (Serial Communication Controller) of an integrated multiprotocol processor (IMP) is used for U-interface matching of basic rate interface (hereinafter referred to as 'BRI') of an ISDN block. It performs control board and Layer 3 communication at 256Kbps transmission speed through BUS (Serial Communication-BUS) and transmits and transmits PCM data at transmission rate of 4.906Mbps through separate PCM subhighway for PCM data communication.

Meanwhile, in the conventional exchange system, the BRI U-interface matching circuit includes a control including the SC-BUS interface unit 10-1 and the PCM subhighway interface unit 10-2 as shown in FIG. 1. SC-BUS (30) connected between the board (10), the plurality of BRI boards (20), and the corresponding control board (10) and BRI board (20) to perform BRI U-interface matching and separate PCM matching. ) And the PCM subhighway 40.

Each of the BRI boards 20 is commonly connected to the SC-BUS 30 on the back plain, and the BRI board 20 of 16 channels is mounted on the back plane, and the backplane on the control board 10 is provided. In order to confirm the position of each BRI board 20 mounted or detached on the drawing as shown in FIG. 2, each BRI board 20 is commonly connected by four hardware lines, and each slot identification number (Slot ID). Is represented by 4 bits (eg 0011).

The SC-BUS 30 is connected to the SC-BUS interface unit 10-1 of the control board 10 and is commonly connected to each BRI board 20 to communicate with the control board 10. Used for call processing and signaling, the transmission line of the 256KHz clock signal (SCC-CLK) provided by the control board 10, the transmission line of the 1ms frame synchronization signal (SCC-FS), and the control board ( 10) a data bus (SCC-RXD) for transmitting data, and a data line (SCC-TXD) and SC-BUS occupancy signal (TSCASRTB) for transmitting data of the BRI board 20. .

The PCM subhighway 40 is connected to the PCM subhighway interface unit 10-2 of the control board 10 and is commonly connected to each BRI board 20 to be used for transmission and reception of PCM data. 10) the transmission line of the 4.096 MHz PCM data clock signal MCLK, the transmission line of the 8KHz frame synchronization signal (FSB), the PCM data bus (PDR) for transmitting the PCM data of the control board 10, and It consists of a PCM data bus (PDX) for transmitting PCM data of the BRI board 20.

The operation of the BRI U-interface matching circuit in the conventional exchange system configured as described above is as follows.

Since the SC-BUS 30 is commonly connected to all the BRI boards 20 in the backplane, the control board 10 or the respective BRI boards 20 share a common SC-BUS occupancy signal (TSCASRTB). Attempt to occupy the corresponding SC-BUS 30 by checking the status of).

For example, in a state in which the first BRI board (BRI board # 1) occupies the SC-BUS 30, the control board 10 occupies the SC-BUS 30 so as to occupy the third BRI board (BRI board # 3). In case of transmitting data with), it is as follows.

First, the control board 10 checks the signal level of the SC-BUS occupancy signal TSCASRTB in order to check whether the SC-BUS 30 is currently being used. Because it is occupied by the 1BRI board, the corresponding SC-BUS occupied signal (TSCASRTB) is at the 'low' level.

Accordingly, the control board 10 may control the corresponding SC- until the first BRI board releases the occupation of the SC-BUS 30, that is, until the corresponding SC-BUS occupation signal TSCASRTB transitions to the 'high' level. Holds the possession of the BUS 30 and waits.

Thereafter, when the first BRI board releases the occupancy of the SC-BUS 30 and the SC-BUS occupancy signal TSCASRTB becomes 'high' level, the control board 10 occupies the corresponding SC-BUS 30. Thereafter, the slot identification number (Slot ID) and data are transmitted to the third BRI board through the data bus (SCC-RXD) while the frame synchronization signal SCC-FS maintains the 'high' level.

Meanwhile, in order to transmit and receive data between the control board 10 and the BRI board 20 through the SC-BUS 30, the control board 10 is provided from the control board 10, as shown in the timing diagram shown in FIG. While the frame synchronization signal SCC-FS is maintained at the 'high' level, data transmission and reception is performed between the control board 10 and the BRI board 20 through the data buses SCC-TXD and SCC-RXD. .

In addition, in the BRI U-interface matching circuit of the conventional switching system, a signal line separate from the corresponding SC-BUS is used for PCM subhighway matching, and transmitting and receiving 4.906Mbps PCM data through the corresponding PCM subhighway 40. In order to maintain the 'high' level of the 8KHz frame synchronization signal (FSB) provided from the control board 10, the corresponding control board 10 and each BRI board 20, as shown in the timing diagram shown in FIG. Valid PCM data is transmitted and received through the PCM data buses (PDR, PDX).

As described above, in the conventional exchange system, the BRI U-interface matching circuit uses the control board 10 and each BRI board 20 to occupy the SC-BUS 30 to transmit and receive data at 256 Kbps, and is provided separately. PCM data is transmitted and received at the rate of 4.906 Mbps through the PCM subhighway 40.

However, in the related art, since a solid hardware line for providing the corresponding U-interface matching, the PCM subhighway matching, and the slot identification number is separately configured, the circuit configuration is complicated in the backplane design.

In addition, since each BRI board uses the SC-BUS in common, there is a risk of data collision, and there is a problem in that high-speed data transmission and reception cannot be implemented because the transmission rate (256Kbps) of the corresponding SC-BUS is low.

An object of the present invention is to solve the problems described above, and an object thereof is an interface including a SA-BUS that can stably perform U-interface matching and PCM subhighway matching in an exchange system and enables high-speed data transmission and reception. To provide a matching system.

Another object of the present invention is to provide an interface matching system and method that can prevent data collision during communication by providing independent data transmission paths for a plurality of BRI boards.

It is still another object of the present invention to provide an interface matching system and method that can simplify circuit configuration in backplane design by integrating a hardware structure for U-interface matching and PCM subhighway and slot identification number into one.

1 is a schematic diagram of a BRI U-interface matching circuit in a conventional exchange system.

FIG. 2 is a diagram showing solid lines connected in common in FIG. 1 to confirm mounting positions of respective BRI boards. FIG.

3 is a timing diagram of data transmission and reception performed through a conventional SC-BUS.

4 is a timing diagram of PCM data transmission and reception performed through a conventional PCM subhighway.

5 is a schematic diagram of a BRI U-interface matching system in an exchange system according to the present invention.

Figure 6 is a SA-BUS timing diagram between the control board and the BRI board in the present invention.

7 is a view showing a slot identification number of the BRI board in the present invention.

8 is a timing diagram of slot identification number recording of the BRI board through the SA-BUS in the present invention.

9 is a timing diagram of data transmission to a BRI board in accordance with the present invention.

10 is a timing diagram of data reception from a BRI board in accordance with the present invention.

11 is a flowchart illustrating a data transmission operation through SA-BUS according to the present invention.

12 is a flowchart illustrating a data receiving operation through SA-BUS according to the present invention.

Explanation of symbols on the main parts of the drawings

50: control board 50-1: SA-BUS interface unit

60: BRI board 70: SA-BUS

In order to achieve the above object, an aspect of the present invention provides a switching system for performing a basic subscriber matching function, comprising: a plurality of subscriber matching boards performing digital subscriber matching and activated by a valid bit included in control data; A control board for controlling an operation mode of the plurality of subscriber matching boards using the time-divided control data; It includes the SA-BUS to provide an independent data transmission path for the control board and subscriber matching board.

Another aspect of the invention, the process of identifying the mounting position of each subscriber registration board; Reading a reception flag of a subscriber matching board to which data is to be transmitted and checking whether the flag indicates a completion of access of the subscriber matching board; If the received reception flag is a flag indicating completion of access to the subscriber registration board, setting the subscriber registration board in the recording mode and transmitting data length information and transmission data; And receiving the transmitted transmission data at the subscriber matching board.

Still another aspect of the present invention provides a method, comprising the steps of: reading a transmission flag of a subscriber matching board when the read mode is set by the control board to determine whether it is a flag indicating completion of access to the control board; Transmitting data length information and transmission data when the read transmission flag is a flag indicating completion of control board access; And receiving the transmitted transmission data in the control board.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the switching system according to the present invention, the interface matching system of basic subscriber matching includes a control board 50 including a SA-BUS interface unit 50-1 and digital subscriber matching, as shown in FIG. 5. A plurality of BRI boards 60 (corresponding to subscriber matching boards) and SA-BUS (Serial Access-BUS, 70) providing data transmission paths for the corresponding control board 50 and each BRI board 60 are provided. It is made.

Each corresponding BRI board 60 is connected to the control board 50 via SA-BUS 70 for BRI subscriber registration, control data, D-channel signaling and packets between the Peripheral Processor and the subscriber board. It is used for transmitting and receiving data.

Thus, 32 BRI boards 60 having 16 channels are mounted in the backplane of the switching system, accommodating 512 (16 channels x 32) ISDN subscribers and 1024 (32 channels x 32) general subscribers.

The SA-BUS 70 is a serial access bus, which is used to transmit and receive control data, D-channel signaling and packet data, and PCM data to communicate with the control board 50. It is connected to the SA-BUS interface unit 50-1) and provides an independent data transmission path for each BRI board 60.

In addition, the SA-BUS 70 transmits a 2.048 MHz data clock signal SCLK, a 4.096 MHz PCM interface clock signal PCLK, and an 8 KHz PCM frame synchronization signal SFS. Transmission line of data synchronization signal DCS for synchronization of lines, D-channel signaling and packet data, and transmission data bus CMD1 for transmitting D-channel signaling and packet data and PCM data of control board 50. ~ CMDn)) and transmission data buses SMD1 to SMDD for transmitting D-channel signaling and packet data and PCM data of the BRI board 60, wherein the corresponding transmission data buses CMD1 to CMDn and SMD1 to SMDn) is separately connected to each BRI board 60, and other transmission lines are commonly connected to each BRI board 60.

In the present invention configured as described above, the SA-BUS timing diagram between the control board 50 and the BRI board 60 is as shown in FIG. 6, where 'C5 to C0' is control data and 'P7 to P0' is shown in FIG. PCM interface data, 'D' means D-channel packet interface data, and 'S15 ~ S0' means D-channel signaling data, respectively.

When the control board 50 intends to read or record data through the SA-BUS 70, the control information is recorded through the transmission data bus CMD, and then the data is recorded on the BRI board 60. When the control mode is selected through the corresponding SA-BUS 70, the control unit 50 checks flags transmitted and received between the control board 50 and the BRI board 60 to transmit and receive data.

The operation of the BRI U-interface matching circuit according to the present invention configured as described above is as follows.

First, the control board 50 periodically transmits control data to each BRI board 60 through the transmission data bus CMD1 to CMDn to check the position of each BRI board 60 mounted on the backplane. The corresponding control data formats are shown in Table 1 below.

C5 C4 C3 C2 C1 C0 VAL DS4 DS3 DS2 DS1 DS0

In this case, 'C5' is a valid bit (Valid bit, VAL) indicating whether the BRI board 60 is activated, and 'C4 to C0' is a mode selection bit for selecting a control mode of the BRI board 60. (DS4 to DS0).

Then, the BRI board 60 checks the valid bit VAL of the control data input from the control board 50, and the valid bit VAL is bit '0' indicating activation of the BRI board 60. In this case, the operation of the control mode set by the corresponding mode selection bits DS4 to DS0 is performed.

That is, the BRI board 60 performs a corresponding operation according to the control mode determined by the control data output from the control board 50, as shown in Table 2 below.

VAL DS4 DS3 DS2 DS1 DS0 Control mode Contents 0 0 0 One 0 0 TXFWM TX flag record 0 0 0 One 0 One TXFRM TX flag reading 0 0 0 One One 0 RXFWM RX Flag Record 0 0 0 One One One RXFRM RX flag read 0 0 One One 0 0 LDWM Length / data record 0 0 One One 0 One LDRM Length / data readout 0 One One One One 0 SIDWRM Slot Identification Number Record 0 One One One One One SIDRDM Read Slot Identification Number

That is, the control board 50 periodically outputs control data (010111) to the BRI board 60 through the transmission data buses CMD1 to CMDn to set the BRI board 60 to the slot identification number reading mode (SIDRDM). Each BRI board 60 set in the corresponding slot identification number read mode SIDRDM checks the valid bit VAL of the control data 010111 to determine whether the bit '0' indicates an activation state.

If the valid bit VAL is '0', the corresponding BRI board 60 reads a slot ID stored in its FPGA (Field ProGrammable Array; not shown in the drawing). As shown in the timing diagram shown in FIG. 8, the 4-bit slot identification number 0x04 is transmitted to the control board 50 while the data synchronization signal DCS is maintained at the 'high' level.

Therefore, the control board 50 confirms the mounting position of each BRI board 60 by checking the input slot ID of the 4-bit.

In addition, a SRAM (Static RAM; not shown) of the BRI board 60 includes a TX flag area and a RX flag area. The transmission flag area includes a BRI board ( 60 is an area for transmitting data to the control board 50, and the reception flag area is an area for transmitting data from the control board 50 to the BRI board 60, and the control board 50 and the BRI. Both directions can be recorded / read by the board 60.

Flags shown in Table 3 below are recorded in the flag area of the BRI board 60.

Flag condition 0x00 SA-BUS initialization status 0x01 Control Board Access Time 0x02 Control board access completed 0x03 BRI board access time 0x04 BRI board access termination

In this case, when the corresponding flag is '0x01' or '0x02', it indicates that the control board 50 is being accessed, and when it is '0x03' or '0x04', the BRI board 60 is being accessed.

Therefore, when setting the BRI board 60 to the read mode, the control board 50 sequentially turns flags '0x01' and '0x02' to indicate the start and end of its access to the transmission flag areas of all the BRI boards 60. When the BRI board 60 is set to the recording mode, the flags '0x03' and '0x04' for indicating its own access start and end are sequentially recorded in the reception flag areas of all the BRI boards 60.

That is, the access subject is the control board 50, and when the data is transmitted from the control board 50 to the BRI board 60, the recording mode is entered, and the data is transferred from the BRI board 60 to the control board 50. In the case of transmission, the read mode is entered.

When the read mode of the BRI board 60 is set by the control board 50, the corresponding BRI board 60 has flags' 0x03 'and' for indicating the start and end of its access to its transmission flag area. 0x04 'is recorded in order, and when the recording mode of the corresponding BRI board 60 is set, the flags' 0x03' and '0x04' are sequentially recorded in the reception flag area of the BRI board 60 to indicate the access start and end. .

Therefore, when the mounting position of each BRI board 60 is confirmed by the 4-bit slot identification number, the control board 50 reads a reception flag from the reception flag area of the BRI board 60 to which data is to be transmitted, and reads it. Data is transmitted only when one reception flag is '0x04'.

Then, the BRI board 60 reads the transmission flag from its transmission flag area only when the valid bit VAL transmitted from the control board 50 is '0', and the read transmission flag is '0x02'. Only when data is sent.

In the BRI U-interface matching circuit according to the present invention as described above in detail the data transmission and reception operation through the SA-BUS 70 as follows.

First, an operation of transmitting data from the control board 50 to the BRI board 60 will be described with reference to FIG. 11.

The control board 50 confirms the mounting position of each BRI board 60 (step S10). At this time, the slot identification number periodically recorded by the control board 50 is stored in the FPGA of each BRI board 60. Since it is stored, the control board 50 sets each BRI board 60 to the slot identification number reading mode (SIDRDM), and then checks the slot identification number input from the corresponding BRI board 60 to determine each BRI board ( Check the mounting position of 60).

When the mounting position of each BRI board 60 is confirmed, the control board 50 reads a reception flag from the reception flag area of the BRI board 60 to which data is to be transmitted (step S11).

That is, the control board 50 outputs control data (000111) to a predetermined BRI board, for example, the first BRI board (BRI board # 1), and sets the first BRI board to the read mode (RXFRM). After that, the reception flag is read from the reception flag area of the first BRI board.

Subsequently, when reading of the reception flag is completed, the control board 50 checks whether the read reception flag is '0x04', which is a flag indicating completion of BRI board access (step S12), and if the reception flag is '0x04'. If not, the control board 50 returns to step S11 to perform a repeating operation.

However, if the corresponding reception flag is '0x04', the control board 50 records '0x01', which is a flag indicating the start of control board access, in the reception flag areas of all the BRI boards 60, and then the accompanying drawings. As shown in the timing diagram shown in FIG. 2, two bytes of length information DATA LENGTH of transmission data and the transmission data are successively transmitted to the first BRI board through the transmission data bus CMD1 (step S13). The control board 50 maintains the data synchronization signal DCS at a 'low' level by the length of the transmission data.

Subsequently, the control board 50 checks whether the transmission of the transmission data is completed (step S14). When the transmission of the transmission data is not completed, the control board 50 returns to step S13 to perform a repeating operation. When the transmission is completed, '0x02', which is a flag indicating completion of access to the control board, is recorded in the reception flag areas of all the BRI boards 60.

Then, the first BRI board writes '0x03', which is a flag indicating BRI board access start, in its reception flag area, and then starts reading the transmitted data and when the reading of the data is completed, the corresponding reception flag. '0x04', which is a flag indicating completion of BRI board access, is recorded in the area (step S15).

In addition, the control board 50 transmits data to all the BRI board 60 in the same manner as described above.

Next, an operation of transmitting data from the BRI board 60 to the control board 50, that is, receiving data from the BRI board 60 from the control board 50 will be described with reference to FIG. 12. As follows.

When the control board 50 periodically transmits control data for checking whether there is transmission data in each BRI board 60 through the transmission data bus CMD, the corresponding BRI board 60 is periodically controlled. Data, for example, control data (001101) is received (step S20).

Then, the BRI board 60 is set to the length / data read mode (LDRM) only when the valid bit VAL of the control data 001101 is '0', and reads the transmission flag from its transmission flag area ( (Step S21), at which time, the control board 50 makes the data synchronizing signal DCS transition to the 'low' level.

For example, a case in which the second BRI board (BRI board # 2) wants to transmit data to the control board 50 is as follows.

First, the second BRI board checks the valid bit (VAL) of the received control data and reads the transmission flag from its transmission flag area only when the bit is '0' indicating the activation state, and then the read transmission flag is controlled. It is checked whether or not the flag '0x02' indicating the board access is completed (step S22). If the corresponding transmission flag is not '0x02', the flow returns to step S21 to perform a repetitive operation.

By the way, if the transmission flag is '0x02', the second BRI board records '0x03', which is a flag indicating the start of BRI board access, in the transmission flag area, and then transmits the signal as shown in the timing chart shown in FIG. Two bytes of data length information DATALENGTH and the corresponding transmission data are successively transmitted to the control board 50 via the transmission data bus SMD2 (step S23).

Thereafter, the second BRI board checks whether the transmission of the transmission data is completed (step S24). If the transmission of the transmission data is not completed, the second BRI board returns to step S23 to perform a repeating operation. When the transmission is completed, '0x04', a flag indicating completion of BRI board access, is recorded in its transmission flag area.

Then, the control board 50 writes '0x01', which is a flag indicating the start of control board access, in the transmission flag area of all the BRI boards 60, and then starts to read the transmitted data to start reading the transmission data. Upon completion, '0x02', a flag indicating completion of access to the control board, is recorded in the transmission flag area (step S25). At this time, the control board 50 sets the data synchronization signal DCS as long as the length of the transmission data. Keep it low.

In addition, in the same manner as described above, each BRI board 60 transmits data to the control board 50.

In addition, the preceding embodiments in the present invention do not limit the claims by way of example only, and various alternatives, modifications, and changes will be apparent to those skilled in the art.

As described above, the present invention simplifies the circuit configuration in the backplane design by connecting the SA-BUS between the control board and the multiple BRI boards that can stably perform the U-interface matching and the PCM subhighway matching in the exchange system. At the same time, high-speed data transmission and reception can be realized, and by providing independent transmission data buses for each BRI board, data collisions can be prevented during communication.

Claims (13)

In an exchange system that performs basic subscriber matching function, A plurality of subscriber matching boards that perform digital subscriber matching and are activated by valid bits included in the control data; A control board for controlling an operation mode of the plurality of subscriber matching boards using the time-divided control data; And a SA-BUS providing independent data transmission paths to the control board and the subscriber matching board. The method of claim 1, The SA-BUS includes: a transmission line commonly connected to a plurality of subscriber matching boards for transmitting a clock signal and a synchronization signal from the control board to the subscriber matching board; And a transmission data bus that is separately connected to a plurality of subscriber matching boards for transferring data between the control board and the subscriber matching board. The method of claim 3, wherein The transmission line includes: a first transmission line for transmitting a data clock signal; A second transmission line for transmitting the PCM interface clock signal; A third transmission line for transmitting the PCM frame synchronization signal; And a fourth transmission line for transmitting the control data synchronization signal. The interface matching system of basic subscriber matching in a switching system. The method of claim 3, wherein The transmission data bus includes: a first transmission data bus for transmitting data from a control board to a subscriber matching board; And a second transmission data bus for transmitting data from the subscriber matching board to the control board. The method of claim 1, Each of the subscriber matching boards includes a memory indicating a signal transmission / reception state capable of bidirectional writing / reading, and comprising a transmission flag area for transmitting data from the subscriber matching board to the control board; And a receiving flag area necessary for transmitting data from the control board to the subscriber matching board. The method of claim 6, When setting the subscriber matching board reading mode, the control board sequentially records flags indicating start and end of access to the control board in the transmission flag areas of all subscriber matching boards, and sets all subscriber matching boards when setting the subscriber matching board recording mode. The interface matching system of the basic subscriber matching in the switching system, characterized in that the flag indicating the control board access start and end in order in the receiving flag area. The method of claim 6, When the subscriber match board read mode is set by the control board, the subscriber match board writes flags indicating start and end of access to the subscriber match board in its transmission flag area, and the subscriber match board write mode is set by the control board. If set, the interface matching system of the basic subscriber matching in the switching system, characterized in that the flag indicating the start and end of subscriber matching board access in the receiving flag area. The method of claim 1, Each subscriber matching board includes a logic circuit that stores its own slot identification number, and the control board periodically checks the mounting position of each subscriber matching board by recording / reading the slot identification number with respect to the logic circuit. Interface matching system of basic subscriber matching in the switching system, characterized in that. Checking a mounting position of each subscriber matching board; Reading a reception flag of a subscriber matching board to which data is to be transmitted and checking whether the flag indicates a completion of access of the subscriber matching board; If the received reception flag is a flag indicating completion of access to the subscriber registration board, setting the subscriber registration board in the recording mode and transmitting data length information and transmission data; And receiving the transmitted data at the subscriber matching board. 2. The interface matching method of basic subscriber matching in a switching system. The method of claim 10, The process of confirming the mounting position of each subscriber matching board may include verifying the mounting position of the corresponding subscriber matching board by periodically recording / reading a slot identification number for a logic circuit provided in each subscriber matching board. Interface matching method of basic subscriber matching in system. The method of claim 10, The reception flag of the subscriber matching board includes a flag indicating start and end of control board access, which are sequentially recorded in the reception flag areas of all subscriber matching boards by the control board, and start of subscriber registration board access, which is sequentially recorded by the subscriber matching board. And a flag indicating a termination and an interface matching method of basic subscriber matching in a switching system. When the read mode is set by the control board, reading the transmission flag of the subscriber matching board to confirm whether the flag indicates completion of access to the control board; Transmitting data length information and transmission data when the read transmission flag is a flag indicating completion of control board access; And receiving the transmitted data from the control board. The interface matching method of basic subscriber matching in a switching system. The method of claim 13, The transmission flag of the subscriber matching board is a flag indicating the control board access start and end which are sequentially recorded in the transmission flag area of the subscriber matching board to be set to the read mode by the control board, and are sequentially recorded by the subscriber matching board. A method of interface matching of basic subscriber matching in a switching system, comprising a flag indicating access and termination of subscriber matching board access.