KR100322550B1 - Booth multiplier and design - Google Patents

Abstract

PURPOSE: A booth multiplier and a digital filter for adopting the same are provided to create a multiplicand of a negative number simply without using an incrementer. CONSTITUTION: A booth table(202) includes transformation information for transforming a multiplicand in accordance with a multiplier being inputted by a predetermined booth algorithm. An encoder(204) transforms the multiplicand being inputted in accordance with the transformation information, generates a transformed multiplicand, and generates an increment control signal necessary for transforming into a multiplicand of a negative number. The encoder(204) outputs a coded result being expressed as 1's complement for creating a multiplicand of a negative number.

Description

Booth multiplier and digital filter employing it {Booth multiplier and design}

The present invention relates to a booth multiplier and a digital filter employing the same, and more particularly, to a booth multiplier and a digital filter employing the same that can implement the generation of the negative multiplier without using an increaser to reduce the delay caused by hardware size and operation will be.

In general, a booth algorithm, which is widely used in the implementation of a multiplier, has been improved in various forms because a function of multiplying a plurality of bits at a time and a two's complement multiplication can be easily solved.

Here, the booth algorithm does not compare the multiplier and the multiply bit by bit when performing the multiplication, but instead of multiplying the multiplicand by multiplying the multiplicand by multiplying the multiply according to the multiplier according to the recording table.

The simplest record table (abbreviated as booth table) for the booth algorithm is shown in Table 1 below.

Win count variant of the multiplicand corresponding to the i th bit i th bit i-1th bit 0 0

피승수0

multiplicand 0 One +1

multiplicand One 0 -One

Bloodman One One 0

multiplicand

피승수가 필요하고 이를 구현하려면 2의 보수 연산을 수행하여야 한다.In the booth table above, the multiplicand is transformed by multiplying the multiplicand by 0, +1, or -1 according to the multiplier in 2-bit units. As you can see from this booth table, -1

The multiplicand needs to be implemented and the two's complement operation must be performed.

In addition to the booth table mentioned in Table 1, there is a modified booth algorithm that compares three bits or more at the same time. However, all booth algorithms require multiplying the multiplicand by a negative value, that is, two's complement operation. To perform a two's complement operation, one usually takes a one's complement to the multiplicand, that is, inverts the multiplicand and adds one to the inverted result. When a number A having n bits is regarded as a multiplicand and expressed in binary, it is given by Equation 1.

A = X [n-1] ~ X [n-2] ~ X [n-3] ~ ... ~ X [1] ~ X [0]

To convert this to two's complement, invert each bit as shown in Equation 2.

A)에 수학식 3과 같이 1을 증가시켜야 한다.Inverted multiplicand (

In A), 1 should be increased as in Equation 3.

At this time, the incrementer necessary to calculate the two's complement is a half adder that increases in proportion to the n-bit input and the time delay also increases in proportion.

Implementing the booth algorithm or its modified form, the modified booth algorithm, requires multiplying the multiplicands according to the multiplier, and to implement a negative multiplicator, one of these variants, typically inverts the value of the multiplicand and adds one to the two's complement. I have made it.

Therefore, using a booth algorithm to implement a conventional booth multiplier requires two's complement to the multiplicand, and an incrementer is always needed to perform the function of adding the required one, which is an input bit. Since the number increases proportionally as the number increases, there is a problem of causing an increase in cost and computational delay in hardware implementation. In the case of a digital filter using multiple bus multipliers, there is a problem of causing a cost increase due to the increase of the multiplier.

In order to solve the above problems, it is an object of the present invention to provide a booth multiplier that simply implements the generation of a negative multiplicand without using an incrementer.

Another object of the present invention is to provide a digital filter for generating a negative multiplier using control information that an increase value is required for generating a negative multiplicant generated from a plurality of booth multipliers that do not use an increaser.

In order to achieve the above object, the booth multiplier according to the present invention is modified by modifying the multiplicand inputted in accordance with the booth table and the modified information is recorded in the deformation information for modifying the multiplier according to the multiplier input by a predetermined booth algorithm And an encoder for generating a multiplied multiplier and generating an increase control signal necessary for transforming to a negative multiplicand.

In order to achieve the above another object, the digital filter employing the booth multiplier according to the present invention is a deformation read from a booth table in which deformation information for modifying the multiplier according to n input multipliers by a predetermined booth algorithm is recorded. N booth multipliers for generating a modified multiplicand by transforming the input multiplicand according to the information, and generating an increase control signal necessary for transforming to a negative multiplicand, and converting the n multiply multipliers from a n booth multiplier according to the increase control signal. And an encoder for supplying the encoded increase value by encoding the increase value corresponding to the number, and an adder for adding the n modified multiplicands and the encoded increase value.

1 is a structure of a digital filter employing a conventional booth multiplier.

2 is a structure of a digital filter employing a bus multiplier according to the present invention.

3 is a diagram illustrating a structure of a first adder shown in FIG. 2.

Hereinafter, a preferred embodiment of a bus multiplier and a digital filter employing the same according to the present invention will be described with reference to the accompanying drawings.

First, a digital filter is an example to which the booth algorithm is applied. The structure of a conventional digital filter employing a booth multiplier using the booth algorithm is illustrated in FIG. 1 to assist in understanding the present invention.

In FIG. 1, for convenience of explanation, only one booth multiplier 100 of the plurality of booth multipliers determined by the number of input bits is shown.

The booth table 102 of the booth multiplier 100 may be, for example, the booth table shown in Table 1, and determines information of a certain form of deformation of the multiplicand b [0] according to the input multiplier a [0] ( +1, -1 or 0) is applied to encoder 108. In addition, since the deformation includes the modification to the two's complement, the booth table 102 indicates that "1" is represented by the incrementer (denoted by INC: 104) if the deformation requires the multiplicand to be a negative multiplicand. A selection control signal is applied to the multiplexer (denoted MUX: 106) to select the multiply multiplied and to otherwise input the multiplicand b [0].

The encoder 108 multiplies the multiplicand selected by the multiplexer 106 by the information (+1, -1 or 0) read out from the booth table 102, resulting in a multiplicand to which the booth algorithm is applied according to the multiplier bit value (hereinafter, modified). Abbreviated multiplier) is applied to the first adder 110.

In a digital filter, the operation of adding multiple multipliers simultaneously is a basic operation. Accordingly, the first adder 110 adds the outputs of multiple n-boos multipliers (multiple [0], ..., multiple [n-1]) to the barrel shifter 112 at the same time. At this time, the barrel shifter 112 increases and shifts the output of the first adder 112 in units of 1 bit if the booth multiplier uses the booth table shown in Table 1, and shifts the output of the first adder 112 if it is a modified booth multiplier. Shift in increments of two or more bits.

For example, when using the booth table shown in Table 1, the barrel shifter 112 shifts one bit from the second output of the first adder 112 and shifts the third output of the first adder 112 two bits. do. The control signal p applied to the barrel shifter 112 indicates how much to shift by a predetermined amount of shift action, and is also applied to the booth table 102.

The second adder 114 adds the output of the barrel shifter 112 and the accumulated value fed back from the accumulator 116 and applies it to the accumulator 116 again by an iterative sum of n multipliers and n multipliers. Multiply by and sum the sum result is output from the accumulator 112.

Therefore, the digital filter including the conventional bus multiplier shown in FIG. 1 requires an increaser, and an overall delay caused by the increaser.

However, the booth multiplier proposed in the present invention does not require an incrementer, and the digital filter employing the same may include one second encoder that performs the function of each incrementer required by the n booth multipliers corresponding to the number of input bits n. 206 to reduce overall delay and system cost.

The structure of the digital filter is shown in FIG. 2, and is shown as one booth multiplier 200 for convenience of description among a plurality of booth multipliers determined by the number of input bits. The booth multiplier 200 of the present invention is a booth table. 202 and a first encoder 204.

That is, according to the input multiplier a [0], the deformation information of the multiplier is read from the booth table 202 of the booth multiplier 200 and applied to the first encoder 204.

In this case, when the multiplicand b [0] input from the first encoder 204 needs to be transformed into a negative multiplicand, the output of the first encoder 204 may have a two's complement result using an incrementer as shown in FIG. 1. Rather than simply inverting the multiplier, i.e., the coded result represented by one's complement, changing the output value of the first encoder 204 back to two's complement is done in the first adder 208, where n is summed. . This one's complement is simply handled by simply inverting the input bits, eliminating the need for incremental operations and delays.

In addition, the first encoder 204 outputs the control information c [0] to the second encoder 206 indicating that an increase of 1 is required when transforming to a negative multiplicand. The generation of control information indicating that an increase of "1" for the two's complement operation is required in the first encoder 204 can be easily implemented in logic or a table.

Therefore, in a digital filter that performs multiplication on n-bit inputs simultaneously, the control information (c) indicates that an increase of 1 for the calculation of two's complement is required to generate a negative multiplier in each first encoder of the n booth multipliers. [0], ... c [n-1]), and the second encoder 206 generates n bus multipliers according to this control information (c [0], ... c [n-1]). It is supposed to generate a sum indicating how many of the booth multipliers should be transformed into a negative multiplicand.

In other words, the second encoder 206 adds the n control information c [0], ... c [n-1] to the first adder 208. The second encoder 206 can be simply configured by logic that adds the number of " 1 " among the values of the n control information c0, ..., c [n-1] and expresses it in binary.

The time delay that occurs due to the increaser is a coded increment sum output from the second encoder 206 and n encoded results multiple [0] output from each first encoder. The first adder 206 that adds multiple [n−1]) may be reduced by using a carry save adder (CSA). This carry save adder is a widely used adder when adding multiple inputs at the same time. It has a characteristic that almost no time delay occurs even if one input is added.

On the other hand, the first adder 208 simultaneously adds the outputs of the n number of bus multipliers (multiple [0], ..., multiple [n-1]) and the output sum of the second encoder 206 to the barrel shifter ( 210). At this time, the barrel shifter 210 shifts the output of the first adder 208 in accordance with the control signal p for controlling the number of shifted bits. This control signal p is also applied to the booth table 202.

The second adder 212 adds the output of the barrel shifter 210 and the accumulated value fed back from the accumulator 214 and applies it to the accumulator 214 again by an iterative sum of n multipliers and n multipliers. The result of multiplying and adding together is output from the accumulator 214.

On the other hand, in Fig. 3, for example, a carry save adder having n (= 15) output values (N0-N14) applied from each bus multiplier and one output value (N15) output from the second encoder 206 as an input. As illustrated, since the output of the CSA 216 inputting the output value N15 of the second encoder 206 is added to the latest, the time delay caused by the existing incrementer can be prevented.

Here, the CSA 216 into which the output of the second encoder 206 is introduced has a somewhat more complicated complexity than the conventional CSA, but has a smaller amount of logic than a conventional digital filter requiring n incrementers. As the number of bits increases, the hardware is greatly reduced.

The present invention implements the +1 increment function required to generate a negative multiplicand by the booth algorithm without using an incrementer to reduce the cost of the overall hardware and also to perform the sequential operations required for the increment function simultaneously with other operations. There is an effect of reducing the overall delay time of the multiplier according to the processing.

Claims (5)

A booth table in which deformation information for modifying the multiplicand is recorded according to a multiplier input by a predetermined booth algorithm; And And an encoder for generating a modified multiplicand by generating an input multiplier according to the deformation information, and generating an increase control signal necessary for transforming the multiplicand into a negative multiplicand. The booth multiplier according to claim 1, wherein the encoder outputs an encoded result represented by a one's complement inverting an input multiplicator to generate a negative multiplicand. For digital filters employing multiple booth multipliers: The modified multiplicand inputted in accordance with the deformation information read out from the booth table in which deformation information for modifying the multiplicand according to the n input multipliers is recorded by a predetermined booth algorithm to generate n modified multiplicands, and the negative multiplicand N booth multipliers for generating an increment control signal necessary to transform the circuit into a < RTI ID = 0.0 > An encoder for supplying an encoded increase value by encoding an increase value corresponding to a number transformed by a negative multiplicator in the n bus multipliers according to the increase control signal; And A first adder for adding the n modified multiplicands and the encoded increase value; A barrel shifter shifting according to a control signal indicating the number of bits for shifting the output of the first adder; A second adder for adding an output of the barrel shifter and a feedback value; And And an accumulator for accumulating the outputs of the second adder and outputting the sum values by multiplying n multipliers and n multipliers and outputting the sums. 4. The digital filter of claim 3, wherein the first adder consists of a plurality of carry save adders, and the coded increment is applied to a carry save adder that is added last. 4. The digital filter of claim 3, wherein the booth multiplier outputs an encoded result represented by a one's complement that inverts the input multiplicator to generate a negative multiplicand.

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