KR100322014B1 - Baseband Analog Chipset Performance Test Apparatus and Method for Digital Cellular Terminal - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a performance test apparatus and method for a baseband analog chipset that converts intermediate frequency signals, baseband analog signals, and digital signals from digital cellular terminals. The present invention relates to a device and a method for testing the baseband analog chipset performance even when the finished product is not implemented.

The present invention implements a predetermined program for interfacing with a baseband analog chipset in an FPGA, stores necessary data corresponding to the implemented program in a nonvolatile memory, and drives the baseband according to driving of the program and data. Generates an arbitrary frequency signal corresponding to the transmission system of the analog chipset, performs the test based on the result, converts the serial signal into a parallel signal, and processes the analysis of the logic analyzer, and converts the serial digital signal into a parallel digital signal. And a test apparatus for performing baseband analog chipset performance test according to the signal amplification degree, the number of signals, and the frequency control operation by performing A / D converter testing.

Description

Baseband Analog Chipset Performance Test Apparatus and Method for Digital Cellular Terminal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a performance test apparatus and method for a baseband analog chipset for converting intermediate frequency signals from baseband analog signals and digital signals in digital cellular terminals, and in particular, to a programmable digital FPGA terminal. The present invention relates to an apparatus and a method for testing the performance of the baseband analog chipset even when the finished product is not implemented.

In general, in order to implement a digital cellular terminal, an apparatus for converting an intermediate frequency (IF) band signal, a base band analog signal and a digital signal to each other is required as a chipset. The provided chipset is commonly referred to as a base band analog chipset (BBA). The baseband analog chipset demodulates IF signals to baseband, converts demodulated analog signals to digital signals, and vice versa in implementing AMPS, PCS, and CDMA cellular terminals. Converts the digital signal output from the modem device into an analog signal. The baseband analog chipset is an essential device for implementing a cellular terminal. In manufacturing a cellular terminal, a process for determining whether the BBA is normal is required, that is, a BBA performance test process. In particular, it is necessary to test whether the performance of the BBA in the reception system and the transmission system is normal.

Conventionally, in testing the performance of the BBA as described above, the cellular terminal was first configured as a finished product, and then the test was performed by the operation of the mobile terminal modem device matched with the BBA. Therefore, in order to test the performance of the BBA in the related art, a predetermined program for testing is pre-programmed and embedded in the mobile terminal modem device, and then a test operation is performed according to a call of the embedded program.

However, as described above, the BBA test method using the mobile terminal modem device can be performed only in a state where the cellular terminal is implemented as a finished product. Therefore, the limitation of the performance test is inevitably increased, and an error occurs in performing the performance test. If this is detected, there is a problem of inefficiency of disassembling the cellular terminal already implemented as a finished product, correcting the error of the BBA, and then assembling the finished product again.

In addition, the performance test of the BBA mainly aims at the performance test of the CDMA transmitter, the CDMA receiver, the FM transmitter, the FM receiver, and the serial A / D converter implemented in the BBA. As a result of the standard, there was a problem that the performance of the BBA cannot be objectively tested. These factors have led to problems of inefficiency such as an increase in manufacturing cost and an increase in manufacturing time in manufacturing a cellular terminal.

As a result, the conventional BBA performance test in the finished state can not produce a spreading signal according to the CDMA, PCS method in parallel to the mobile terminal modem chip has a problem that can not test the performance of the BBA required for transmission. In addition, although the entire terminal can be tested as implemented software separately, there was no way to test only BBA itself.

Accordingly, an object of the present invention is to provide an apparatus and method for testing the performance of a baseband analog chipset (BBA) as described above even when a programmable digital FPGA is not implemented in a digital cellular terminal. Is in.

In addition, another object of the present invention is to provide a test apparatus and method for objectively evaluating the performance of the BBA by testing the performance of the baseband analog chipset by performing an absolute evaluation criteria. have.

In order to achieve these objects, the present invention implements a predetermined program for interfacing with a baseband analog chipset in an FPGA, stores necessary data corresponding to the implemented program in a nonvolatile memory, and drives the program and data. According to the baseband analog chipset to generate a random frequency signal corresponding to the transmission system to perform the test through the results, and convert the serial signal to a parallel signal to process the analysis of the logic analyzer, and to process the serial digital signal A test apparatus and a method for performing a baseband analog chipset performance test according to the signal amplification degree, the number of signals, and the frequency control operation by performing the A / D converter testing by converting to a parallel digital signal are proposed. .

1 is a block diagram of a conventional digital cellular terminal.

2 is a diagram illustrating a test state of a baseband analog chipset through a test apparatus according to the present invention.

3 is a block diagram of an apparatus for testing baseband analog chipset performance according to a preferred embodiment of the present invention.

4 is a flowchart illustrating a process of implementing a test apparatus through an FPGA according to the present invention.

5 is a flowchart illustrating a process of testing a transmission system performance of a baseband analog chipset in a test apparatus according to the present invention.

6 is a flowchart illustrating a process of testing a reception system performance of a baseband analog chipset in a test apparatus according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The baseband analog chipset of the digital cellular terminal shown in the accompanying drawings will be described as an example of a chipset implemented to support the CDMA and AMPS scheme.

On the other hand, the baseband analog chipset is connected to the mobile terminal modem device to perform the above-described operation, a mobile terminal modem device that is commonly used as a "Mobile Station Modem (MSM)" of the US "Qualcomm (Qualcomm)" There is a family of chips. The MSM chips are generally used in CDMA / AMPS digital cellular terminals. The embodiments of the present invention described below are used when the baseband analog chipset is applied to the MSM chips. This is an explanation of the operation.

In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more comprehensive understanding of the present invention, and the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Meanwhile, prior to the detailed description of the present invention, a schematic configuration and operation of the baseband analog chipset, which is a test application target in the implementation of the present invention, and a core configuration of a cellular terminal in which the baseband analog chipset is applied are attached. A description with reference to FIG. 1 is as follows. The following description of the configuration of the cellular terminal is intended to clarify the scope of the present invention, which is in accordance with the present invention is a test apparatus and method necessary for manufacturing and testing the digital cellular terminal.

First, the digital cellular terminal is largely composed of the RF unit 100, the BBA 110, and the mobile terminal modem device 120 to perform the overall operation according to the respective operation performed. The RF unit 100 is a terminal Transmits a radio signal generated from or receives a radio signal from an external source. The RF unit 100 includes an internal antenna for optimizing transmission and reception of radio waves through the air and a duplex for separating transmission and reception signals. The mobile terminal modem device 120 is an essential device in a CDMA / AMPS type digital cellular terminal. The most common core configuration is a central processing unit implemented with a '186 microprocessor and a CDMA type phone call. A digital baseband processing unit, a DFM processing unit for processing digital FM signals, and a vocoder for outputting a predetermined conversion process of an applied audio signal. In addition, an RF interface for performing transmit power level control and a receive gain control operation, a clock generator for generating a reference clock in chip operation, a general-purpose ADC for performing a general analog digital converting operation, the central processing unit and a keypad The apparatus further includes a general-purpose interface (GPI) for interfacing between predetermined external devices. In this case, the central processing unit controls the overall operation of the terminal and the MSM chip, processes data read or written from an external memory, or performs a control operation of an external device through the general-purpose interface, and the CDMA digital baseband processor Has a digital signal processing function by CDMA (IS-95), and processes CDMA data transmitted and received such as electric field strength calculation and transmission / reception AGC circuit operation, CDMA transmission and reception spectrum inversion. The DFM processor performs interfacing with the CDMA BBA interface and separates the transmission path and the reception path to process the digital FM signal. The vocoder transmits and receives a voice signal with the DFM processor and performs a predetermined conversion process to perform an input / output operation. The vocoder is connected to a codec to perform an operation of outputting a voice signal through an amplifier and a speaker and receiving a voice signal input through a microphone and performing a predetermined process. The CPU additionally performed a conventional baseband analog chipset performance test operation, which was performed according to a pre-built test program as mentioned above.

A baseband analog chipset (BBA) 110, which is a device to be subjected to a performance test performed according to an embodiment of the present invention, is provided between the mobile terminal modem device 120 and the RF unit 100. Connected so that RF signal processing and digital signal processing are performed by matching the two devices. The reception system operation of the BBA 110 converts a signal received through the RF unit 100 into an intermediate frequency signal, and converts it again through a local oscillation frequency signal and a down converter to perform a baseband signal. Convert to The converted baseband signal is filtered according to each of the CDMA / FM schemes, which are then converted to digital signals by A / D conversion and outputted to the mobile terminal modem device 120. The operation of the transmission system converts the digital signal received from the mobile terminal modem device 120 into an analog signal of the baseband through the built-in A / D converter, and converts the converted signal through each corresponding filter of the CDMA / FM method. Local oscillation frequency and up-converter (Up Converter) converts to intermediate frequency (IF). The converted signal is converted into a radio signal and output to the RF unit 100 and transmitted to the air through an antenna.

The operation of the transceiver is shown in the attached Figure 3, the baseband analog A / D converter, LPF (FM / CDMA), divider, voltage controlled oscillator (VCO) provided in the chipset. This is done through the operation of a PLL, a blender, etc. On the other hand, the description of the operation of each of the internal configuration of the BBA (110) is already known and will be omitted below. Internal components of the BEA 110 shown in FIG. 3 are also omitted in the description herein.

In addition, the performance test of the BBA to be carried out in the present invention refers to the operation of testing the performance of the transmission system and the reception system, which is the strength and frequency of the signal appearing at the input and output terminals of the transmission system and the reception system, and other This is done through the output state of the necessary information. More specifically, it is a performance test of LPF, ADC, and DAC in BBA. That is, it is a test of the side band attenuation, ripple state, and signal attenuation state of LPF, and it is to measure the time delay state, quantization error state, and frequency generation accuracy of each mode of ADC and DAC. will be.

2 is a diagram illustrating a test state when a BBA is tested through a test apparatus according to the present invention.

Referring to FIG. 2, an FPGA test apparatus 130 according to an embodiment of the present invention is connected to a BBA 110 that is a test target, and the FPGA test apparatus 130 is connected to an external computer 170. The signal generator inputs a signal necessary for performing a transmission system test to the BBA, and the spectrum analyzer 150 receives an intermediate frequency signal signal state output through the BBA 110, that is, the magnitude of the signal, and the I and Q signals. Measure the time delay and ripple state. The logic analyzer 160 receives the parallel signal output from the FPGA test apparatus 130 as an input and analyzes the state of the received data to analyze whether the BBA 110 is operating normally.

3 is an internal block diagram of the FPGA test apparatus 130 according to an exemplary embodiment of the present invention, which is a block diagram of a state connected to the BBA 110 during the performance test of the BBA 110. In addition, FIG. 2 shows a schematic internal block configuration of the BBA 110.

Referring to FIG. 2, the buffer 132 receives digital data output from the CDMA ADC of the BBA 110, temporarily stores the digital data, and outputs the digital data to the logic analyzer 160. When the CDMA ADC converts the analog signal of the CDMA I-channel and the analog signal of the CDMA Q-channel into 4 bits of parallel data, the buffer 132 receives the input and outputs 8 bits of parallel data. I and Q signals, which are converted into 8-bit serial data from the FM ADCs of the BBA 110 and output, are output through a corresponding selection operation, and the output serial data is converted into a first SP (Serial-Parallel) converter ( 134) is converted into parallel data. As an example, the serial data output from the FM ADC is composed of 8 bits, which are converted into parallel data of 8 bits through the first S-P converter 134. The Tx clock and frequency generator 136 generates a digital signal necessary for the performance test and outputs it to the IDAC and QDAC of the BBA 110. The Tx clock and the frequency generator 136 are driven under the control of the PC 170, and the PC 170 performs a corresponding operation by a program embedded in the EEPROM 144. In a specific embodiment of the present invention, the Tx clock and frequency generator 136 generates a CDMA clock and 8-bit CDMA I, Q channel parallel data. The generated parallel data is converted into an analog signal in the DAC and output to the corresponding block. The Tx clock and the frequency generator 136 simultaneously generate and output an FM clock and 8-bit FM Q channel parallel data. At this time, it is transmitted to the FM LPF through the I, Q DAC and output to the corresponding block. Accordingly, the Tx clock and frequency generator 136 generates clocks of CDMA and FM, respectively, and simultaneously drives them under the control of the PC 170. The mode controller 138 outputs the control signal to the mode controller provided in the BBA 110. The mode controller 138 outputs a control signal according to the FM and CDMA mode selection (which is performed in the dual mode function) and the idle mode and sleep mode selection operations. The second S-P converter 142 converts 8-bit serial data output from the GP ADC of the BBA into parallel data and outputs the parallel data to the logic analyzer 160 to perform a corresponding analysis process. In general, the GP ADC reads temperature, battery type, and battery voltage, converts them into digital data, and transmits them to the mobile terminal modem chip.

4 is an implementation process of the test apparatus through the FPGA according to the present invention, with reference to the configuration shown in Figs. 2 and 3 will be described below.

First, in step 210, programming for interfacing with the BBA 110 is performed on the FPGA. In operation 220, the EEPROM 144 stores corresponding data necessary for the programming operation. In operation 230, the amplification degree, the number of signals, and the frequency control operation are performed through the parallel port.

5 is a flowchart illustrating a process of testing a transmission system performance of a baseband analog chipset in a test apparatus (shown in FIG. 3) according to the present invention.

Referring to FIG. 5, in step 310, the operation of the mode controller 138 is controlled to perform an FM mode or a CDMA mode selection operation. When the mode selection operation is performed in step 310, the corresponding mode selected in step 312 is set, and in step 314, the corresponding program is called by the PC 170 for processing. In step 316, the data stored in the EEPROM 144 is read. The operations of steps 314 and 316 are performed by generating frequencies of 1-tone, 2-tone, and 3-tone signals that meet the specifications. In accordance with the tone signal generating operation, the Tx clock is performed in step 318. The frequency generator 136 is driven, and in step 320, the Tx clock and the frequency generated by the driving of the Tx clock and the frequency generator 136 are input to the transmission system of the BBA 110. The operation of the spectrum analyzer 150 is performed in step 322, and the performance test result of the BBA 110 is read in operation 324 through the operation of the spectrum analyzer 150. Through this result, the user can know the performance state of the BBA (110). On the other hand, the spectrum analyzer 150 is connected to the TxIF, TxIF / stage, which is the transmitting end of the BBA (110), the output of the TxIF, TxIF / stage can be seen whether the performance of the transmission system.

6 is a flowchart illustrating a process of testing a reception system performance of a baseband analog chipset in a test apparatus according to the present invention.

Referring to FIG. 6, in operation 410, it is determined whether a user selects a mode in the FM mode or the CDMA mode. The operation of step 410 is also performed by the operation of the mode control unit 138. When the FM mode is selected in step 410, the setting of the FM mode is made in step 411. In operation 413, the channel selection operation is performed through the I / Q switch. In operation 415, the operation of the signal generator 140 is started. In step 415, the signal generator 140 generates 1-tone, 2-tone, and 3-tone signals, and the generated tone signal is applied to RxIF and RxIF / terminals of the BBA 110. The signal receiver undergoes a corresponding signal processing through the FM receiver of 110. In step 417, the serial data output through the FM receiver of the BBA 110 is converted into parallel data through the S / P converter 134, and the converted data is analyzed in step 419. Is applied to 160. In operation 421, a performance test operation of the BBA 110 receiving system through the logic analyzer 160 is performed and other test results are read.

On the other hand, if the selection is made to the CDMA mode in step 410, and the setting to the CDMA mode in step 412 is made by the operation of the mode control unit 138. In step 414, the operation of the signal generator 140 is performed. In this case, 1-tone, 2-tone, and 3-tone signals are generated and applied to the CDMA receiving system of the BBA 110 to perform the corresponding signal processing operation. In step 416, the data of the BBA 110, which is output according to the operation of the signal generator 140, is output through the buffer 132. Since the data output from the CDMA receiver is composed of parallel data, it is not necessary to perform a separate data conversion operation, which is only transmitted to the logic analyzer 160 by the operation of a buffer. In operation 418, the operation of the logic analyzer 160 is performed. In operation 420, the performance test result is read.

In conclusion, the operation of the present invention is summarized as follows. In testing whether the operation of the transmission system and the reception system of the BBA 110 is normally performed, that is, whether the operation corresponding to the specified specification is performed, the FPGA By implementing the corresponding test device through the connection to the BBA (110), to select the transceiver required for the test to perform the test operation accordingly. In operation of the dual mode (FM / CDMA) type BBA, when the FM / CDMA transmission system is tested, the corresponding tone signal generated through the Tx and the frequency generator 136 implemented through the FPGA is used. When applied to the transmission system of the BBA 110 and the result is output, it is received through the spectrum analyzer 150 to test the state of the BBA 110 transmission system. In the case of testing an FM / CDMA receiver, after applying a corresponding signal from an external signal generator, converting the output into parallel data in a form that data can be analyzed by a logic analyzer, and then converting the converted data into the logic analyzer. Through the 160, the performance of the receiver is tested. In the case of the FM receiver, since the output data is serial data, a separate operation for converting the data into parallel data is performed. In the case of the CDMA receiver, the output data is already parallel data. Is done.

As described above, the present invention performs the performance test of the baseband analog chipset for converting the intermediate frequency signal, the baseband analog signal and the digital signal from the digital cellular terminal, and applies the programmable FPGA to the digital cellular terminal. By performing the BBA performance test, there is an advantage that you can test the performance of the BBA without necessarily implementing a terminal product.

Claims (5)

In the performance test apparatus of the baseband analog chipset, A signal generator for outputting a tone signal having a predetermined specification to a reception system of the baseband analog chipset; A spectrum analyzer which receives a predetermined signal output from a transmission system of the baseband analog chipset and analyzes a state of the predetermined signal; A predetermined program for interfacing with the baseband analog chipset is implemented by F.GA. (FPGA), and generates a predetermined frequency signal corresponding to the transmission system of the baseband analog chipset according to the implemented program and data. And a test device for converting the signal output from the reception system of the baseband analog chipset into parallel data and outputting the parallel data; And a logic analyzer configured to receive the parallel data output from the test apparatus, analyze a state of the data, and output a corresponding result. The method of claim 1, wherein the test device, A buffer for temporarily storing parallel data output through the CDMA receiver of the baseband analog chipset and outputting the data as it is, and serial data output through a frequency modulation (FM) receiver as parallel data. A serial-to-parallel (SP) converter for converting and outputting the same; A computer operating according to the predetermined program for interfacing with the baseband analog chipset; A nonvolatile memory for storing corresponding data to be read and processed under the control of the computer; A transmission clock and frequency generator for generating and outputting a transmission clock and a frequency according to the read data; And a mode control unit for performing an operation of selecting a frequency modulation (FM) mode or a code division multiple access (CDMA) mode. In the method for implementing the performance test apparatus of the baseband analog chipset, A first process of implementing the amplification degree, the number of signals, the frequency control operation of the signal through the parallel port, and the programming to perform the interface with the baseband analog chipset with F.GA., And a second process of storing data and generated data necessary for the operation according to the programming of the first process in the provided nonvolatile memory. In the transmission system performance test method of the baseband analog chipset, The interface programming of the baseband analog chipset is implemented by F.P.G. (FPGA), and the necessary data corresponding to the implemented program is stored in the nonvolatile memory, A first process of generating a corresponding frequency signal according to the driving of the program and data; A second process of outputting the generated frequency signal to a transmission system of the baseband analog chipset; And a third process of measuring a result output from the baseband analog chipset according to the second process to test the performance of the transmission system. A method of performing a receiver performance test of a baseband analog chipset connected to a receiver by a logic analyzer, A first process of driving the signal generator to generate a corresponding signal and then outputting the generated signal to a reception system of the baseband analog chipset; A second process of converting the converted serial data into parallel data when the signal output in the first process is converted into serial data through a reception system of the baseband analog chipset; A third process of applying the parallel data converted in the second process to the logic analyzer to perform an analysis operation of the logic analyzer through the parallel data; And a fourth process of reading a corresponding performance test result through the logic analyzer.