KR100320458B1 - Apparatus for displaying osd of analog/digital tv receiver - Google Patents

Abstract

The present invention relates to an OSD display of an analog / digital TV receiver capable of providing a digital graphic-level OSD regardless of analog / digital, and converting the received analog broadcast signal into a video signal that can be displayed on a screen. An analog signal processor, a memory for storing image data for configuring a menu screen according to a user request, an amplifier decoder for decoding a digital broadcast signal and outputting the image data stored in the memory in an OSD form according to a predetermined control signal; A synchronization interface for generating a vertical / horizontal synchronization signal for synchronizing the OSD output of the amplifier to an analog screen, and synchronizing the vertical / horizontal synchronization signal output from the synchronization interface or the OSD output of the amplifier decoder to a digital screen Self-generated vertical / horizontal sync signal A digital signal processor including an RGB encoder for converting the OSD output from the amplifier to an analog color signal, and controlling the analog signal processor and the digital signal processor to correspond to a user's operation command, and analog and digital according to the user's request. A control unit for generating and outputting image data for constituting a broadcast menu screen, a switching unit for selecting one of outputs of an analog signal processing unit and a digital signal processing unit according to a control signal of the control unit, and deflecting the output of the switching unit It is configured to include an image processing unit to display on the screen to meet the user's visual needs to improve the reliability of the product, and by combining two existing control units into one can simplify the overall circuit configuration and reduce the manufacturing cost.

Description

OSD display of analog / digital TV receivers {APPARATUS FOR DISPLAYING OSD OF ANALOG / DIGITAL TV RECEIVER}

TECHNICAL FIELD The present invention relates to an analog / digital TV receiver, and more particularly, to an On Screen Display (OSD) display of an analog / digital TV receiver.

The existing analog TVs are being introduced to consumers in various forms ranging from small models such as 14 inches to projection TVs over 60 inches.

However, current analog TVs are showing various problems as they become larger and more functionalized. First, in terms of video quality, the quality of video when watching the current analog broadcasting quality such as NTSC, PAL or SECAM on a large TV can be deteriorated. Can be.

Second, in view of the limit of broadcasting channels that can be serviced in the future, the number of currently allocated TV broadcasts is limited to about 80 in total in both microwave and microwave channel bands. It is only about.

Third, the limitation as a unidirectional medium is mentioned.

That is, TV until now has only a function as a reception medium, but as the demand for interactive functions explodes due to the appearance of personal computers and the Internet, future TVs are required to function as interactive terminals.

Finally, the saturation of the analog TV market.

In other words, Korea currently has more than 2 units of supply per household, so we cannot expect any more demand.

As a result, digital TVs have emerged as a way to solve the problems of analog TVs. Digital TVs have dramatically improved the video quality of analog TVs, providing more than twice as sharp image quality as analog TVs, and the interference between adjacent channels Since there is no channel area, it is possible to use all channel areas that were not used previously.

In addition, according to the Program Service Information Protocol (PSIP), a broadcasting supplementary information standard that provides detailed information about broadcast programs in the US Digital TV Standard Advanced Television Service Committe (ATSC) proposed in November 1997, One high-resolution (HD) digital broadcast program or four standard-definition (SD) digital broadcast programs can be transmitted per channel, that is, a 6 MHz band, which can provide hundreds of diverse services. By providing services such as Internet service, home shopping, and home banking, it is highly likely that analog channels will be replaced by digital channels in the near future, and explosive demand window is expected in the future.

However, in order to change the current analog method to digital method, both the broadcasting equipment and the TV receiver have to be changed, which requires a lot of time, so there is a high possibility that the analog broadcast and the digital broadcast will coexist for a certain period of time.

Therefore, until the digital broadcasting system is completely established, the analog / digital TV that can simultaneously receive analog and digital is expected to become mainstream.

As described above, the digital method has advantages over the analog method, and it can be seen that there is a marked difference in graphic representation.

However, in the current analog / digital TV receiver, the graphic representation technology of the digital receiver cannot be used in the analog receiver. Therefore, it is necessary to develop a technology related to this because it will take a long time before the complete digital broadcasting is performed.

Hereinafter, the OSD display technology of the analog / digital TV according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an analog / digital TV receiver according to the prior art, FIG. 2 is a block diagram showing the detailed configuration of the digital signal processor of FIG. 1, and FIG. 3 is a timing diagram showing the output waveform of each part of FIG. It is also.

As shown in FIG. 1, the analog / digital TV according to the prior art converts a digital broadcast signal tuned through an antenna into a digital RGB signal through a series of processes such as decoding and encoding, and outputs the converted digital RGB signal to the input graphic data. Digital signal processing unit 3 for generating a corresponding OSD, digital microcomputer for controlling the digital signal processing unit 3 to correspond to a user's operation command and outputting graphic data for displaying the user's operation command processing result and menu, etc. (4) The user inputs through the analog signal processor 1 and the key input unit 7 which converts and outputs the analog broadcast signal tuned through the antenna into a video signal, that is, an RGB signal, through a series of processes such as demodulation. An OSD for controlling the analog signal processor 1 to correspond to an operation command and displaying a user's operation command processing result and menu, etc. The digital signal processor (3) or the analog signal processor (1) is generated according to the control signal of the analog microcomputer (2) and the analog microcomputer (2), which generates and transmits a digital broadcast-related command to the digital microcomputer (4). And a video processor 6 which performs a series of signal processing such as a deflection process so that the output of the switch 5 can be displayed on the screen.

In this case, as shown in FIG. 2, the digital signal processor 3 decodes the digital broadcast signal received through the antenna according to the control signals of the DRAM 12 and the digital microcomputer 4, and transmits the digital broadcast signal from the digital microcomputer 4. An amplifier decoder 11 and a pixel clock PIXCLK that store graphic data in the DRAM 12 and output the graphic data in OSD form according to the vertical / horizontal synchronization signal V_Sync / H_Sync are divided into the vertical / horizontal synchronization signal And an RGB encoder 13 for generating V_Sync / H_Sync and converting the digital output of the amplifier decoder 11 into an analog form and outputting it as an image signal displayable on the screen.

In this case, if the horizontal synchronization signal and the image data are not synchronized with the pixel clock, the screen may be slightly shaken. Therefore, synchronization should be performed. As described above, the pixel clock PIXCLK is divided into the vertical / horizontal synchronization signal V_Sync /. H_Sync) is generated, as shown in FIG. 3.

Referring to the OSD display operation of the prior art configured as described above is as follows.

Conventionally, each OSD is generated separately from the analog / digital, that is, the analog microcomputer 2 and the digital signal processing unit 3 and displayed by the image processing unit 6.

First, in the analog broadcast mode, the analog microcomputer 2 generates an OSD corresponding to a user's operation command input through the key input unit 7 and supplies the vertical pulse V_Pulse and the horizontal pulse supplied from the image processor 6. The image is output to the image processor 6 according to (H_Pulse).

Subsequently, the image processor 6 processes the input OSD and displays the image on the screen.

On the other hand, in the digital broadcast mode, the digital microcomputer 4 receives the user's operation command input through the key input unit 7 from the analog microcomputer 2 to generate graphic data corresponding to the operation command to the amplifier amplifier ( 11) to transmit.

Subsequently, the amplifier decoder 11 converts the graphic data into an OSD form according to the vertical / horizontal synchronization signal V_Sync / H_Sync and the OSD activation signal FB_OSD provided from the RGB encoder 13 and transmits the same to the RGB encoder 13. do.

In addition, the RGB encoder 13 converts the OSD signal into an analog form so as to be displayed on the screen according to the vertical / horizontal synchronization signal V_Sync / H_Sync.

Therefore, the viewer may feel that the OSD type and level displayed through the same display means are different according to the analog broadcast mode and the digital broadcast mode, and in particular, the OSD of the analog broadcast mode is significantly lower than the digital OSD.

The analog / digital TV receiver according to the prior art displays a different type of OSD through a process of each of the analog method and the digital method, and thus has the following problems.

First, separate micom and signal processing circuits are required to display each OSD, which complicates circuit configuration and design.

Second, a big difference occurs in the graphic level of the analog OSD and the digital OSD displayed on the same screen, causing a visual dissatisfaction of the viewer.

Accordingly, the present invention has been made to solve the above-mentioned problems, and to provide an OSD display device of an analog / digital TV receiver capable of providing a digital graphic level OSD regardless of analog / digital with a simplified configuration. The purpose is.

1 is a block diagram showing the configuration of an analog / digital TV receiver according to the prior art

FIG. 2 is a block diagram illustrating a detailed configuration of the digital signal processor of FIG. 1.

3 is a timing diagram illustrating output waveforms of each part of FIG. 2;

Figure 4 is a block diagram showing the configuration of the OSD display of the analog / digital TV receiver according to the present invention

5 is a block diagram illustrating a configuration of a digital signal processor of FIG. 4.

6 is a circuit diagram illustrating a configuration of a synchronous interface unit of FIG. 5.

7A, 7B, and 8 are timing diagrams illustrating output waveforms of each part of FIG. 6.

Explanation of symbols for main parts of drawings

21: analog signal processor 22: digital signal processor

23: control unit 24: switching unit

25: image processing unit 26: key input unit

31: Ampeck decoder 32: DRAM

33: RGB encoder 34: synchronous interface unit

40: vertical sync signal generator 50: horizontal sync signal generator

60: output disconnect 41, 42, 51 to 55: D flip-flop

43, 44, 56: NAND gate 45, 46: NOR gate

61, 62: buffer

The present invention provides an analog signal processing unit for converting a received analog broadcast signal into a video signal that can be displayed on a screen, a memory for storing image data for constituting a menu screen according to a user's request, and decoding a digital broadcast signal in the memory. An amplifier decoder for outputting the stored image data in OSD form according to a predetermined control signal, a synchronization interface unit for generating vertical / horizontal synchronization signals for synchronizing the OSD output of the amplifier decoder with an analog screen, and outputting from the synchronization interface unit Digital signal processing unit including an RGB encoder for converting the OSD output from the amplifier to an analog color signal according to the vertical / horizontal synchronizing signal or the vertical / horizontal synchronizing signal generated by itself to synchronize the OSD output of the amplifier decoder to the digital screen And, according to the operation command of the user A controller for controlling the analog signal processor and the digital signal processor and generating and outputting image data for constituting the menu screen for analog and digital broadcasting according to the user's request, and the analog signal processor and the digital signal processor according to the control signal of the controller. And a switching unit for selecting one of the outputs, and an image processing unit for deflecting the output of the switching unit and displaying the same on the screen.

In addition, the synchronization interface of the present invention is a vertical synchronization signal generator for generating a vertical synchronization signal in which the odd and even fields are divided and synchronized with the pixel clock by using the horizontal pulse and the vertical pulse output during the deflection processing of the image processor; A horizontal synchronizing signal generator for delaying the horizontal pulse output during the deflection processing of the processing unit to generate a horizontal synchronizing signal synchronized with the pixel clock, and an output blocking unit for interrupting the output of the vertical and horizontal synchronizing signals according to a control signal of the controller; Characterized in that configured.

Hereinafter, a preferred embodiment of an OSD display of an analog / digital TV receiver according to the present invention will be described with reference to the accompanying drawings.

Prior to the detailed description, the overview of the present invention will be described first, and the present invention is an apparatus for implementing a high-level OSD applied in a digital method regardless of analog / digital broadcasting, as can be seen in the configuration of the present invention described below. Since the main point is a technology for integrating a conventional analog microcomputer and a digital microcomputer and synchronizing a digital OSD to an analog screen, the description will be focused on this.

Figure 4 is a block diagram showing the configuration of the OSD display device of the analog / digital TV receiver according to the present invention, Figure 5 is a block diagram showing the configuration of the digital signal processor of Figure 4, Figure 6 is a configuration of the synchronization interface of Figure 5 7A, 7B, and 8 are timing diagrams illustrating output waveforms of each part of FIG. 6.

As shown in FIG. 4, the OSD display device of the analog / digital TV receiver according to the present invention includes an analog signal processor 21 for converting a received analog broadcast signal into a video signal that can be displayed on a screen and a digital broadcast signal. A digital signal processor 22 for converting an analog image signal displayable on the image into a digital broadcasting OSD synchronized with the OSD-forming graphic data, and the analog signal processor 21 to correspond to a user's operation command. And a control unit 23 for controlling the digital signal processing unit 22 and outputting graphic data for displaying a processing result of the user operation command, a menu, etc. in an OSD form, and an analog signal processing unit according to a control signal of the control unit 23. Switching unit 24 for selecting one of the output of the 21 and the digital signal processing unit 22, the switching unit 24 And an image processor 25 for deflecting the output of the output on the screen.

At this time, the control unit 23 is configured by adding a program of an analog micom to the digital micom of the prior art, and additionally assigning a port capable of accepting a signal from the key input unit 26 and a control signal port.

Next, a detailed configuration of the digital signal processing unit 22 will be described. As shown in FIG. 5, the DRAM 32 and the digital broadcast signal are decoded and the graphic data output from the control unit 23 is stored in the DRAM 32. The amplifier decoder 31 outputs in OSD form according to the control signal of the controller 23, the vertical / horizontal pulses V_Pulse / H_Pulse and pixels output from the image processor 25 according to the control signal of the controller 23. In the synchronization interface unit 34, which generates a vertical / horizontal synchronization signal V_OSD / H_OSD for synchronizing the OSD output of the amplifier decoder 31 to the analog screen using the clock PIXCLK. RGB for converting the OSD output from the amplifier decoder 31 into an analog color signal according to the output vertical / horizontal synchronization signal or the vertical / horizontal synchronization signal generated by itself to synchronize the OSD output of the amplifier decoder 31 to a digital screen. Encoder 33).

In this case, as shown in FIG. 6, the synchronous interface unit 34 separates odd / even fields by using the vertical / horizontal pulses V_Pulse / H_Pulse output from the image processor 25, and the pixel clock PIXCLK and the pixel clock. The vertical synchronizing signal generator 40 generating the synchronized vertical synchronizing signal V_OSD and the horizontal synchronizing signal H_OSD synchronized with the pixel clock PIXCLK by delaying the horizontal pulse H_Pulse output from the image processing unit 25. ), A horizontal synchronizing signal generating unit 50 for generating a) and an output interrupting unit 60 for interrupting the output of the vertical / horizontal synchronizing signal (V_OSD / H_OSD) according to the control signal of the control unit 23.

In this case, the vertical synchronization signal generator 40 may delay the vertical pulse V_Pulse output from the image processor 25 according to the pixel clock PIXCLK. The second D flip-flop 42 delays the output of the pixel clock PIXCLK according to the pixel clock PIXCLK, and the output of the first D flip-flop 41 and the horizontal pulse H_Pulse and the inverted second D flip-flop 42 A second NAND gate 43 that negatively ANDs the output, an inverted horizontal pulse H_Pulse and an inverted second D flip-flop 42, and a second negative AND that outputs the first D flip-flop 41. RS flip-flop which consists of NAND gate 44, first NOR gate 45 and second NOR gate 46 to maintain the outputs of the first NAND gate 43 and the second NAND gate 44 to the next field. It is composed.

The horizontal synchronizing signal generator 50 receives the output of the front end sequentially by using the horizontal pulse H_Pulse output from the image processor 25 as the first stage and delays the output according to the pixel clock Pixclk. And a seventh D flip-flop 51 to 55, and a third NAND gate 56 that negatively ANDs the output of the third D flip-flop 51 and the inverted output of the seventh D flip-flop 55. .

In addition, the output blocking unit 60 blocks the output of the first NOR gate 45 according to the control signal EN_OSD of the inverted control unit 23 and the third NAND gate 56. And a second buffer 62 for blocking the output of the signal according to the control signal.

The OSD display operation of the analog / digital TV receiver according to the present invention configured as described above will be described in detail by dividing the digital and analog broadcasting modes.

_ Digital Broadcasting Mode _

When the user presses a predetermined key (for example, a user menu key) through the key input unit 26 while the digital channel is tuned and the corresponding broadcast program is displayed, the controller 23 controls the operation command of the user, that is, the menu screen. Recognizing the request command, the graphic data for menu screen composition is generated and output to the digital signal processor 22.

Subsequently, the amplifier decoder 31 of the digital signal processor 22 converts the graphic data output from the controller 23 into an OSD form and stores the graphic data in the DRAM 32 and then generates the vertical / horizontal generated by the RGB encoder 33. Output to the RGB encoder 33 in accordance with the synchronization signal (V_Sync / H_Sync).

At this time, since the control unit 23 is the digital broadcasting mode, the control signal EN_OSD signal is set to 'high' to block the vertical / horizontal synchronization signal V_OSD / H_OSD output of the synchronization interface unit 34.

At the same time, the image processor 25 outputs a signal [FB (Fast Blankin) _OSD] for enabling the OSD output.

The RGB encoder 33 converts the menu screen OSD into an analog color signal according to the generated vertical / horizontal synchronization signal V_Sync / H_Sync.

The output of the RGB encoder 33 is then deflected by the image processing unit 25 via the switching unit 24 and displayed on the screen.

_ Analog broadcast mode _

When the user presses a predetermined key (for example, a user menu key) through the key input unit 26 while the current analog channel is tuned and the corresponding broadcast program is displayed, the controller 23 controls an operation command of the user, that is, a menu screen. Recognizing the request command, the graphic data for menu screen composition is generated and output to the digital signal processor 22.

Subsequently, the amplifier decoder 31 of the digital signal processor 22 converts the graphic data output from the controller 23 into an OSD form and stores the graphic data in the DRAM 32 and then supplies the vertical / Output to the RGB encoder 33 in accordance with the horizontal synchronization signal (V_OSD / H_OSD).

At the same time, the image processor 25 outputs an OSD activation signal FB_OSD.

In this case, the operation of generating the vertical / horizontal synchronization signal V_OSD / H_OSD of the synchronization interface unit 34 will be described in detail as follows.

First, the vertical synchronizing signal V_OSD is synchronized with the pixel clock PIXCLK, and the odd and even fields must be distinguished. Therefore, by synchronizing with the pixel clock PIXCLK by inputting a vertical pulse H_Pulse to the first and second D flip-flops 41 and 42 using the pixel clock PIXCLK as a clock pulse, the pixel clock PIXCLK is synchronized with FIGS. 7A and 7B. As described above, the odd / even field is determined by the first and second NAND gates 43 and 44 using a characteristic in which the horizontal pulse H_Pulse and the vertical pulse V_Pulse are synchronized in the odd field and not in the even field. To generate the vertical synchronization signal V_OSD.

That is, if the output 'O6' of the first NAND gate 43 is 'high', an odd field is used, and if the output 'O7' of the second NAND gate 44 is 'high', an even field is indicated. Subsequently, the vertical sync signal V_OSD in which the odd / even fields are determined using the RS flip-flop is maintained until the next field and output through the first buffer 61.

In this case, as described above, in the digital broadcast mode, since the output of the synchronization interface unit 34 should be cut off, the controller 23 cuts the output by setting the 'EN_OSD' signal to the 'high' level.

Meanwhile, as shown in FIG. 8, the horizontal synchronization signal H_OSD is delayed by one clock through the third to seventh D flip-flops 51 to 55, so that the horizontal pulse H_OSD is delayed by one clock signal to the pixel clock PIXCLK. After synchronization, the logic operation 'O1 × O5 ^* ' of the output 'O1' of the third D flip-flop 51 and the output '05' of the seventh D flip-flop 55 through the third NAND gate 56 is performed. Is generated and output through the second buffer 62.

The RGB encoder 33 converts the menu screen OSD into an analog color signal according to the vertical / horizontal synchronization signal V_OSD / H_OSD supplied from the synchronization interface unit 34 and outputs the analog color signal.

The output of the RGB encoder 33 is then deflected by the image processing unit 25 via the switching unit 24 and displayed on the screen.

The OSD display of the analog / digital TV receiver according to the present invention has the following effects.

First, it provides digital level high quality OSD regardless of digital and analog broadcasting, which can improve the reliability of the product by satisfying user's visual needs.

Second, since the two existing control unit is integrated into one, the circuit configuration is simplified, so that the overall circuit configuration can be simplified and the manufacturing cost can be reduced.

Claims (3)

In analog / digital TV receivers, An analog signal processor for converting the received analog broadcast signal into a video signal displayable on the screen; A memory for storing image data for constituting a menu screen according to a user request, an amplifier decoder for decoding a digital broadcast signal and outputting the image data stored in the memory in an OSD form according to a predetermined control signal, and an OSD of the amplifier module A synchronization interface for generating a vertical / horizontal synchronization signal for synchronizing the output to an analog screen, and a self-generated signal for synchronizing the vertical / horizontal synchronization signal output from the synchronization interface or the OSD output of the amplifier decoder to a digital screen. A digital signal processor including an RGB encoder for converting an OSD output from the amplifier decoder into an analog color signal according to a vertical / horizontal synchronization signal; A control unit for controlling the analog signal processor and the digital signal processor to correspond to a user's operation command and generating and outputting image data for configuring a menu screen for analog and digital broadcasting according to the user request; A switching unit which selects one of an output of an analog signal processor and a digital signal processor according to a control signal of the controller; And an image processing unit for deflecting the output of the switching unit to display on the screen. The method of claim 1, And the sync interface unit is blocked by the control unit when a vertical / horizontal sync signal is output from the RGB encoder. The method of claim 1, The sync interface unit includes a vertical sync signal generator for generating a vertical sync signal in which odd / even fields are divided and synchronized with a pixel clock by using horizontal and vertical pulses output in a deflection process of the image processor; A horizontal synchronous signal generator for delaying the horizontal pulse output in the deflection process of the image processor to generate a horizontal synchronous signal synchronized with the pixel clock; And an output blocker configured to block the vertical and horizontal sync signal outputs according to the control signal of the controller.