KR100315350B1 - Apparatus for carrier recovery by using frequency sweeping - Google Patents

Abstract

Disclosed is a carrier recovery apparatus using frequency sweeping. The carrier restorer detects when a lock is swept over a range of frequencies in the derotator and sweeps near the frequency offset, causing the derotator to stop frequency sweeping. After locking, the phase is held by a normal phase-lock loop. In addition, the feedback of the frequency offset change according to the long-term system operation from the frequency restorer is corrected when the frequency sweep of the derotator. When frequency sweeping is performed on the derotator, the fall lock does not occur due to an error due to the frequency domain mismatch in the SRC filter.

Description

Carrier recovery device using frequency sweeping {APPARATUS FOR CARRIER RECOVERY BY USING FREQUENCY SWEEPING}

TECHNICAL FIELD The present invention relates to a digital communication system, and more particularly, to a carrier recovery apparatus using frequency sweeping in a device on a receiving side of a digital communication and requiring no false lock detection.

In general, since a signal transmitted through a channel in a digital communication system includes various noises or distortions caused by multiple paths, a phase error and a timing error occur in a signal transmitted by modulating a phase or a frequency. This causes the interference of the carrier and the reduction of the power level, so that the receiving side needs to recover the carrier to obtain information from the modulated signal.

In general, when broadcasting using satellites, since a large transmission power is not taken, an efficient modulation method must be adopted. Accordingly, quadrature phase shift keying (QPSK), which is an efficient digital modulation method, has been adopted. Since the QPSK method has a constant amplitude and only needs to transmit phase information, the QPSK method has maximum amplitude modulation and is efficient. Another widely used signal modulation method of digital data communication is the 16QAM modulation method.

The operation principle of the QPSK method is shift keying of four phases. The data is divided into I-axis and Q-axis (1 bit each), and the transmission carriers that are orthogonal to the data, i.e., shifted by 90 ° phase, are modulated. will be. Therefore, in the satellite broadcasting receiver that receives the QPSK modulated high-speed transmission signal, a lock detection circuit for detecting whether the carrier is synchronized during QPSK demodulation is required.

1 is a block diagram showing the configuration of a conventional carrier recovery apparatus using frequency sweeping, and FIG. 2 is a detailed configuration of the frequency sweeper / carrier recovery 16 shown in FIG. It is a block diagram.

Conventional carrier recovery apparatus is a square root up filter, which is a filter that is matched with an analog-to-digital converter (hereinafter referred to as 'ADC') 10 for converting an analog baseband input signal into a digital signal, and a shaping filter (not shown) of a transmitting end. (b) a square equalizer (14) for compensating for channel distortions such as multipath with only normal data without using training data streams (12). Frequency sweeper / carrier restorer (16) performs carrier frequency recovery and phase recovery with frequency sweeping and phase locked loop (PLL), corrects 90, 180, and 270 degree out of phase conditions The output phase controller 18 includes an error correction decoder 20 for correcting an error due to noise on the channel as a channel decoding portion, and a phase detector 22 for generating a phase error.

2 shows a detailed configuration of the frequency sweeper / carrier restorer 16. The frequency sweeper / carrier restorer (16) separates only the outer four symbols from the complex multiplier (16a) and 16QAM modulation scheme for complex multiplication of the output of the blind equalizer 14 and the output of the numerically controlled oscillator 16e. Output signal separator 16b, phase detector 16c for generating phase error of the output signal of complex multiplier 16a, loop filter 16d for removing high frequency components from the phase error components and passing only low frequency components, voltage Numerically controlled oscillator (NCO) 16e, which digitally implements a control oscillator (VCO) and generates sin and cos values with frequencies according to the output values of the loop filter 16d, and carrier frequency recovery mode. Lock detector (16f) to detect whether the lock is locked in the frequency, frequency sweep phase generator (16g) to generate a phase value for frequency sweeping, and the data value closest to the constellation It includes a slicer 16h that makes the value corresponding to the original signal point.

As described above, in the conventional carrier restoring apparatus, the carrier sweeper is included in the carrier restoring block at the rear end of the equalizer 14. Sweeping a range of frequencies in the Carrier Restorer block to see if a lock is engaged and stopping the frequency sweep when the lock is engaged.

If this method is used in a system that modulates a signal according to QPSK or quadrature amplitude modulation (QAM), the phase is continuously rotated at an integer multiple of 90 degrees for each symbol due to the constellation of the modulation. That is, it appears that the lock is locked in the carrier restorer for a frequency offset of n / 4 (n = 1, 2, 3, ...) of the symbol rate, which is called a false lock. Therefore, there is a need for a circuit that can discriminate between this lock and true lock.

For the 16 QAM modulation scheme, using all 16 signal points, as well as the above mentioned lock lock as shown in Fig. 3 (a), another fall lock occurs around 30 degrees. Thus, this method has a problem in that the configuration of the circuit for determining the lock lock becomes complicated.

On the other hand, if only four signal points on the outer side are used, no other lock lock is generated as shown in Fig. 3 (b), so that the circuit configuration for determining the lock lock is simpler than the previous method. Conventionally, this method is mainly employed, and the method of operating the remaining carrier reconstructors for only the four signal points by distinguishing the outer four signal points in the signal separator 16b. However, this method is basically the same problem in that the carrier recoverer includes a frequency sweeper, and a fault lock occurs when the phase is continuously rotated by an integer multiple of 90 degrees every symbol, so a circuit for detecting the lock lock is necessary. Is holding.

The present invention can remove the lock lock without adding a separate circuit in the QPSK and 16QAM modulation schemes and monitors and compensates for the variation of the carrier frequency offset according to the long-term system operation. It is an object of the present invention to provide a carrier recovery apparatus capable of providing a reception quality.

1 is a block diagram showing the configuration of a carrier restoration system according to the prior art.

2 is a detailed block diagram showing a detailed configuration of the carrier restorer shown in FIG.

3 shows the carrier reconstruction S-curve for 16QAM.

4 is a block diagram showing the configuration of a carrier recovery system according to the present invention.

5 is a frequency characteristic diagram of an SRC filter.

6 is a detailed block diagram showing the configuration of a de-rotator according to the present invention.

7 is a detailed block diagram showing the configuration of a carrier recoverer according to the present invention.

8 is a detailed block diagram illustrating a configuration of a signal separator according to the present invention.

9 is a detailed block diagram showing the configuration of a phase detector according to the present invention.

10 is a detailed block diagram showing the configuration of a loop filter according to the present invention.

<Description of the symbols for the main parts of the drawings>

40: A / D converter 50: de-rorator

52: complex multiplier 54: numerically controlled oscillator / frequency sweeper

60: SRC filter 70: blind equalizer

80: carrier restorer 90: FEC

150: first complex multiplier 160: frequency sweeper

180: first numerically controlled oscillator 190: second complex multiplier

200: signal separator 210: phase detector

220: loop filter 230: second numerical control oscillator

240: frequency offset monitor 250: slicer

260: rock detector

In order to achieve the above object, the analog-to-digital conversion means for receiving a baseband analog complex signal as an input and sampling and converting it into digital complex data; Based on the offset variation amount (afc_phase) of the carrier frequency and the lock detection data (afc_lock_det) regarding whether the PLL lock is engaged, the frequency offset is performed in the baseband by performing frequency sweeping on the digital complex data input from the analog / digital conversion means. A derotator for outputting compensated data; An SRC filter which receives the output of the de-rotator as an input and maximizes the signal-to-noise ratio; A blind equalizer which receives the output data from the SRC filter and compensates for the data distortion due to the multipath on the channel; And a carrier for receiving the output of the blind equalizer as an input, detecting and outputting the amount of change (afc_phase) of the frequency offset of the carrier frequency and the lock detection data (afc_lock_det) regarding whether the PLL lock is applied from the output, and restoring the carrier phase. Provided is a carrier restoring device for a digital communication system, comprising a restoring device.

The derotator sweeps a range of frequencies and detects when the carrier restorer is locked near the frequency offset, providing the lock detection data to the derotator and performing a frequency sweeping operation. After stopping, lock the phase by a normal phase-locked loop. In order to perform such a function, the de-rotator may include: a frequency sweeper for generating a phase value for frequency sweeping while being controlled by the lock detection data afc_lock_det; A first numerically controlled oscillator for receiving the sum of the output phase value of the frequency sweeper and the change amount (afc_phase) of the frequency offset as an input and separately outputting a cosine component and a sine component of a signal having a frequency corresponding to the magnitude; And a complex multiplication unit configured to perform complex multiplication with the output of the first numerically controlled oscillator from the I channel output and the Q channel output of the analog / digital converter.

On the other hand, the carrier restorer is connected to the output terminal of the I and Q channels of the blind equalizer and is connected to the output terminal of the second numerically controlled oscillator to output the two channels of the blind equalizer and the cosine and the sine of the second numerically controlled oscillator. A second complex multiplier which performs a complex multiplication between the outputs of the components and outputs the calculation results PH _I (n) and PH _Q (n); A signal separator for measuring the signal power of the outputs PH _I (n) and PH _Q (n) of the second complex multiplier and separating only the outer four symbols from the 16 signal points of the 16QAM modulation scheme; A phase detector which receives outputs of two channels PH _I (n) and PH _Q (n) of the second complex multiplier and calculates phase errors e _{k of} these outputs; A loop filter which removes and outputs noise included in the phase error e _k calculated by the phase detector; A second numerically controlled oscillator that receives a phase error (delta_phase) from which the noise is removed from the loop filter and generates a signal having a frequency corresponding to the magnitude and provides the cosine and the sine component to the second complex multiplier in an output form ; A frequency offset monitor which receives the output of the loop filter and detects whether there is a change in the frequency offset that is impossible to restore data, and provides the magnitude to the de-rotator; A slicer which receives outputs of two channels PH _I (n) and PH _Q (n) of the second complex multiplier and makes a data value corresponding to an original signal point closest to the constellation; And measuring the difference between the output of the slicer and the outputs of the two channels of the second complex multiplier (PH _I (n), PH _Q (n)) and comparing the difference with a reference value to determine the occurrence of a PLL lock. And a lock detector for providing information to the derotator.

In the present invention, since the frequency sweeper is performed in the de-rotator, if the frequency of n / 4 (where n = 1, 2, 3, ...) of the symbol rate at which the lock lock occurs is shifted In the SRC filter in FIG. 3, no lock is taken in the carrier recoverer because of an error due to a mismatch in the frequency domain. Therefore, since a lock lock does not occur, a separate circuit for discriminating it is not required, which simplifies the structure.

In addition, by adding a circuit for monitoring and compensating for the variation in the carrier frequency offset according to the long-term system operation, it is possible to improve reception quality in an area with low SNR.

Preferred configurations and various embodiments of the invention will be more clearly understood from the description of the claims and the following detailed description.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 shows a configuration of a carrier recovery system according to an embodiment of the present invention. According to the drawings, the carrier restoration system comprises an analog-to-digital converter (ADC) 40, a de-rotator 50, an SRC filter 60, a blind equalizer 70, a carrier restorer 80 and A forward error corrector (FEC) 90 is provided. The thick solid arrow indicates the flow of complex data in the baseband, and the dotted arrow indicates the control signal value using a register.

The ADC 40 receives the analog complex signal down to the baseband as an input, samples the I channel and the Q channel separately, converts the digital complex data into digital complex data, and provides the analog complex signal to the derotator 50.

The de-rotator 50 receives the digital complex data of the two channels from the ADC 40 and performs frequency sweeping, and outputs data that compensates for the shift of the frequency band in the baseband, that is, the frequency offset.

The SRC filter 60 is a filter that is matched with a pulse shaping filter (not shown) of the transmitting end and receives the output of the de-rotator 50 as an input so that the signal-to-noise ratio is maximized and output.

The blind equalizer 70 receives output data from the SRC filter 60 and compensates for data distortion due to multipath on the channel using only general data without using a training sequence.

The carrier restorer 80, which is a typical PLL loop, receives the output of the blind equalizer 70 as an input and works in conjunction with the derotator 50 to detect the carrier frequency offset and restore the carrier phase.

The FEC 90 is a channel decoding part that receives an output of the carrier restorer 80 and corrects an error due to noise on the channel.

The carrier restoration system of the present invention detects when a sweep of a range of frequencies in the derotator 50 and sweeps near the frequency offset, i.e., when the lock is engaged, de-rotates the carrier restorer 80. Carrier frequency recovery mode in which the rotator 50 has an open loop shape to stop frequency sweeping, and the carrier phase to hold the phase by a general phase locked loop (PLL) after locking It has the function of executing the restoration mode and monitoring the amount of change of the frequency offset according to the long time system operation and correcting it.

When frequency sweeping is performed on the de-rotator 50, the fall lock, which has occurred in the prior art, does not occur due to an error due to the frequency domain mismatch (see FIG. 5) in the SRC filter 60. For example, the detailed description is as follows.

Assuming that the symbol rate is 20 MBaud, the frequency sweep range is ± 5 MHz (this recommendation is ± 5 MHz, where the frequency offset can occur in the DAVIC standard), assuming that the frequency offset is 2 MHz, Since the frequency corresponding to 1/4 of the symbol rate is 5 MHz, a lock lock occurs at -3 MHz (= 2 MHz-5 MHz).

In the SRC filter 60, the frequency recovery system according to the prior art generates an error due to the mismatch of the frequency domain up to ± 5 MHz in both the case of the false lock and the true lock. Therefore, this error cannot be used to distinguish between a true lock and a true lock, and as a result, it is not possible to prevent the false lock alone.

However, in the present invention, since the frequency sweep is performed by the de-rotator 50, from the standpoint of the SRC filter 60, there is no discrepancy in the frequency domain in the case of true lock and there is always ± 5 MHz mismatch in the case of the false lock. 5 is a graph showing the frequency domain of the SRC filter, in which the solid line 100 is the frequency response curve of the SRC filter, and the dotted line 110 is the frequency of the input signal of the SRC filter 60 shifted by the frequency offset. It refers to a characteristic response curve, and the hatched portion 120 represents a portion where two frequency domains are shifted. This means that it is possible to distinguish between the false lock and the true lock from the determination of whether the frequency domain is inconsistent. Therefore, the carrier restorer 80 may appropriately adjust the parameters of the PLL so that the lock may not be caught by the error occurring at this time. That is, when the derotator 50 performs frequency sweeping, if the frequency of n / 4 of the symbol rate at which the lock lock occurs is shifted, the carrier may be caused by an error due to an inconsistency in the frequency domain in the matching filter SRC filter 60. The lock is not engaged in the decompressor 80.

6 is a detailed view of the de-rotator 50. The derotator 50 is composed of a complex multiplier 150, a first NCO 180, and a frequency sweeper 160.

The frequency sweeper 160 may be configured as a counter 164 whose count value increases or decreases according to a clock rate of the freq_sweep_phase signal. The output value of the frequency sweeper 160 is a ΔΦ value entering the input of the first NCO 180. ΔΦ is the phase value for frequency sweeping. Three input values applied to the counter 164, that is, initial value, afc_lock_det, and freq_sweep_phase, are values stored in a register (not shown) and control frequency sweeping. The initial value designates an initial value of the counter 164 and is a frequency value of the start point of the frequency sweep. freq_sweep_phase adjusts the speed of frequency sweeping and is the operating clock of the counter 164. afc_lock_det is a value that indicates whether the lock is locked in the carrier restorer 80. The lock has a value of '0' before the lock is applied and a value of '1' if the lock is locked. If the value of afc_lock_det is '0', the counter 164 increases the value to sweep the frequency. If the value is '1', the counter 164 stops the operation and maintains the previous output value.

The output value of the counter 164 is added by the adder 170 with afc_phase and provided to the input of the first NCO 180. afc_phase is also stored in the register. The frequency offset monitor 240 of the carrier restorer 80 measures the amount of change in the frequency offset for a long time and writes the phase value afc_phase corresponding to the amount of change in the afc_phase register (not shown) to de-rotator 50. Reads this value and compensates by shifting the frequency by the amount of change.

The first NCO 180 receives a phase value obtained by summing the output value of the frequency sweeper 160 and the value of the afc_phase register from the adder 170, and a cosine value and an imaginary number, which are real components of a signal having a frequency corresponding to the phase value. Generates the sine value of a component.

The first complex multiplier 150 is composed of a plurality of multipliers 252, 153, 154, and 155 and adders 152 and 156, and output data ADC_OUT _I (m) of the ADC 40 including a frequency offset. , Performs a complex product of ADC_OUT _Q (m) and the output cos (m) and sin (m) of the first NCO 180, and calculates the result of the complex product of the input signal SRC_IN _I (m) of the SRC filter 60. Provided by SRC_IN _Q (m). The above-mentioned complex product of the first complex multiplier 150 cancels the frequency offset included in the output data of the ADC 40. The two outputs of the first complex multiplier 150 are values calculated by the following two equations.

SRC_IN _I (m) = ADC_OUT _I (m) x cos (m)-ADC_OUT _Q (m) x sin (m)

SRC_IN _Q (m) = ADC_OUT _I (m) x sin (m) + ADC_OUT _Q (m) x cos (m)

7 shows a detailed configuration of the carrier restorer 80. The carrier recoverer 80 includes a second complex multiplier 190, a signal separator 200, a phase detector 210, a loop filter 220, a second NCO 230, a frequency offset monitor 240, and a slicer 250. ), A lock detector 260 and an or gate 270. The second complex multiplier 190 and the second NCO 230 are identical in configuration and function to the first complex multiplier 150 and the first NCO 180 of the de-rotator 50.

The second complex multiplication unit 190 outputs the outputs of the I and Q channels provided from the blind equalizer 70 (EQ _I (n), EQ _Q (n)), and the output of the second NCO 230 (cosin value, Complex multiplication of the sin value).

As described above, if the 16QAM modulation method does not use all 16 signal points but only the outer 4 signal points, no other lock lock occurs, so that the signal splitter 200 has the outer 4 of the 16 signal points. Separate only symbols. The signal is separated by measuring signal power.

8 shows a more detailed configuration example of the signal separator 200. The signal separator 200 receives the outputs PH _I (n) and PH _Q (n) of the I and Q channels of the second complex multiplier 190 and operates only in the 16QAM modulation scheme. The signal separator 200 includes multipliers 280 and 290 that square and output the PH _I (n) and PH _Q (n), respectively, and an adder 300 that sums the outputs of the two multipliers 280 and 290. And a comparator 310 that compares the output of the adder 300 with the size of the value PLL_TH 14 of the PLL_TH register (not shown) and outputs '1' if the former is large and '0' if the former is large.

In the signal splitter 200, if x> y, the output 16QAM_outside has a value of '1', and if x <y, the correlation between 16QAM_outside has a value of '0' and distinguishing only 4 signal points Will be described with reference to the constellation diagram of 16QAM shown in FIG. In the constellation diagram of FIG. 11, it is a function of the signal separator 200 to distinguish only the outer four signal points on the outermost circle 500. The square of the distance from the origin to each signal point is the power of each signal point. Therefore, in order to distinguish only the outer four signal points, the power value corresponding to the intermediate level between the outermost circle 500 and the middle circle 510 is given as a threshold value y, and each signal coming into the input of the signal separator 200 is input. If x> y is compared with the calculated power (x), that is, if the power of the signal coming into the input of the signal separator is greater than the threshold, it means that 16QAM_outside is '1' as the output and one of the four outer signal points. . On the contrary, if x <y, 16QAM_outside is outputted as '0' and is one of the signal points on the center circle 510 and the innermost circle 520. In order to obtain the S-curve as shown in FIG. 3 (b), only the outer four signal points on the outermost circle 500 line in FIG. 11 need to be used.

The output value 16QAM_outside of the signal separator 200 and the value mode_sel of the mode_sel register (not shown) indicating the modulation scheme are provided to the OR gate 270 to generate an OR _{PLL_EN} signal. The phase detector 210 and the loop filter 220 to be described later operate only when the f _{PLL_EN} signal is '1'.

The constellation of the QPSK consists of only the outer four signal points on the outermost circle 500 among the signal points of the constellations of the above 16QAM. So no signal separator is needed for QPSK. When the _fLL-EN signal is 1, it means that the signal corresponds to the outer 4 signal points on the outermost circle 500 in the QPSK modulation method or the 16QAM modulation method as shown in the or gate 270 of FIG. 7. To obtain the S-curve as shown in FIG. 3 (b), the phase detector 210 and the loop filter 220 only for all signal points in the QPSK modulation scheme and only the outer four signal points in the red line in the 16QAM modulation scheme. Can only be obtained by running.

The phase detector 210 receives outputs PH _I (n) and PH _Q (n) of two channels of the second complex multiplier 190 and calculates phase errors of the outputs. 9 shows a detailed circuit configuration of the phase detector 210. Referring to the figure, the phase detector 210 generates the complements for two of the output PH _I (n) and PH _Q (n) of the two channels, the complementors 330 and 360, PH _I (n) and PH _Q MSB extraction units 320 and 350 extracting the most significant 1 bit of (n). In addition, the phase detector 210 compensates for the output PH _Q (n) of the Q channel and its 2 according to the value of the most significant bit of the output PH _I (n) of the I channel provided by the MSB extractor 320. The output PH _I (n) of the I channel and the multiplexer 370 for selectively outputting any one of the output signals according to the value of the most significant bit of the output PH _Q (n) of the Q channel provided by the MSB extractor 350; It further has a multiplexer 340 for selectively outputting any one of two's complements, and an adder 380 for outputting a phase error e _k by summing two data output from these two multiplexers 340 and 370. The phase error e _k is calculated by the following equation. Since the output of the slicer 250 is a constant constant value, it is possible to calculate only the output value and the sign of the second complex multiplier 190.

e _k = Im {y _k a _k ^* } = y _ik a _rk -y _rk a _ik = C (y _ik sgn [y _rk ] -y _rk sgn [y _ik ])

The loop filter 220 receives the phase error e _k calculated by the phase detector 210. The output from the phase detector 210 generally contains noise. This noise has a mean of zero. Therefore, it is the loop filter 220 to remove the noise using this noise characteristic. The loop filter 220 is a low pass filter (LPF) that acts similar to taking the average of the incoming signal. In addition, the loop filter 220 removes high frequency components that change rapidly and passes only low frequency components that change slowly.

The loop filter 220 illustrated in FIG. 10 is generally used as a second-order loop filter. The loop filter 220 receives the output of the phase detector as described above and outputs a signal from which noise and high frequency components are removed. The loop filter 220 operates in two modes. The PLL operates in a carrier frequency recovery mode that first detects the frequency offset and in a carrier phase recovery mode that corrects the phase error after the frequency offset is set. The distinction between these two modes of the PLL is the adjustment of the loop filter's parameters γ and ρ. First, when the PLL operates in the carrier frequency recovery mode, it acquires and sets the values of γ and ρ experimentally so that it does not take the lock lock but only the true lock. When the PLL operates in the carrier phase recovery mode, the values of γ and ρ are also minimized. Obtain and set experimentally. Switching of the values of γ and ρ is realized using the values of the afc_lock_det register 424 and the multiplexers 412 and 422. That is, when the value of the afc_lock_det register 424 is 0, γ ₁ (9) and ρ ₁ (6) are selected as the carrier frequency recovery mode, and when the value of the afc_lock_det register is 1, γ ₂ (5) and ρ ₂ as the carrier phase recovery mode. (9) is selected. And although a multiplier is needed to multiply γ and ρ values, it can be replaced by simply shifting using shifters 410 and 414. Shifting 1 bit to the left is equivalent to multiplying by 2; shifting 1 bit to the right is equivalent to dividing by 2. In addition, the output of the shifter 414 is summed with the z-inverse transform 420 of the output of the adder 416 and output to the adder 418, which is finally summed with the output of the shifter 410.

The second NCO 230 receives a phase error delta_phase from which the noise is removed from the loop filter 220 and generates a signal having a frequency corresponding to the magnitude. The cos component and sin component of the generated signal are separately input. The path is provided to the second complex multiplier 190. The second NCO 230 is a commonly used structure using a look up table (LUT) 436. The input is provided from the loop filter 220 and the output of the adder 432 is z-inverse transformed 434 and fed back to the adder 432 and provided to the lookup table 436 to provide a sin function corresponding to the input phase value. Output the cosin function.

The frequency offset monitor 240 has a large output frequency (eg, 1 MHz or more) of the second NCO 230 in the carrier phase recovery mode when a change in the frequency offset occurs due to a change in the external environment caused by a long system operation. If an error occurs in the RS decoder and data restoration is impossible, the delta_phase value of the second NCO 230 is written to the afc_phase of the first NCO 180 of the derotator 50, and the PLL is reset.

Referring to FIG. 7 again, the slicer 250 receives two outputs PH _I (n) and PH _Q (n) of the second complex multiplier 190 and corresponds to the original signal point closest to the constellation diagram. It makes a value to be. That is, the transmitter sends a value corresponding to each signal point as shown in FIG. However, noise may be mixed on the channel to receive data having a different value from each signal point. The slicer 250 receives the received data value as an input and outputs the received data value as the value of the closest signal point among the signal points.

The lock detector 260 calculates an error vector magnitude of the determined value and determines that the lock is locked if it is less than or equal to a threshold and generates an afc_lock_det signal. That is, the lock detector 260 receives the input data and the output data of the slicer 250 and compares the difference between the received data value and the signal point in the constellation of FIG. 11 selected by the slicer 250. This difference is the amount of noise. Therefore, the magnitude of noise is measured to determine the presence or absence of the lock of the PLL. The output of the lock detector 260 stores 1 and 0 in the afc_lcok_det register depending on whether or not the PLL is locked.

According to the present invention, the false lock generated by the carrier recovery algorithm of the prior art for the QPSK and 16QAM modulation schemes can be removed without adding a separate circuit. Therefore, the structure of the carrier recovery circuit according to the present invention can be more simply configured to reduce the manufacturing cost. In addition, since the function of monitoring and compensating for the variation of the carrier frequency offset according to the long-term system operation is added, it is possible to provide good reception quality even in a region having a low signal-to-noise ratio (SNR).

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (8)

Analog / digital converting means for receiving a baseband analog complex signal as an input and sampling the sample to convert it into digital complex data; Based on the offset variation amount (afc_phase) of the carrier frequency and the lock detection data (afc_lock_det) regarding whether the PLL lock is engaged, the frequency offset is performed in the baseband by performing frequency sweeping on the digital complex data input from the analog / digital conversion means. A derotator for outputting compensated data; An SRC filter which receives the output of the de-rotator as an input and maximizes the signal-to-noise ratio; A blind equalizer which receives the output data from the SRC filter and compensates for the data distortion due to the multipath on the channel; And Receiving the output of the blind equalizer as an input, detecting and outputting the lock detection data (afc_lock_det) relating to the change in the frequency offset (afc_phase) of the carrier frequency and whether the PLL lock has been received from the output, and restores the carrier phase And a carrier restoring apparatus for a digital communication system. The de-rotator of claim 1, wherein the de-rotator sweeps a range of frequencies and detects when the carrier restorer is locked to sweep near a frequency offset to provide the lock detection data to the de-rotator. And stop the frequency sweeping operation, and hold the phase by a general phase-locked loop after the lock is applied. 2. The apparatus of claim 1, wherein the derotator comprises: a frequency sweeper for generating a phase value for frequency sweeping under lock control by the lock detection data (afc_lock_det); A first numerically controlled oscillator for receiving the sum of the output phase value of the frequency sweeper and the change amount (afc_phase) of the frequency offset as an input and separately outputting a cosine component and a sine component of a signal having a frequency corresponding to the magnitude; And a complex multiplier configured to perform a complex multiplication of the I channel output and the Q channel output of the analog-to-digital converter with the output of the first numerically controlled oscillator. 4. The frequency sweeper of claim 3, wherein the frequency sweeper includes a counter that adjusts the speed of frequency sweeping by increasing or decreasing a count value according to a clock rate of an operation clock (freq_sweep_phase) signal. and increasing the count value while afc_lock_det) has the unlocked state, and stopping the counting operation and maintaining the previous output value if it has the locked state. 2. The apparatus of claim 1, wherein the carrier restorer is connected to an output terminal of an I channel and a Q channel of the blind equalizer, and is connected to an output terminal of a second numerically controlled oscillator to output the two channels of the blind equalizer and the second numerically controlled oscillator. A second complex multiplier which performs a complex multiplication between the cosine of and the output of the sine component and outputs the calculation result PH _I (n) and PH _Q (n); A signal separator for measuring the signal power of the outputs PH _I (n) and PH _Q (n) of the second complex multiplier and separating only the outer four symbols from the 16 signal points of the 16QAM modulation scheme; A phase detector which receives outputs of two channels PH _I (n) and PH _Q (n) of the second complex multiplier and calculates phase errors e _{k of} these outputs; A loop filter which removes and outputs noise included in the phase error e _k calculated by the phase detector; A second numerically controlled oscillator that receives a phase error (delta_phase) from which the noise is removed from the loop filter and generates a signal having a frequency corresponding to the magnitude and provides the cosine and the sine component to the second complex multiplier in an output form ; A frequency offset monitor which receives the output of the loop filter and detects whether there is a change in the frequency offset that is impossible to restore data, and provides the magnitude to the de-rotator; A slicer which receives outputs of two channels PH _I (n) and PH _Q (n) of the second complex multiplier and makes a data value corresponding to an original signal point closest to the constellation; And measuring the difference between the output of the slicer and the outputs of the two channels of the second complex multiplier (PH _I (n), PH _Q (n)) and comparing the difference with a reference value to determine the occurrence of a PLL lock. And a lock detector for providing information to said de-rotator. 6. The apparatus of claim 5, wherein the signal splitter comprises: first and second multipliers for outputting squared outputs of two channels PH _I (n) and PH _Q (n) of the second complex multiplier; An adder that sums outputs of the first and second multipliers; And a comparator for comparing the output of the adder with a size of a reference value (PLL_TH (14)) for distinguishing the outer four symbols. 7. The signal separator of claim 6, further comprising an orgate configured to OR the output 16QAM_outside of the comparator and data mode_sel (QPSK: 0, 16QAM: 1) indicating a modulation scheme, and outputting the orgator. The carrier recovery apparatus of the digital communication system, characterized in that for controlling the operability of the phase detector and / or loop filter. 6. The apparatus of claim 5, wherein the phase detector comprises: first and second complementers for generating complements for two of the outputs PH _I (n), PH _Q (n) of two channels of a second complex multiplier; First and second MSB extractors configured to extract data of most significant bits of the outputs PH _I (n) and PH _Q (n) of the two channels, respectively; Selectively outputs one of the output PH _I (n) of the I channel and the output of the first complementer according to the value of the most significant bit of the output PH _Q (n) of the Q channel provided by the second MSB extractor _; A first multiplexer; Selectively outputs any one of the output PH _Q (n) of the Q channel and the output of the second complementer according to the value of the most significant bit of the output PH _I (n) of the I channel provided by the first MSB extractor _; A second multiplexer; And an adder (380) for adding the two data output from the first and second multiplexers to output the phase error (e _k ).