KR100312620B1 - Dual port static random access memory - Google Patents

Abstract

PURPOSE: A dual port static random access memory is provided to be capable of reducing bit line capacitance and signal delay on a word line. CONSTITUTION: A memory cell array is divided into two memory blocks(10, 30), and an address decoder(20) for selecting a word line is disposed between the memory blocks(10, 30). Each of the memory blocks(10, 30) has a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Signals for selecting word lines are supplied to each memory block via buffers(AB1-AB8) from the address decoder(20).

Description

Dual port status lamp {DUAL PORT STATIC RANDOM ACCESS MEMORY}

1 is a diagram illustrating a memory cell of a general dual port static ram.

2 is a view showing a memory cell array of a conventional dual port static RAM.

3 is a cross-sectional view illustrating a memory cell array of a dual port static ram according to a preferred embodiment of the present invention.

4 is a diagram illustrating a circuit for processing output data in a dual port static ram according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to dual port static RAM, and more particularly to dual port static RAM that reduces signal delay on word lines and capacitance of bit lines.

When designing the static ram for a display, two word lines and two bit lines are used, and the signal source driving the two word lines uses different dual port static rams.

In general, since the static ram itself is composed of a larger number of transistors than the dynamic ram, it is necessary to design the memory cell with the smallest possible area in order to realize a larger capacity. However, as the size of the transistors constituting the memory cell becomes smaller, there is a problem in that it is disadvantageous in bit line and charge sharing.

That is, as shown in FIG. 1, in the memory cell MC of the dual port static RAM, two cell transistors 1 and 3 are turned on by the word line WL. Charge-type data charged in 4) is transferred to the pair of bit lines BL and BLB.

Similarly, the cell transistors 5 and 7 turned on by the display word line DWL transfer data charged in the storage nodes 2 and 4 to the pair of display bit lines DBL and DBLB. At this time, in the charge distribution process between the storage nodes 2 and 4 and the bit line pairs, when the capacitance of the bit line becomes relatively large, it becomes difficult to identify data having a desired potential. Also, the word line must have a potential sufficient to turn on the cell transistor.

2 illustrates a conventional memory cell array in which a plurality of memory cells MC are arranged as shown in FIG. In FIG. 2, as an example, 64? 4 memory cells MC1 / 1 to MC4 / 64 are continuously arranged in plural numbers. The word lines WL and DWL extend in the row direction of the memory cell array, and the bit line pairs BL / BLB and DBL / DBLB extend in the column direction of the memory cell array.

As such, since the word lines and the bit lines extend in the row direction and the column direction of the entire memory cell array, the bit delay due to the increasing bit line as well as the signal delay due to the long word line when the number of memory cells increases. An increase in line capacitance is inevitable.

As a result, this makes it difficult to obtain valid data in a read operation, considering the size of memory cells, which are becoming smaller due to the trend of high integration, in particular the size of cell transistors and the increase in signal delay on word lines and capacitance on bit lines. do.

Accordingly, an object of the present invention is to provide a dual port static ram that can reduce signal delay and bit line capacitance on a word line.

In order to achieve the object of the present invention, the present invention, in the dual port static RAM, at least in the middle of the memory cell array address decoder for driving the word lines of the memory cell array and from the memory cell array And means for outputting a display read signal corresponding to one address as a display data signal through a latch circuit.

The means includes means for precharging a bit line for transmitting the display read signal, and means for simultaneously transmitting and multiplexing the display read signal and then supplying the latched circuit to the latch circuit. As such, the present invention reduces signal delay on word lines and reduces bit line capacitance.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 3, in the memory cell array according to the present invention, the memory cell array 64 ?? 4 of FIG. 2 is divided into two memory blocks 10 and 30, and memory blocks 10 and 30. As shown in FIG. In between are address decoders 20 for selecting word lines. As shown in FIG. 2, the memory blocks 10 and 30 in the memory cell array shown in FIG. 3 also extend word lines in the row direction and the bit lines in the column direction. Signals for selecting a word line from the address decoder 20 are provided to the memory blocks 10 and 30 through the buffers AB1 to AB8. As a result, it can be seen that there is an effect of reducing the signal delay of the word line by half.

4 shows a data output circuit for reducing capacitance on a bit line. As an example, the circuit of FIG. 4 outputs the display read signals b1 to b4 on the display bit lines DBL1 to DBL4 as the display data signals SD1 and SD2. In other words, the circuit shown in FIG. 4 is located in the memory block 10 or 30 of FIG. 3, so that some memory cells corresponding to one address, for example, memory cells MCi / 1 to MCi / 4) display read signals b1, b2, b3, b4 connected to the display bit lines DBL1, DBL2, DBL3, and DBL4 of the display bit lines DBL1, DBL2, DBL3, and DBL4, respectively, ) As a display data signal. Its configuration is as follows.

The PMOS transistors 11, 13, 15, and 17 for precharge having a gate connected to the precharge signal SGPB in common are provided between the power supply voltage Vcc and the display bit lines DBL1 to DBL4. Connected. The display bit line DBL1 is connected to one input terminal 12 of the NOR gate 35 through the inverter 19 and the transfer gate 27. The display bit line DBL2 is connected to one input terminal 12 of the NOR gate 35 through the inverter 21 and the transfer gate 29. The display bit line DBL3 is connected to one input terminal 14 of the NOA gate 39 through the inverter 23 and the transfer gate 31. Finally, the display bit line DBL4 is connected to one input terminal 12 of the NOA gate 35 through the inverter 25 and the transmission gate 33. The outputs of the transfer gates 27 and 29 are multiplexed and then applied to one input terminal 12 of the noah gate 35, and the outputs of the transfer gates 31 and 33 are also multiplexed and then the noa gate 39. Is applied to one input terminal (14).

Inverters 19, 21, 23, 25 are not shown, but two PMOS transistors (one gated to the input terminal and one gated up) connected in series between the supply voltage and its output terminal. Known as a control electrode for switching and two NMOS transistors (one gate connected to the input terminal and one gate used as the control electrode for pull-down switching) connected in series between its output terminal and ground. Inverter.

The output activation signal SGEB is commonly applied to the pull-up switching control electrode of the inverters 19, 21, 23, and 25, and the output is activated to the control electrode for pull-down switching of the inverters 19, 21, 23, and 25. A signal SGE (which is a logical complementary signal of SGEB) is commonly applied.

The latch signal LT is commonly applied to the other input terminal of the noah gates 35 and 39. The output terminal of the noah gate 35, from which the display data signal SD1 is generated, is connected to the input terminal of the inverter 37, and the output terminal of the inverter 37 is connected to one input terminal 12 of the noah gate 35. Connected. Thus, the NOA gate 35 and the inverter 37 constitute one latch circuit. The output activation signals SGE and SGEB are applied to the pull-up switching and pull-down switching control electrodes of the inverter 37, respectively.

On the other hand, the output terminal of the NOA gate 39, from which the display data signal SD2 is generated, is connected to the input terminal of the inverter 41, and the output terminal of the inverter 41 is one input terminal 14 of the NOA gate 39. ) Is connected. Thus, the NOA gate 39 and the inverter 41 constitute one latch circuit. The output activation signals SGE and SGEB are applied to the pull-up switching and pull-down switching control electrodes of the inverter 41, respectively.

Even-numbered transmission signals Φ E are applied to the N-type control electrodes of the transfer gates 27 and 31 and the P-type control electrodes of the transfer gates 29 and 33 and the transfer gates 27 and 31 of the transfer gates 27 and 31. An odd transfer signal Φ 0 is applied to the P-type control electrode and the N-type control electrodes of the transfer gates 29 and 33. The even transmission signal .phi.E and the odd transmission signal .phi.0 are signals corresponding to different timings, respectively, so that display data signals having different transmission timings can be output at the same time.

As described above, the present invention reduces the signal delay on the word line by arranging the address decoder in the middle of the dual-port static RAM memory cell array, and simultaneously activates the display data having different transfer timings and multiplexes through the latches. This has the effect of reducing the capacitance.

Claims (2)

A dual port static RAM, comprising: a memory cell array having memory blocks in which a word line extends in a row direction and a bit line in a column direction, and a memory cell array disposed between the memory blocks in the memory cell array, An address decoder for driving a word line and a bit line in the memory cell array and means for outputting a display read signal corresponding to one address as a display data signal through a latch circuit; Dual port status ram. 2. The transmission of claim 1, wherein the means comprises: precharge means for precharging a bit line for transmitting the display read signal, and multiplexing and transmitting the display read signals simultaneously to the latch circuit. Dual port static ram characterized in that it comprises a means.