KR100312363B1 - Data flow control switch and method for scheduling the same - Google Patents

Abstract

It provides a pipeline scheduler that allows for fair scheduling between the incoming lines of crossbar high-speed switch fabrics.

By round robin, the carry round robin pipeline scheduler (CORPS) realizes scalability to multiple ports. Moreover, CORPS makes one scheduling decision per slot per line by scheduling future slot packets. Since the choice of queue to be scheduled is arbitrary, the present invention is suitable for supporting the quality of service of traffic. CORPS resolves contention evenly between output ports.

Description

Data flow control switch and method for scheduling the same

The present invention relates to a network system and a switch for controlling the flow of data by a network, and more particularly, to a scheduler for managing the flow of data through a large capacity switch.

Input queue switch architectures have always been a viable option for high-speed switching systems. This is mainly because the memory access speed of the input buffer scales with the speed of a single granularity, not with all the exchange capacity. However, it has been previously known that input buffered switches suffer from head-of-line blocking, thereby limiting all throughput to a theoretical limit of 58.6% (MJ Karol, MG Hluchyj. SP Morgan, ' Input Versus 0utput Queuing on a Space Division Packct Switch ', IEEE Transactions on Communications, Vol. C0M-35, No. 12, PP. 1347-1356, Dec. 1987).

Recently, in order to overcome the problem of HOL blocking of input switches, an input queuing scheme called virtual output queuing (VOQ) has been proposed (Y. Tamir and G. Frazier, 'High Performance Multiqueue Buffers for VLSI Communication). Switches', Proceedings of 15th Ann.Symp. On Comp.Arch., Pp.343 354, June 1988 and T. Anderson, S. 0wieki, J. Saxe, C. Thacker, 'High Speed Switch Scheduling for Local Area Networks' ACM Transactions on Computer Systems, pp. 319-352, Nov. 1993,). The idea is to set up a separate queue for each output port of the switch so that packets per empty output port are not likely to be blocked by the first packet that does not proceed due to contention for other ports. In this case, the N × N switch has N cues, i.e., N ² cues per input port. As discussed by other researchers (see A. Mekkittikul, N. McKeown, A Practical Scheduling Algorithm to Achieve 100% Through-put in Input-Queued Swithces, Proceedings of Infocom98, April 1998, VOQ) As a result, 100% throughput can be achieved by the design of a high performance scheduler.

Thus, the scheduler of the VOQ input buffered switch is one of the important design points of the high speed input buffered switch. In the case of VOQ, the scheduler has much more options for exchanging packets from an input port with a backlog to an output port than with a conventional pre-input pre-output (FIFO) input queuing architecture. You can select any I / O port pair from among the input ports with backlog.

Most of the studies on these schedulers can be classified as follows. The centralized scheduler is a single entity with information about all N ² VOQs and makes scheduling decisions about every possible I / O port pair per packet slot (for example, A. Mekkittikul. N. McKeown, 'A Practical Scheduling Algorithm to Achieve 100% Through-put in Input Queued Switches', Proceedings of Infocom 98, April 1998,).

In the distributed scheduler, the scheduler is divided into several functional blocks (typically one or two blocks per input or output port, or one block per input / output cross point) (for example, N. McKeown, M. Izzard). , A. Mekkittikul, W. Ellersick, M. Horowitz, 'The Tiny Tera: A Packet Switch Core'.IEEE Micro, Jan / Feb 1997, pp.2632 and Y. Tamir and HC Chi,' Symmetric Crossbar Arbiters for VLSI Communication Switches', IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 1, PP.1327, 1993,).

1 is a schematic block diagram illustrating an example of a concentrated scheduler. The centralized scheduler needs to access N ² pieces of information before making scheduling decisions. Such a scheduler is generally not scalable in the sense that the hardware installing the scheduler is strongly dependent on the number of switch lines (N).

The distributed scheduler has the potential to make the hardware less dependent on the number of switch ports. However, what has been proposed so far still requires a communication mechanism to provide information about all N ² queues before a scheduling decision can be made for individual packet slots. This communication, in parallel (as with the SLIP scheduler. N. McKeown. M. lzzard, A. Mekkittikul, W. Ellersick, M. Horowitz, 'The Tiny Tera: A Packet Switch Core', IEEE Micro, Jan / Feb 1997, pp. 26-32), or in a round robin fashion (Y. Tamir and HC Chi, 'Symmetric Crossbar Arbiters for VLSI Communication Switches'.IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 1 , pp. 1327, 1993).

2A and 2B are schematic diagrams showing the architecture of the parallel method and the round robin method, respectively. In the parallel communication architecture in FIG. 2A, each block is fairly dependent on the size of the switch. This is because each block must accept N ² messages. The round robin architecture in FIG. 2B overcomes this problem but results in another problem. In other words, to achieve scheduling decisions for all output ports, message exchanges must complete one round of a single packet slot. This requires message processing that is at least N times faster than scheduling decisions.

Moreover, in recent years, the Round Robin RobinGreedy Scheduler (RRGS) has been proposed. This is a scheduler based on message passing (exchange), where each input port makes a scheduling decision and passes this information to the next port in a round robin fashion (see Japanese Patent Application No. ll-172584 by the present applicant). ). To alleviate message exchange rate requirements, RRGS introduces a pipelined feature. The input port makes enough scheduling decisions about future slots, allowing the message exchange mechanism enough time to spread this information to other input ports. RRGS can be installed at high speed and easily.

First, the architecture of a general pipeline scheduler will be described. 3 is a schematic diagram illustrating an input buffer switch architecture. Regarding the switch architecture, it is assumed that scheduling is applied to pure nonblocking N × N crossbar switches. It is also assumed that the virtual output queue V0Q is used to cope with the HOL blocking problem.

Moreover, assume a fixed size packet and a constant link speed. Time is slotted. One slot is defined as the time taken to transmit one packet by the output link. If no output port contention exists, the nonblocking crossbar can exchange up to N packets per time slot. The basic task of the scheduler is to determine, for each slot, which of the N ² V0Q queues with no spaces can access the output port. For efficiency, the scheduler must resolve all contentions between queues with backlogs within l time slots.

As line speeds increase, it is important that the scheduling algorithm is scalable to large switches. Therefore, distributed architecture is considered to be powerful. In a distributed architecture, the tight processing time required for packet scheduling in high-speed switches is mitigated. For example, in a l6 x l6 port switch that is a line rate of 10 Gbit / s, the scheduling decision must be made at each packet transmission and is 42 ns for a 424 bit ATM cell. When using the sequential scheduler, each decision must be made less than 0.16 ns on a 16x16 switch. This is because N ² decisions must be made. In the case of using an optical core, it is meaningful to disperse the electronic hardware from port to port while maintaining all the switching bandwidth requirements of the optical core. Moreover, the distributed scheduler is naturally scaled to any number of lines. 4 illustrates such a scheduler.

In FIG. 4, each crossbar input port has an input port scheduler module (SM). Each SM has an SM-ID which is an individual ID. In order to maintain scalability with the number of lines, the SM is only allowed to communicate with one neighboring SM. This ensures that the SM hardware block can be used with any N × N crossbar fabric. The SM communication chain is shown in FIG. This is used to communicate scheduling information such as time slots, slot ownership and output port reservations. The only interaction between the crossbar module and the SM is through the global clock. This informs all SMs which slot is the current system time slot (CTS) and the current decision table (not shown) regarding the input / output port pairs exchanged in the CTS. This can be realized by a global memory recorded by the scheduler and read by the crossbar fabric.

For each time slot, each SM is assumed to have full freedom of choice with respect to the output port of the access request destination. SMs making the same choices cause "collisions" (collisions), which need to be resolved before determining the global scheduling pattern for a given slot. If the SM will have current information about all other requests, the communication chain must operate at a rate that is N times faster than the rate of the scheduling decision. That is, the SM must be able to receive N messages before making one scheduling decision.

In order to preserve the speed of the SM hardware along with the line speed, it is possible to use the N look ahead scheduling scheme. That is, each SM makes a scheduling decision regarding at least N slots in the current slot. This function ensures that the SM knows about other scheduling decisions made for the same time slot before making scheduling decisions. Moreover, this function does not need to speed up the communication chain to N times the input line speed. The time axis is subdivided into slot frames. Each slot frame is just N consecutive slot sequences. In this way, time can be regarded as a frame sequence.

To set criteria to resolve collisions between competing SMs, first use a matrix . The N × N priority matrix is a matrix that defines the order in which the SM traverses a given time slot in the future. The matrix row indexes the slots in the current frame (the frame including the current system slot), and the matrix column indexes the slots in the next visited frame. The elements of the matrix specify which SMs should "visit" the slots in the next frame shown by the column index.

FIG. 5 is a diagram illustrating a 4 × 4 priority matrix, and FIG. 6 illustrates the pipelined time slot traversal order for the matrix shown in FIG. 5. Note that the pipelined decision process is first included in the use of the matrix. For example, when the current time slot of the system is the second slot of the current frame, while SM # 1 is making scheduling decisions regarding the fourth slot of the next frame, SM # 3 is assigned to the second slot of the next frame. I'm making a scheduling decision.

The N × N priority matrix is created by rotating the SM string in the same direction as the communication chain message exchange. This ensures that all SMs get information about the ports that have already been scheduled in a timely manner. Collision can be completely avoided if an SM avoids choosing an output port that has already been selected by a previous "visitor" (that is, an SM before a time slot).

However, if the SM is limited to select an output port that has not yet been selected, the V0Q service rate becomes difficult to predict. Moreover, there arises a problem of significant equity. For example, in the matrix of FIG. 5, for the four slots of the next frame of the current frame, each of four traversal sequences, namely (1, 2, 3, 4), (2, 3, 4, 1), ( 3, 4, 1, 2) and (4, 1, 2, 3) can be considered. Here, SM # 1 and SM # 2 have a backlog at the constant in the queue of the given output port, and the queue corresponding to the other SM is left blank. In this case, since SM # 1 visits three of the four slots of the frame before SM # 2 in the traversal order defined by the matrix, three of the four slots are taken by SM # 1. This actually happens in RRGS (see Japanese Patent Application No. ll-l72584 by the applicant). Furthermore, since it involves many orders, it is easy to see that, first, when the size of the matrix is greater than N, the communication chain used does not already guarantee timely transmission of the scheduling information necessary to make consistent scheduling decisions. .

As such, the RRGS scheduler is easy to install at high speed, but does not realize predictable and adjustable service rates. As described above, there is also a problem of fairness in that scheduling of some VOQs is interrupted by different VOQ states.

It is an object of the present invention to provide a scheduler for a large capacity switch that allows full freedom of choice when the VOQ queue performs scheduling.

Another object of the present invention is to provide a scheduler that makes the VOQ service rate predictable and adjustable.

It is another object of the present invention to provide a fair scheduler in the sense that any VOQ is scheduled with the same probability regardless of other VOQ states.

Another constraint in the scheduler design is the determination of which VOQ from the N VOQs belonging to a given incoming line to be scheduled next, from the scheduler's control. In other words, for each input port, which external entity is completely free to determine which output port is scheduled next. This request is important for future quality of service (QoS) support. It is clear that this has the potential to reduce the maximum throughput that makes the predictable service rate of V0Q more predictable. However, this is important. Maximizing throughput throughout the switch is likely to deplete some queues and, moreover, hinder the flow associated with those queues.

1 is a schematic block diagram illustrating a centralized VOQ scheduler.

FIG. 2A is a schematic diagram of a distributed scheduler architecture each illustrating a parallel approach and b a round robin architecture. FIG.

3 is an explanatory diagram of an input buffered switch architecture.

4 is a schematic block diagram showing a configuration of an input port distribution scheduler.

FIG. 5 is a schematic diagram showing an example of a preferred matrix used to solve a collision. FIG.

6 is a schematic diagram illustrating an example of a pipeline scheduling decision.

Fig. 7 is an explanatory diagram showing the carryover operation between SMs in one embodiment of the scheduler according to the present invention.

8 is a format diagram of an S message in the present embodiment.

Fig. 9 is a format diagram of a data structure which is a scheduler module in this embodiment.

Fig. 10 is a flowchart showing a CORPS scheduling algorithm in the present embodiment.

11 is a schematic diagram illustrating a C0RPS VOQ queuing model.

12 is a graph showing packet delay as a function of system load.

Fig. 13 is a graph showing the complementary delay variance of an l6x16 switch with a C0RPS scheduler.

14 is a block diagram illustrating an example of a C0RPS controller.

15 is a graph illustrating expected delays for system load of various contention schedulers.

※ Explanation of code for main part of drawing ※

101: task box 105: task

(Means to solve the task)

According to a first aspect of the invention, a switch for controlling the flow of data in a network has a scheduler having a plurality of input ports, a plurality of output ports, and a plurality of input port scheduling modules. Each schedule module schedules a specific input port of the plurality of input ports to send the designated output port data of the plurality of output ports. The schedule module exchanges scheduling messages between the modules, and each schedule module calculates a future time slot for which the schedule module wants to access a designated output port. The schedule module further includes whether the future time slot is currently reserved by the corresponding schedule module, whether the future time slot is blocked, and whether the future time slot is taken by another schedule module. Based on whether or not the future time slot is valid, it is determined. If valid, the schedule module takes the future time slot and inputs information indicating that the future time slot was taken in a scheduling message.

The scheduler of the switch advances the future time slot by a predetermined number of time slots when the future time slot is reserved or taken.

The switch queues data input through the input port using virtual output queuing, which maintains a separate queue for each of the output ports. Alternatively, virtual output queuing for individual ports may be independent of virtual output queuing for other ports. Moreover, the switch has a service rate of predictable and adjustable virtual output queuing. The switch scheduler also selects a designated output port based on weighted round robin.

According to a second aspect of the present invention, a method is provided for scheduling input packets arriving at various input ports of a switch to be sent to various output ports of the switch. Here, the scheduler has a plurality of input port schedule modules. This way,

a) the current schedule module receiving the scheduling message from the previous schedule module,

b) the current schedule module designing future time slots to access one of the plurality of output ports;

c) selecting one of said plurality of output ports to schedule for transmission in said future time slot;

d) determining whether the future time slot is already reserved by the current schedule module;

e) determining whether or not the future time slot is blocked if the future time slot is not reserved by the current schedule module;

f) if the future time slot is not blocked, determining whether the future time slot has already been taken by another scheduling module;

g) if the future time slot has already been taken by another schedule module or already reserved by the current schedule module, determining from the scheduling message whether a carryover operation has already been initiated,

h) if the carryover operation has already begun, setting the future time slot to a blocked state and returning to step d;

i) if the carryover operation is not started, advancing the future time slot by a predetermined number of time slots, setting a carry forward flag, and returning to step d;

j) if the future time slot is not taken by another scheduling module, taking the future time slot and inputting information into the scheduling message indicating that the future time slot has been taken;

k) passing the scheduling message to the next schedule module.

Data entering through multiple input ports is queued using virtual output queuing, which maintains a separate queue for each output port. Virtual output queuing for individual ports is independent of the virtual output queuing for other ports. In addition, the service rate of the virtual output queuing is predictable and adjustable. The scheduler selects the designated output port based on weighted round robin.

Embodiment of the Invention

The carry over round robin pipeline scheduler (hereinafter referred to as CORPS) according to the present invention is a fair scheduler for a high speed crossbar fabric and solves the problem of the scheduler of the prior art. CORPS has scalability with respect to both the line speed and the number of lines in a high speed switch fabric. Because of the scalability with respect to the number of lines, a distributed architecture with message exchange is chosen. Moreover, like RRGS, pipeline architectures are used to keep message processing requirements scalable with line speed.

Moreover, the present invention introduces a carry over operation to provide fairness while maintaining a distributed architecture and message exchange scheme. In this way of thinking, when a scheduler module SMa visits a slot in which a desired output port is already reserved by the scheduler module SM preceding it, the port is N slots in the future from the slot to be processed. Is to carry over scheduling enforcement. If you know that the slot is on the same output port, the SM will proceed to N slots until it finds a slot for which the desired output port is not yet taken.

FIG. 7 is an explanatory diagram illustrating a carryover operation among a plurality of scheduler modules SM. The carryover operation can be extended to N frames depending on the number of " conflicting " SMs in a given time slot. The slots affected by the carry over operation can be regarded as a set of slots (hereinafter referred to as a collision solving set) taken to solve the collision (collision). In addition, slots that have been carried forward will be re-visited by all SMs in subsequent frames. Thus, a slot taken by a carryover operation potentially receives new collisions, possibly causing overlap of collision resolution sets. This is likely to require N ² frames, that is, N ³ slots in total, in order to solve a large number of collisions.

Output of over one to shorten the scheduling delay and at the same time mitigate the memory requirements of the system, the running count is, February operation of the affected frame by February operation SM, a plurality of slots taken to address the Curley jeonreul Limited to no other scheduling for the port . In other words, one slot is not used to solve multiple collisions at the same time.

For example, suppose SMa finds a slot m taken by a given port p, thereby triggering a carryover operation. The slot reserved by SMa as a result of this carryover operation is called mx. None of the slots mn (1 ≦ n <x) becomes available (stopping, blocking) in SMa for the same port p. Thus, this blocking function ensures that multiple collisions for a given slot are prohibited.

The C0RPS scheduling algorithm is described below. First, the message passed in the communication chain and the SM database in which the scheduling decision is recorded will be described, and then the flow of the algorithm will be described.

In each cell slot, it defines a vector of scheduling decision elements that are passed from the SM in the chain to the next SM. The S message contains a scheduling element (hereinafter referred to as SE) of a scheduling decision consisting of at most the last N cell slots. That is, the S message has at most N SE. The S message has the following format.

8 shows the format of an S message. In the same figure, each scheduling element SE of the S message includes a time to live (TTL), a time slot ID (TSI), an SM-ID, and an output port ID (0PI: 0utput Port ID). )

The duration time TTL is initially set to N by the SM that generated the SE.

The time slot ID (TSI) is defined as the number of slots until a slot is scheduled in the current TS (time slot) and is an ID of a slot to be scheduled.

SM-ID is an input port scheduling module ID for scheduling reservation.

The output port ID (0PI) is the ID of the output port to be scheduled.

At the beginning of the slot, each SM receives an S message from the preceding SM. This includes the SE attached to the last N slots. Every SM makes at most one scheduling decision per time slot. When the SMp makes a scheduling decision, the SMp creates a new SE having the following contents.

TTL = N

TSI = number of slots (including it) from the current slot to the selected time slot (m)

SM-ID = p

OPT = desired output port q in the time slot (CTS + m) in which packets are exchanged from input port p to output port q.

Regardless of the scheduling decision, each SM decrements the TTL of all other SEs in the S message before discarding the message to the next SM and discards the SE of TTL = 0.

Each SM has a memory array SC including (N + 1) N positions. The first N positions record the scheduling decision of the current frame which is read by the crossbar switch module. These positions, among all SMs, have the same information about the current frame and can be accessed by the crossbar controller in several ways. Strictly speaking, the SM does not need to preserve this information. The remaining N ² positions are used to record future scheduling decisions. The memory array has the following format.

As shown in Fig. 9, the following fields are defined.

Time slot ID: Index to the SC array. This gives the time slot ID where the SC location holds the scheduling information. This is synchronized with the global clock provided by the crossbar module. This field wraps round as the global clock advances.

Blockage: This defines the set of output ports that the SM is preventing from making scheduling reservations. There may be up to N entries in this field. It is also blank at first.

Reservations: This records scheduling reservations for a given time slot. CORPS ensures that all entries in this field for the current time slot (CTS) are the same across all SMs. Thus, the crossbar module can read the cell's current input / output scheduling in any SM (CTS). The algorithmic consistency check can be performed by the crossbar module by comparing this field between all SMs, if the crossbar controller has sufficient processing time.

CORPS Scheduling Algorithm

Each SM follows the CORPS scheduling algorithm described herein. In C0RPS, there is no restriction as to which output port a given SM tries to schedule. The choice of which output port you want to schedule depends on the unique policy that is left to each SM and serves that VOQ.

10 is a flowchart illustrating a CORPS scheduling algorithm. Hereinafter, the task boxes l0l to ll0 will be described with the flow of the same drawing.

First, in task 101, an S message is received from a previous SM, and the TTL (duration time) is decremented for each SE. Furthermore, when TTL> 0 for a given SE, the TSI (Time Slot ID) is decremented to update the memory array SC in the TSI. If TTL = 0, the SE is removed from the S message. Also, the CARRY flag is reset to CARRY = FALSE (see task 109).

The task 102 (calculate execution slots) then calculates which future time slots (FTS) are to be scheduled using the appropriate priority matrix. For simplicity, the matrix can be encoded in a function f of the form FTS = f (CTS, SM-ID).

Furthermore, select which output port (OPIS) the SM wishes to schedule for transmission (task 103: selection of output port). In addition, the strategy for selecting an output port may depend on the result of the previous task. CORPS does not specify this strategy (for example, weighted round robin selection of output ports is available).

Then, it is only checked whether any of the reserved entries of the SC (FTS) is the same as the SM executing this scheduling (task 104): a test of owning a slot).

If the SM-ID is different from the SM that performs this scheduling (NO in task 104), furthermore, in the inhibit entry of SC (FTS), the output port that OPI (output port ID) is testing for scheduling is It is checked whether there is something like (OPIS) (task (l05): a test of self-blocking).

If it is self-blocked (YES in task 105), the S message is passed to the next SM (task 106).

If it is not self-blocking (NO in task 105), it is checked whether or not OPI (output port ID) is the same as the output port OPIS that is testing scheduling among the reserved entries of SC (FTS). (Task 107: Test whether the slot is taken).

If the slot is not occupied (NO in task 107), a reserved entry in which SCPI has its own SM-ID and 0PI equals 0PIS is created, and TTL = N and TSI = FTS are used. -ID equals its own ID and creates an SE with OPI = OPIS (task 108: takes a slot). Subsequently, the procedure proceeds to task 06 (exchange of S messages).

If it owns this slot (YES of task 104) or if the slot has already been taken (YES of task l07), it is checked whether the carryover operation has already started, and the flag CARRY = Check TRUE / FALSE. If CARRY = TRUE, an entry of OPI = OPIS is created in the blocking field of SC (FTS), otherwise CARRY = TRUE is set, and FTS = FTS + N is further set (task 1010 ): February).

When the carryover operation is executed by the task 109, a health check is subsequently performed (task ll0). In other words, the FTS should not be far from 2N ² in the CTS. If (FTS-CTS)> 2N ² (NOK of task 110), an error message is issued and processing is stopped. If (FTS-CTS) ≤ 2N ² (OK of task l10), the process returns to task 104.

Using the CORPS algorithm has the following advantages: The VOQ with the backlog is not depleted even if it is finally selected by the SM. Assuming that VOQq is selected by the SMp, according to FIG. 10, the only case where the SMp does not succeed in scheduling q and exits the reservation loop is when it is blocked for the attempted slot. The fact that SMp is blocked means that the queue q is already scheduled, but the following points should be noted. The only other way to get out of the loop is to pass a health check, but this means that the carryover did not find an empty slot in the next N frames. Since there are at most N SMs involved in one collision, and many collisions are forbidden by the blocking procedure, they do not fall out of the loop in this way.

A set of m input ports SM for which the same output port q is to be sequentially scheduled is referred to as M. Further, the number of slots scheduled by SMi for the output port q between time slots of? T is referred to as n _i ^q (? T). The scheduler, for any period (Δt) and i, j∈M,

N _i ^q (Δt) -n _j ^q (Δt)

Is m-pair (m-fair). In other words, the SM cannot make N reservations before any other SM.

CORPS is m-equivalent (l <m ≦ N). Assume that m SMs collide for output port q in a given slot ts. Each of the m SMs colliding is not blocked for that slot. If it is ever blocked, it is even impossible to test whether the slot has already been taken (task 105 of FIG. 10). If these m SMs are not blocked in slot ts, there must be n empty slots between ts + nN (1 &lt; n &lt; i). Because the only way to access these slots in the future is through carryover operations, and furthermore, these SMs know that they are not performing carryover operations on these slots (or they are blocked at ts). This means that within the next i frame, the colliding SMs will each make a scheduling request for q. Here, they continue to collide for N consecutive slots of the current frame, and furthermore, if each collision creates one scheduling for the next i-frame for every SM, each SM is an output port (q). N slots are reserved for the next i-frame. As such, any subset of the slots taken from the iN slots of the i-frame in which the collision is to be resolved may not include an SM with more benefits than the N slots than other SMs.

The last note is interesting. This is because even if the measurement period is somewhat long, V0Q having a backlog in succession means that no other SM is served more than N packets before the corresponding VOQ. In fact, in a sufficiently long period, all conflicting SMs get exactly the same number of reservations.

Moreover, under heavy load, assuming that all queues with a common output port are selected by the same number of times by their SMs, they all have the same throughput (task 1008 in Fig. 10).

There are a few comments about the CORPS architecture. The communication chain used to pass scheduling information between the SMs can be used to change the scheduling pattern of the slot in any manner as long as it is at least N slots in the future. For example, it is possible to cancel the output port reservation. This feature is useful when the SM has just made a reservation in the future because of the collision, but finally realizes that the port requested by the next slot is empty. If the SM makes different reservations for the same packet (the closer one), the far-end reservation causes a waste of bandwidth without withdrawal. However, reservation taking may also adversely affect the above properties. For example, if a collided SM later withdraws a reservation, it adversely affects the delay of packets scheduled later in the same colony. In other words, if a SM collided with i-1 other SMs later cancels a reservation due to this collision, the system is not in a state in which only i-1 SMs were initially charged. This scheduler is as simple as possible, meeting the initial design goals. This ensures that the hardware required for final installation is a simple chain.

C0RPS resolves the conflict by extending packet scheduling over multiple frames. Therefore, it is natural to expect that the average packet delay will be larger than other schedulers. For this reason, the performance of CORPS is constantly analyzed under traffic. The final goal is to evaluate how much carryover affects packet delay, and to obtain the maximum utilization from the system compared to competing scheduling algorithms.

To evaluate the scheduler's performance with respect to packet delays against traffic load, you create a CORPS analysis model. In the following, for simplicity, the following two main assumptions are made.

(i) constant traffic arrival process and

(ii) Irregular V0Q queue selection by each SM (task 13 in FIG. 10).

Defines the target VOQ queue Q _mn per output port n of a given SMm. The packet arrives at all input ports according to the Bernoulli process at strength p. Specifically, in a given slot, the probability that one packet arrives at one input port is p. Moreover, all packets have the same probability per output port (assume i). Therefore, the packet arrival process in the target VOQ queue has a Bernoulli distribution of parameter p / N.

Regarding VOQ selection, each queue with no given SM blank is selected with equal probability for scheduling (assumed ii). Thus, for any VOQ, if the VOQ is not empty , q is the probability that it is chosen. Hereinafter, according to Chipalkatti et al. ('Prolocols for 0pticalStar-Coup1er Network using WDM,' IEEE Journal on Selected Areas in Communications, Vol. 11.N0.4, May 1993), if the utilization of all V0Q is ρ, one SM The number of empty VOQ queues expected at is given by 1+ (N-1) ρ.

Moreover, it is convenient to introduce another probability that is closely related to q. Let r be the probability that any queue is chosen by its scheduler. r is different from q in that q assumes that the queue has no spaces, but r does not have this limitation. It is not difficult to see the following equation hold.

r = ρq = p / N (1)

The behavior of Q _mn can be modeled as follows. Clearly, between packet arrival times depends on the geometric distribution of the parameter p / N. The first packet must wait until being selected by the SM. The selection takes place with probability q for a given slot. After being selected, in accordance with task 1005 of FIG. 10, there is a possibility to be prevented from scheduling. When the probability that the block m is blocked for port m in a given slot is P _b ^m , the waiting time until the first packet is selected by the SM depends on the geometric distribution of the parameter s = q (lP _b ). Since the probability is the same for all output ports, we can drop the superscript (m). After Q _mn is selected, it is always assumed that reservations are made in future time slots, and packets are also sent out of the queue to some kind of belt conveyor . Here, the packet waits for a reservation time slot to come out and exits from the system at the point of arrival.

11 is a schematic diagram showing the entire model used for the Q _mn queuing system. The arrival packet is first added to Geo (p / N) / Geo (s) / 1 queue. When a packet _leaves this queue, it receives an additional delay (D _corpx) . This is the delay that results from the specific way C0RPS resolves the collision. This is modeled by a box with an infinite number of servers.

The expected delay of a packet passing through C0RPS is given by the sum of the expected delay for Geo (p / N) / Ge0 (s) / 1 and the average delay <D _corps > (MJ Karol, MG Hluchyj, SP Morgan). , 'Input Versus 0utput Queuing on a Space-Division Packct Switch'.IEEE Transactions on Communications, Vol. C0M35, No. 12.pp. 1347-1356, Dec. 1987). This can be written as follows (In addition, the average value indicated by the upper line in the formula is the same as that enclosed by <> in the specification text).

However, S is a random variable of the Geo (s) time distribution. Next, the calculation of <D _corps > will be described.

After Q _mn is selected (the leading packet leaves Geo (p / N) / Geo (s) / 1), some thought can occur. First, the SMm must confirm that it does not own the slot being tried (task 104 in Fig. 10). The probability that a slot is owned by the SM for the output port ⁿ is called P ₀ ⁿ . Moreover, the probability that a given SM is blocked for output port n at a given time slot is called P _b ⁿ . By this, the following equation can be derived.

According to CORPS, the slot the SM is visiting can prevent the SM from attempting to reserve only if the slot is being used to resolve the previous collision for the same output port.

As a result, the probability that an SM owns a port is

P ₀ = 1- (1-P ₀ ⁿ ) ^N (5)

Becomes

The expected delay &lt; RTI ID = 0.0 &gt; D ₀ &lt; / RTI &gt; caused by task 104 in Fig. 10 is given by the following equation.

If the slot first visited by the SMm is empty (the tests of tasks 104, 105, and 107 in Fig. 10 are all NO), the matrix method is used first, so that the average delay of the packets <D _corps > It is easy to see N being. &_Lt; D _corps &gt; &gt; N, when there is no collision, at least one reservation overflows the future second frame. Here, the irradiation with respect to the delay (D _o) received by Curley before. When a collision with i-1 other SMs occurs for a particular slot, depending on the priority of the SMm for that slot, the delay D ₀ may vary from N to iN. Therefore, when SMm is the i-th SM that visits the slot, the probability that the packet delay is jN is called P [D _corps = jN | v = i]. For example, if m is the first SM to visit that slot,

The above equation is merely that if the SMm is the first SM to visit the slot, the packet is delayed by N slots. This is because the CORPS scheduler schedules one future frame if no collision occurs. Next, recalling that the VOQ queue for any output port (especially output port n) of SMs (s ≠ m) has no space and that the probability selected by s is r, P [D _corps It is not difficult to see the general formula for = jN | v = i] as

The top of equation (8) is that if m is the i-th SM visiting the slot, the delay is at most iN. The lower binomial coefficient is that if il SMs visit the slots before m, then j-1 SMs are likely to collide with m. Simultaneous distribution of (D _corps = jN and v = i) events can be easily derived by multiplying the marker by 1 / N. This is because SMm is consistently certain that it is the i-th visitor of slot l ≦ i ≦ N (see Fig. 5).

Next, wait delay (D _o) of the packet can be derived as follows.

All delays caused by the CORPS scheduler are:

The final probability to calculate is P _b . This is the probability that, for a given output port n, one SM is blocked in a given slot. The following equation can be shown.

Note that for Geo (s), <S> = 1 / s and <S (S-1)> = 2 (1-s) / s ² , all average delays a packet receives from the system It becomes as follows.

However, s = q (1-P _b ). The first three terms correspond to the delay in the V0Q queue before scheduling is performed. The third term corresponds to the additional time required for the packet to wait by the C0RPS pipeline and collision resolution function.

Fig. 12 shows the analytical results of delay vs. throughput of CORPS compared with simulation of a 16x16 switch with CORPS scheduler. In this figure, there is a difference between the average queuing delay received until the packet is selected by the SM scheduler and the C0RPS delay, as pipeline and collision resolution schemes are used. As can be seen from the figure, the analytical prediction is in good agreement with the behavior of the simulated system.

This figure shows that the scheduling delay is superior to the queuing delay over all of the loads. Only in very high loads (when a queue begins to form), the queuing delay becomes important. This means that CORPS is working well in scheduling future packets as soon as they arrive in the VOQ queue. On the other hand, the average delay caused by CORPS increases from about one frame with light load to about five frames when the load reaches 0.85.

For the sake of completeness, in Fig. 13, the complementary distribution of all delays at the 16x16 C0RPS switch is shown. The curve is a case where the loads obtained by the simulations are 0.8 and 0.85. First, it is noted that no packet takes more than N ² slots to pass through the system. This is because CORPS does not allow multiple collisions to occur. In fact, the tail of the distribution, N ^2/2 = 128 seems to end in the vicinity. However, if the system is driven by a very large load, the packet delay is close to N ² .

14 is a system block diagram for realizing CORPS. The VOQM module inputs a packet to the virtual output queue VOQ. In addition, this module makes a request to the SM module instead of the given queue. The SM module controls the message exchange to realize the CORPS scheduler. The SM module communicates with the VOQM to inform about future slot reservations. This notification is kept in V0QM and, in a given slot, causes the packet to be sent to the crossbar register to be exchanged.

In the figure, the communication between the SM and the crossbar controller is shown to be via a bus, but this need not be this particular kind of communication.

In a fair comparison between scheduling algorithms, complexity and installation costs must be considered, as well as performance measures such as average delay and throughput. The first selection criterion is high throughput. Moreover, only schedulers running on VOQ are compared. Thus, as a scheduler competing with the present invention, a comparison with 1-SLIP and RRGS is performed. The reason for choosing one iteration rather than multiple iterations is for fairness of the comparison process. That is, it is assumed that at any input port, at most one decision can be made per slot. i-SLIP (i &gt; l) requires substantially multiple scheduling decisions per slot.

In the performance comparison, it is based on both analytical and simulation results. Constantly, the delay performance of RRGS and SLIP for traffic can be approximated as follows.

The results of the RRGS are described in Japanese Patent Application No. 11-172584 by the present applicant, and the results of the SLIP are described by N. McKeown, 'Scheduling Cells in an Input-Queued Switch', PhD Thesis, University of California at Berkeley. Described in 1995.

Fig. 15 shows the performance of the average delay versus throughput of these algorithms in contrast to C0RPS. As is clear from this figure, RRGS and CORPS can withstand much higher loads than SLIP before the delay becomes large. As can be readily seen, the derivatives of these curves are quite small for RRGS and CORPS at high loads. However, any algorithm has an offset delay budget at moderate to light loads. In the case of RRGS, this is only because the pipeline method is used. In the case of C0RPS, as explained previously, the additional delay is due to the collision resolution. However, CORPS has two advantages over RRGS.

(i) There is freedom to choose which output port the SM will select.

(ii) It is a strictly fair scheduler.

SLIP is also a fair scheduler, but the collision resolution process is quite different from that of C0RPS.

As mentioned above, C0RPS gives you full freedom of choice as to which output port to try to schedule. That is, each V0QM can freely select the output port to be scheduled instead of the given V0Q. This was an important part of the scheduler design strategy. Thus, many algorithms, in conjunction with CORPS, are available for VOQ selection. So far, one such algorithm has been described, namely the irregular selection of VOQs with no gaps. Examples of other VOQ selection strategies are possible. The V0Q selection strategy can be classified into two classes: cooperative selection strategy and non-cooperative selection strategy.

The uncooperative VOQ selection strategy is one in which the VOQ selection decision is made for each input port VOQM independently of other input ports. The irregular selection strategy used for CORPS analysis belongs to this class.

Weighted Fair Queuing (WFQ) is a service strategy well known in the packet-switched research literature (see, for example, H. Zhang.'Service Disciplines for Guaranteed Performance Service in Packet-Switching Networks', In Proceedings of IEEE, Vol. 83, no. 10. pp. 13741396. 0ct, 1995,). The idea is to regulate the service rate of the various queues that contend for the output link capacity, depending on the desired weight. In the VOQ C0RPS switch, the output port band can be divided into a plurality of VOQMs by some kind of signal reception controller. In that case, using WFQ, it is possible to enforce that the maximum service rate of the VOQ queue does not exceed the V0QM band of the given output port.

Rate Controlled Service (RCS) rules assume that a given traffic flow fills some bursty constraints with network entry points (L. Georgiadis, R. Guerin, V. Pens, 'Efficient Network QoS Provisioning Based on'). per Node Traffic Shaping ', Proceedings of INFOCOM 96, vol. 1.pp. 102-110, 1996,). These constraints are generally enforced by the traffic shaper at the edge of the network. Moreover, traffic shapers are also placed in intermediate switches, such that traffic follows their constraints to each intermediate switching point in the network. Traffic shapers are generally realized by a leaky bucket algorithm. J. Turner, New Directions in Communications, or Which Way to the Information Age ?, IEEE Communications Magazine, vol. 24, pp. 8-15, 1986, describes one such algorithm. The basic Ricky bucket is a system with two queues, one for data and one for tokens, or permits. Data packets on the queue require a permit to be serviced. Only a limited number of permits are stored in the permit queue. Permits are generated at a constant rate. This kind of traffic shaper can be used to regulate which of the V0Qs is serviced. Among eligible VOQs, it is possible to use any algorithm for cue selection.

These two service disciplines can be used to support quality of service (QoS) in packet networks, and are an active research field. This QoS support strategy is often of non-cooperative type, because it guarantees the expected VOQ service behavior regardless of other traffic streams. Algorithms in this class can be used in switches that support strict QoS applications, such as video and voice streams.

The cooperative VOQ selection strategy is a selection strategy in which V0Q selection depends on the state of the entire VOQ set in the switch. This strategy is generally aimed at better overall switch behavior, such as maximum throughput, rather than focusing on the services of each flow. Thus, using such a strategy as a switch is a case of supporting data traffic without promises of QoS requirements.

In the case of collaborative strategies, it is necessary to provide additional information, such as the status of other VOQs, to the CORPS scheduler. Since information about the state of the queue is always "old", the service strategy must be fast with respect to old information.

The maximum matching problem is the problem of finding a subset of the sides of a given graph with the opposite sides of the graph's vertices (Cormen, Leiserson and Rivest, 'Introduction to Algorithms', McGraw-IIill). , 1990,). However, it is impossible for any vertex to have several selected sides connecting it. In order to maximize the number of packets exchanged in all slots, it is necessary to solve the problem of Maximun Bipartite Matching (MBM) (RE Tarjan, 'Data Structures and Network Algorithms', Society for Industrial and Applied Mathematics, See Pennsylvania, Nov. 1983). Algorithms for solving MBM with reasonable computations are available (JE Hopcreft.RM Karp, 'An n ^5/2 Algorithm for Maximum Matching in Bipartite Graphs', Society for Industrial and Applied Mathematics J. Comput., 2 (1973) .PP .225-231). In the present invention, status information of whether the VOQ is empty is sent through the communication chain and passed to the VOQM. Here, the MBM algorithm determines which queue serves the slot of the next frame. Interestingly, according to CORPS, queues that are not selected by the MBM algorithm can attempt future reservations.

The Maximum Weight Biparilie Matching (MWBM) problem is similar to the MBM problem above. The main difference is that in the former, the weight is related to the cue of the graph, and the purpose is to find a set of sides that maximizes the sum of the weights of the matching sides. Other researchers have shown that using the MWBM algorithm results in better performance than MBM strategy for throughput under uneven traffic (N. McKeown. V. Anantharam. J. Walrand, 'Achieving 100% Throughput in an Input-Queued Switch'.Proceedings of Infocom 96.San Francisco, March 1996,). The idea is to use the VOQ queue size as the weight to handle the traffic case inconsistently.

Further, according to the above document, as long as input traffic can be accepted, the MWBM algorithm is stable. That is, the V0Q queue does not explode. For all output ports, traffic is acceptable if the sum of the input traffic rates to one output port does not exceed its capacity. This interesting result is that the stability of the MWBN is maintained even in the presence of outdated information, ie even if the weight is based on the cue level of some past time slot. Also in this case, the queue level information of VOQ is passed to all VOQMs, and the MWBM algorithm can be executed in each module before a request for an output port is issued to the SM.

As described in detail above, the carryover round robin pipeline scheduler (CORPS) according to the present invention enables fair scheduling between the winning positions of the crossbar high speed switch fabric. CORPS makes one scheduling decision per slot per line by scheduling future slot packets. Since the choice of queue to be scheduled is arbitrary, it is suitable for supporting the quality of service of traffic. CORPS evenly resolves contention between output ports.

Moreover, it is easy for a person skilled in the art to consider other effects and modifications, and the present invention is not limited to the embodiments described herein. Various modifications can be considered without departing from the structural technical idea or technical scope of the present invention described in the claims.

Claims (11)

In a switch that controls the flow of data in a network, Multiple input ports, Multiple output ports, A scheduler having a plurality of input port scheduling modules for scheduling a specific input port of the plurality of input ports to send data to a designated output port of the plurality of output ports, The current schedule module is Receive scheduling messages from the previous scheduling module, Calculate a future time slot for the current schedule module to access the specified output port, Based on whether the future time slot is already reserved by the current schedule module, whether the future time slot is blocked, and whether the future time slot is taken by another schedule module. Determining whether the future time slot is valid, If it is valid, the future time slot is taken and information indicating that the future time slot is taken is input to the scheduling message. The data flow according to claim 1, wherein the scheduler advances the future time slot by a predetermined number of time slots at any one of the case where the future time slot is reserved or taken. Control switch. The data flow control switch of claim 1, wherein the data input through the plurality of input ports is queued using virtual output queuing (VOQ) that maintains a separate queue for each of the plurality of output ports. . 4. The data flow control switch of claim 3, wherein the virtual output queuing for one port is independent of the virtual output queuing for another port. 4. The data flow control switch of claim 3, wherein the service rate of the virtual output queuing is predictable and adjustable. The data flow control switch of claim 1, wherein the scheduler selects the designated output port based on a weighted round robin. A method for scheduling input signals arriving at various input ports of a switch having a plurality of input port scheduling modules to be sent to various output ports of the corresponding switch. a) the current schedule module receiving a scheduling message from a previous schedule module, b) the current schedule module calculating a future time slot to attempt to access one of the plurality of output ports; c) selecting one of the plurality of output ports to schedule for transmission in the future time slot; d) determining whether the future time slot is already reserved by the current schedule module; e) determining whether or not the future time slot is blocked when the future time slot is not reserved by the current schedule module; f) if the future time slot is not blocked, determining whether the future time slot has already been taken by another scheduling module; g) whether the carryover operation has already begun from the scheduling message, in which case the future time slot has already been taken by another scheduling module or has already been reserved by the current scheduling module. Judging step, h) if the carryover operation has already been initiated, returning to the step (d) by setting the future time slot to a blocked state; i) if the carryover operation is not started, advancing the future time slot by a predetermined number of time slots, setting a carry forward flag, and returning to step d; j) if the future time slot is not taken by another scheduling module, taking the future time slot and inputting information into the scheduling message indicating that the future time slot was taken; k) a step of passing said scheduling message to a next schedule module. 8. The method of claim 7, wherein data input through the plurality of input ports is queued using virtual output queuing that maintains a separate queue for each output port. 9. The method of claim 8, wherein the virtual output queuing for one port is independent of the virtual output queuing for another port. 9. The method of claim 8, wherein the service rate of the virtual output queuing is predictable and adjustable. 8. The method of claim 7, wherein the scheduler selects the designated output port based on a weighted round robin.