KR100305099B1 - Single-chip system having electrostatic discharge (esd) protective circuitry - Google Patents

Abstract

In order to effectively protect the system from static electricity and electrostatic discharge (ESD) and to prevent defects in the system, the system formed on the first conductivity type semiconductor substrate includes a pad for receiving signals, a protective element connected to the pad, And a discharge line connected to the protection element. The protection element has a single bipolar transistor portion and at least one diode portion adjacent the bipolar transistor portion.

Description

Single-chip system with electrostatic discharge (ESD) protection circuits {SINGLE-CHIP SYSTEM HAVING ELECTROSTATIC DISCHARGE (ESD) PROTECTIVE CIRCUITRY}

FIELD OF THE INVENTION The present invention relates generally to single chip systems (e.g. CPUs, DRAMs), and more particularly to systems having circuitry for protecting the system from static electricity (i.e. electrostatic discharge) and for protecting internal circuits from electrostatic failure. .

With recent developments in manufacturing single chip semiconductor systems (such as CPUs and DRAMs), single chip semiconductor systems have been highly integrated and the chip size of the systems has become smaller and smaller. Thus, for example, a metal oxide semiconductor (MOS) transistor or diode formed in a single chip semiconductor system has a low breakdown voltage. Thus, MOS transistors and diodes of a single chip semiconductor system are easily destroyed when static electricity is generated in the single chip semiconductor system.

In order to protect the system from static electricity, the conventional single-chip semiconductor systems in Japanese Patent Laid-Open Nos. 3-91264 and 319480/96 and Japanese Patent Laid-Open No. 7-86510 provide a system for protecting the system from static electricity, electrostatic discharge (ESD) and breakdown. It has a static electricity protector which is a circuit.

1 is shown in Japanese Patent Laid-Open No. 7-86510 including a plurality of metal pads 11, a metal line 12 (e.g., aluminum), a plurality of parasitic bipolar transistors 13, and a plurality of diodes 14. The electrostatic protector described is shown. The collector of the parasitic bipolar transistor 13 is connected to the metal pad 11, the emitter of the parasitic bipolar transistor 13 is connected to the metal line 12, and the base of the parasitic bipolar transistor 13 is connected to the emitter. do. The P-type region of the diode 14 is connected to the metal pad 11 and the N-type region of the diode 14 is connected to the metal line 12.

Therefore, even if a significantly high voltage caused by static electricity is applied between any two metal pads of the plurality of metal pads 11, since the static electricity is discharged by the voltage clamping effect, the interior connected to the metal pads 11 The circuit (not shown in FIG. 1) is not broken. In particular, the voltage clamping effect uses the parasitic bipolar transistor 13 and the diode 14 to discharge the static electricity on one metal pad 11 to the other metal pad 11.

As noted above, the single chip system with the electrostatic protector circuit structure of FIG. 1 ideally operates stably and accurately.

In practice, however, the electrostatic protector of FIG. 1 does not work properly when it has the structure and layout as in FIG.

FIG. 2 shows an exemplary diagram of the electrostatic protector of FIG. 1 as a related art system (not prior art system). In FIG. 2, the metal pad 11 has a ladder portion 15 having a plurality of fingers. The metal line 12 also has fingers for forming the parasitic bipolar transistor 13 and the diode 14. In Figure 2, P ⁺ impurity diffusion region in the P-type silicon substrate (18 ₁ -18 ₃₎ and the N ⁺ impurity diffusion region (17 ₁ -17 ₆₎ of three diode parts (14a, 14b, 14c) consisting of and There are two bipolar transistor portions 13a and 13b. The contact hole 16 is used to connect the metal pad 11 or the metal line 12 to one of the impurity diffusion regions.

When a significantly high amount of voltage is applied to the metal pad 11, breakdown occurs in any one of the N ⁺ impurity diffusion regions 17 ₁ , 17 ₂ , 17 ₃ , 17 ₄ , connected to the metal pad 11. do. For example, a breakdown occurs at one point A of the N ⁺ impurity diffusion region 17 ₁ of FIG. 2.

Since current flows to the P-type semiconductor substrate, the voltage of the P-type semiconductor substrate at the point A increases.

Therefore, the junction between the N ⁺ impurity diffusion region 17 ₂ and the P-type semiconductor substrate is biased in the forward direction. At this time, a current flows into the metal line 12 and operates as a ground current. As a result, bipolar operation of the parasitic bipolar transistor is initiated at point A.

The bipolar operation then initiates another bipolar operation near point A, similar to the geometric progression (ie, chain reaction). Accordingly, bipolar operation eventually occurs in the entire region 13a.

However, an increase in the voltage level in the entire region 13a does not increase the voltage level in the region 13b, because P ⁺ impurity diffusion region 18 ₂ is between the region 13a and the region 13b. Because it is formed on. Thus, since only half of the structure portion acts as a transistor, the electrostatic protector of FIG. 2 does not operate at its maximum performance.

The performance of the voltage clamp is reduced and the bipolar transistor 13 is destroyed. In particular, if the bipolar operating area is narrow, the resistance of the current path in the electrostatic protector increases. As a result, the voltage clamp protection performance is lowered and the current density passing through the bipolar transistor 13 is increased. Therefore, the junction lowering is induced, and ultimately, the bipolar transistor 13 is destroyed.

Thus, as mentioned above, conventional single-chip semiconductor systems are not effectively protected from static electricity. This is the problem.

In view of the above and other problems with conventional systems, it is an object of the present invention to provide an improved single chip semiconductor system.

It is another object of the present invention to provide an improved electrostatic protector for a single chip semiconductor system.

In a first aspect, a system formed on a first conductivity type semiconductor substrate according to the present invention includes a pad for receiving a signal, an internal circuit connected to the pad, a discharge line, and an electrostatic protector connected to the pad and the discharge line. Wherein the electrostatic protector includes a single bipolar transistor portion and one or more diode portions adjacent to the bipolar transistor portion.

In a unique and non-obvious structure of the present invention, the electrostatic protector includes a single bipolar transistor portion and one or more diode portions adjacent to the bipolar transistor portion. Therefore, when electrostatic breakdown occurs, bipolar operation occurs everywhere in the bipolar transistor portion. As a result, the system according to the invention is effectively and strongly protected compared to the conventional system described above.

1 is a circuit diagram of an electrostatic protector in a conventional single chip system.

2 is a detailed circuit diagram of an electrostatic protector in a single chip system of the related art (not related art but related art).

3 is a diagram of a single chip semiconductor DRAM system in accordance with the present invention.

4 is a detailed circuit diagram of an electrostatic protector in a single chip semiconductor DRAM system according to the present invention.

5 is a circuit diagram of a cross section of an electrostatic protector according to the present invention;

6 is a detailed diagram of a diffusion region in accordance with the present invention.

FIG. 7 is a cross-sectional view of the device structure taken along the line VII-VII 'in FIG. 6; FIG.

※ Explanation of code for main part of drawing

22 ₁ to 22 ₇ : N ⁺ impurity diffusion region 23 ₁ to 23 ₄ : P ⁺ impurity diffusion region

24: bipolar transistor portion 25a, 25b: diode portion

26: metal pad 29 ₁ ~ 29 ₆ : internal contact hole

30 ₁ ~ 30 ₆ : Contact hole 50: Static electricity protector

51: discharge line

The above and other objects, features and advantages will be better understood from the following detailed description of preferred embodiments of the invention with reference to the drawings.

Hereinafter, a single chip semiconductor DRAM memory system 60 according to an embodiment of the present invention will be described with reference to the drawings.

In this embodiment, the DRAM system 60 includes a discharge line 51 for discharging static electricity, a plurality of electrostatic protectors 50 connected to the discharge line 51, and a metal pad connected to the electrostatic protector 50. 26a-26d, a row decoder 52, a column decoder 53, a plurality of bitlines (not shown) and wordlines (not shown) and a Sands amplifier (not shown) And a cell array (that is, DRAM cell array) 54 and an input / output circuit 55.

The metal pads 26a-26d are respectively connected to corresponding leads (ie, metal wirings) (not shown), and the DRAM system 60 is molded using a resin.

For example, in FIG. 3, the metal pad 26a is used to receive the ground voltage (0 V), the metal pad 26b is used to receive the high voltage (Vcc> 0 V), and the metal pad 26c. Is used to receive an address signal, and the metal pad 26d is used to input or output data. The row decoder 52, the column decoder 53, the DRAM cell array 54, and the input / output circuit 55 receive the ground voltage and the high voltage Vcc by the read operation and the write operation.

When the read operation is executed by the off-chip CPU, the row decoder 52 reads the address signal and activates the corresponding word line. The column decoder 53 decodes the address signal and selects the corresponding bit line. The sense amplifier then amplifies the data from the DRAM cells connected to the corresponding word line and bit line. This data is output to the metal pad 26d.

When the write operation is executed by the off-chip CPU, the row decoder 52 reads out the address signal and activates the corresponding word line. The column decoder 53 decodes the address signal and selects the corresponding bit line. Then, the data from the metal pad 26d is stored in the DRAM cell.

4 shows the electrostatic protector 50 according to the present invention in detail. In FIG. 4, the metal pads 26 represent one of the metal pads 26a-26d.

The metal pad 26 has a ladder portion 28 having a plurality of fingers. The discharge line 51 also has a substantially ladder shape having a plurality of fingers to form a diode having a circuit connection shown in FIG. 1 and a parasitic bipolar transistor. In Figure 4, N ⁺ impurity diffusion region (22 ₁ -22 ₇₎ and a P ⁺ impurity diffusion region of a parasitic bipolar transistor part (24) composed of a (23 ₁ -23 ₄₎ in the P-type silicon substrate 21 and the There are two diode portions 25a and 25b. N ⁺ impurity diffusion region (22 ₁ -22 ₇₎ and a P ⁺ impurity diffusion region (23 ₁ -23 ₄₎ substantially has a rectangular shape, the longer side of the rectangle is the preferred length is about 50 ㎛. The contact hole 30 is used to connect the metal pad 26 or the discharge line 51 to one of the impurity diffusion regions.

5 is a circuit diagram for showing the relationship between the N ⁺ impurity diffusion region (22 ₁ -22 ₇₎ and a P ⁺ impurity diffusion region (23 ₁ -23 _4). The middle portion of the electrostatic protector 50 has no diode portion, and the diode portion is located on the side of the electrostatic protector 50.

FIG. 6 shows a cross section of the N ⁺ impurity diffusion layers 22 ₃ , 22 ₄ shown in FIG. 5. (Described in FIG. 4 with reference number 30) there are contact holes (30 ₁ -30 _6). Furthermore, the inner contact hole (29 ₁ -29 _6).

N ⁺ four corners of the impurity diffusion layer (22 _3, 22 ₄₎ is gajyeoseo an obtuse angle, the first and the second diffusion layer (22 _3, 22 _4), each of the corner becomes dull with the country or linear. Of the N ⁺ impurity diffusion layers (22, ₄₎ from a corner (31) N ⁺ impurity diffusion layer (22 ₄₎ having a corner (32) the distance (d ₁₎ has a corner (31) up to from inside the contact holes (29, ₄₎ the distance (d ₂₎ ranging from the side portion 33 is longer than (i.e., a line indicating the substantially perpendicular distance (d ₂₎ in the plane formed by the one side of the contact hole (29, _4)).

Furthermore, inside the contact hole (29 ₁ -29 ₃₎ it is formed so as to face inside the contact holes (29 ₄ -29 _6), and contact holes (30 ₄ -30 ₃₎ has contact holes (30 ₄ -30 ₆₎ and It is formed to face. That is, the distance from the contact hole 30 ₁ to the contact hole 30 ₄ and the distance from the contact hole 30 ₂ to the contact hole 30 ₄ are the same (that is, equidistant). Similarly, the distance from the contact hole 30 ₂ to the contact hole 30 ₅ and the distance from the contact hole 30 ₃ to the contact hole 30 ₅ are also the same.

The distance is equal to up to inside the contact hole (29 ₁₎ inside the contact holes (29, ₄₎ inside the contact holes and the distance (29, ₅₎ inside the contact hole (29 ₁₎ from up to from. Similarly, the same degree distance from the inside contact holes (29, ₆₎ from the inside of the contact hole (29 ₂₎ inside the contact holes (29, ₅₎ and a distance inside the contact hole (29 ₂₎ ranging from.

N ⁺ discharged via the impurity diffusion layer (22 ₃₎ is inside the contact hole (29 ₁ -29 _3), the intermediate conductive layer (34 ₁₎ is connected to a further intermediate conductive layer and the contact hole (30 ₁ -30 ₃₎ via line (51). N ⁺ impurity diffusion region (22, ₄₎ inside the contact holes (29 ₄ -29 ₆₎ it is connected to a middle conductive layer (34 ₂₎ via a further intermediate conductive layer (34 ₂₎ and contact holes (30 ₄ -30 ₆ Is connected to the ladder part 28 through ().

FIG. 7 shows a cross-sectional view taken along line VII-VII 'of FIG. 6 to show the device structure. An intermediate conductive layer (34 ₁ -34 ₂₎ is formed using a metal having at least one high melting point, a silicide, polysilicon or a nested. N ⁺ impurity diffusion layers (22, ₄₎ the deep N ⁺ impurity diffusion layer (35) than a, N ⁺ impurity diffusion layers (22, _4), a contact hole (29 ₄ -29 ₆₎ P-type semiconductor substrate (21 corresponding to a position below ) Is formed on. N ⁺ impurity diffusion layer 35 is formed by implanting impurities after the opening inside the contact holes (29 ₄ -29 _6).

When a positive (i.e., "+") significant voltage is applied to the pad 26, breakdown occurs in any of the N ⁺ impurity diffusion layers 22 ₁ , 22 ₃ , 22 ₄ , 22 ₆ , 22 ₇ . do. For example, in this description, breakdown occurs at the point A of the N ⁺ impurity diffusion layer 22 _{2 in} FIG. 4.

At this time, current flows to the P-type semiconductor substrate 21, and the voltage of the P-type semiconductor substrate 21 at the point A 'increases. Therefore, the bonding between the N ⁺ impurity diffusion layer (22 ₃₎ and a P-type semiconductor substrate 21 is biased in the forward direction. As a result, current flows into the discharge line 51. This current acts as the ground current. As a result, bipolar operation of the parasitic bipolar transistor is initiated at the point A '.

At this time, the bipolar operation causes another bipolar operation near the point A '. Thus, finally, bipolar operation occurs throughout the entire area 24. Experiments show that the propagation speed of bipolar operation takes about 40 Hz to propagate 100 μm.

As mentioned above, according to the embodiment of the present invention, since the parasitic bipolar transistor portion 24 is not divided into two parts by the P ⁺ impurity diffusion region, the parasitic bipolar transistor portion 24 effectively operates as a parasitic bipolar transistor. do. Thus, the transistor portion is larger and centrally located.

Furthermore, each of the four corners of the N ⁺ impurity diffused layer (22 ₁ -22 ₇₎ is non-rectangular (substantially forming a right angle with) as in conventional systems, and has a obtuse angle. Thus, if N ⁺ in a corner of the impurity diffusion layers (22 ₁ -22 ₇₎ junction breakdown occurs, because the concentration of the excess current occurs, and minimizes the damage.

Junction breakdown may occur in the four corners of the N ⁺ impurity diffusion region (22 ₁ -22 _7). However, since the distance (d ₁₎ is longer than the distance (d _2), the current density is suppressed by the resistance of the N ⁺ impurity diffused layer (22 ₁ -22 ₇₎ itself.

Furthermore, as in the conventional arrangement, N ⁺ impurity diffusion layer (22 ₃₎ inside the contact hole (29 ₁ -29 ₃₎ of the facing and the internal contact hole (29 ₄ -29 ₆₎ of the N ⁺ impurity diffusion layers (22, ₄₎ It is not located. Instead, the contacts are offset from each other. Thus, for example, the current path from inside the contact hole (29 ₁₎ from the inside of the contact hole (29, ₄₎ is, compared to the current path in the case where such a contact hole situated facing each other, becomes relatively longer. Therefore, the resistance is large. Accordingly, N ⁺ the resistance caused by the impurity diffusion layers (22 ₁ -22 ₇₎ to reduce the current.

In addition, the N ⁺ impurity diffusion layer 35 is deeper than the N ⁺ impurity diffusion layer 22. Therefore, the junction breakdown under the contact holes 29 _{1-2 9 6} is prevented.

In fact, in the area of 50 × 50 μ㎡, five N ⁺ impurity diffusion layer having a length of 50 ㎛ respectively (22 ₂ -22 ₆₎ are arranged in parallel. Therefore, the parasitic bipolar transistor portion 24 operates as less than 20 kW as a parasitic bipolar transistor. Preferably, the length of the N ⁺ impurity diffusion layer 22 is less than 100 m and the area of the parasitic bipolar transistor portion 24 is less than 100 x 100 m 2.

Further, impurity diffusion layers 22 and 23 are formed in parallel along the direction from the metal pads 26 to the discharge lines 51. Thus, the current path is minimized.

In the above description, the total number of N ⁺ impurity diffusion layers 22 in the parasitic bipolar transistor portion 24 is five. However, the present invention is not limited to these five types, and three or more odd numbers may be used. In addition, the shapes of the contact holes 29 and 30 can also be freely determined.

In the above embodiment, although the P-type semiconductor substrate 21 is used, the same structure can be provided by using the N-type semiconductor substrate according to the present invention. Similarly, parasitic bipolar transistors of the PNP type may be provided.

Although the present invention has been described through preferred embodiments, it will be apparent to those skilled in the art that the present invention may be practiced with modification within the scope and spirit of the appended claims.

As described above, according to the present invention, by providing an improved electrostatic protector in a single-chip semiconductor system, there is an effect that can effectively protect the internal circuit from static electricity.

Claims (17)

Pads for receiving signals, A protective element connected to the pad, A discharge line connected to said protective element, The protection element comprises a single bipolar transistor portion and at least one diode portion adjacent the bipolar transistor portion, The substrate includes a first conductive semiconductor substrate, The bipolar transistor unit A plurality of first diffusion regions formed in the substrate in a second conductivity type and connected to the pads, and A plurality of second diffusion regions formed in the substrate with the second conductivity type and connected to the discharge lines; Wherein each of the first diffusion regions is adjacent to the second diffusion region, and end portions of the first and second diffusion regions are formed to have an angle of 90 degrees or more. Pads for receiving signals, A protective element connected to the pad, A discharge line connected to said protective element, The protection element comprises a single bipolar transistor portion and at least one diode portion adjacent the bipolar transistor portion, The substrate includes a first conductive semiconductor substrate, The bipolar transistor unit A plurality of first diffusion regions formed in the substrate in a second conductivity type and connected to the pads, and A plurality of second diffusion regions formed in the substrate with the second conductivity type and connected to the discharge lines; Each of the first diffusion regions is adjacent to the second diffusion region, The first diffusion region and the second diffusion region have a rectangular shape, the first diffusion region and the second diffusion region are located parallel to each other, And the corners of the first and second diffusion regions of the rectangular shape have an obtuse angle. The method of claim 2, And a first contact hole for electrically connecting the first diffusion region to the pad and a second and third contact hole for connecting the second diffusion region to the discharge line. . The method of claim 3, wherein The distance from the first contact hole to the second contact hole and the distance from the first contact hole to the third contact hole is the same. The method of claim 3, wherein And the second contact hole is offset from the first and third contact holes. The method of claim 4, wherein Wherein said substrate has a plurality of third diffusion regions under said first, second and third contact holes having said second conductivity type and having a depth deeper than said first and second diffusion regions. Chip system. The method of claim 6, Wherein said first conductivity type comprises a P type and said second conductivity type comprises an N type. The method of claim 7, wherein Wherein said single chip system further comprises an internal circuit connected to said pad, said internal circuit including a plurality of DRAM cells, and said protective element having an electrostatic discharge protector. An electrostatic discharge (ESD) protection circuit formed on a substrate to protect a semiconductor device, A single bipolar transistor unit; And At least one diode unit adjacent to the bipolar transistor unit, The semiconductor device includes a pad and a discharge line connected to the protection circuit, and the substrate includes a first conductive semiconductor substrate. The plurality of bipolar transistor portions formed in the substrate in a second conductivity type and connected to the pad, and a plurality of second diffusion regions formed in the substrate in the second conductivity type and connected to the discharge line. And Each of the first diffusion regions is located adjacent to the second diffusion region, An end portion of the first and second diffusion regions is formed on the substrate to protect the semiconductor device, characterized in that formed at an angle substantially 90 degrees or more. An electrostatic discharge (ESD) protection circuit formed on a substrate to protect a semiconductor device, A single bipolar transistor unit; And At least one diode unit adjacent to the bipolar transistor unit, The semiconductor device includes a pad and a discharge line connected to the protection circuit, and the substrate includes a first conductive semiconductor substrate. The plurality of bipolar transistor portions formed in the substrate in a second conductivity type and connected to the pad, and a plurality of second diffusion regions formed in the substrate in the second conductivity type and connected to the discharge line. And Each of the first diffusion regions is located adjacent to the second diffusion region, Each of the first and second diffusion regions has a rectangular shape, The first and second diffusion regions are located parallel to each other, Electrostatic discharge (ESD) protection circuit, characterized in that the rectangular corner has an obtuse angle. The method of claim 10, And a first contact hole for electrically connecting the first diffusion region to the pad and a second and third contact hole for connecting the second diffusion region to the discharge line. ESD protection circuit. The method of claim 11, The distance from the first contact hole to the second contact hole and the distance from the first contact hole to the third contact hole are the same. The method of claim 12, Wherein the substrate has a plurality of third diffusion regions under the first, second and third contact holes and having a second conductivity type and having a depth deeper than the first and second diffusion regions. Discharge (ESD) protection circuit. The method of claim 13, Wherein the first conductivity type comprises a P type and the second conductivity type comprises an N type. A semiconductor device having an electrostatic discharge protection circuit connected between a pad and a discharge line, A first diffusion region having a first conductivity type and connected to said discharge line, and a second diffusion region having a second conductivity type and connected to said pad, said first diffusion region being adjacent to said second diffusion region A diode unit; And A fifth diffusion region having the second conductivity type and connected to the discharge line, a fourth diffusion region having the second conductivity type and connected to the pad, and a fifth diffusion region having the second conductivity type and connected to the discharge line A bipolar transistor unit having a diffusion region, And the first, second, third, fourth, and fifth diffusion regions are sequentially formed in the first conductive semiconductor layer. A semiconductor device having an electrostatic discharge protection circuit connected between a pad and a discharge line, A first diffusion region having a first conductivity type and connected to said discharge line, and a second diffusion region having a second conductivity type and connected to said pad, said first diffusion region being adjacent to said second diffusion region A diode unit; And A fifth diffusion region having the second conductivity type and connected to the discharge line, a fourth diffusion region having the second conductivity type and connected to the pad, and a fifth diffusion region having the second conductivity type and connected to the discharge line A bipolar transistor unit having a diffusion region, And the second, first, third, fourth, and fifth diffusion regions are sequentially formed in the first conductive semiconductor layer. A semiconductor device having an electrostatic discharge protection circuit connected between a pad and a discharge line, A first diffusion region having a first conductivity type and connected to said discharge line, and a second diffusion region having a second conductivity type and connected to said pad, said first diffusion region being adjacent to said second diffusion region A diode unit; And A fifth diffusion region having the second conductivity type and connected to the discharge line, a fourth diffusion region having the second conductivity type and connected to the pad, and a fifth diffusion type having the second conductivity type and connected to the discharge line A bipolar transistor unit having a diffusion region, The diode unit further includes a sixth diffusion region having the first conductivity type and connected to the discharge line. And the sixth, second, first, third, fourth, and fifth diffusion regions are sequentially formed in the first conductive semiconductor layer.

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