KR100304942B1 - Device for sending/receiving data between board in communication device and Method for sending/receiving data using the same - Google Patents

Abstract

The present invention relates to a board-to-board data transmission / reception apparatus and a data transmission / reception method using the same of a communication apparatus capable of improving data transmission / reception efficiency by reducing unnecessary waiting time during data transmission / reception between base station boards. The board-to-board data transmission / reception device of such a communication device is a device in which a plurality of slave boards having different addresses are connected to a shared global bus. While transmitting data using the global bus to any one or more of the master board or other subordinate boards, signals that data to be newly transmitted from any one or more of the boards to any one or more other boards has occurred. The global bus controller is configured to control the OWN_REQ signal for transmission to the master board. Therefore, data transfer efficiency between boards can be improved.

Description

Device for sending / receiving data between boards in communication device and method for sending / receiving data using the same}

The present invention relates to board-to-board data transmission / reception of a communication device. In particular, when transmitting / receiving data between a plurality of boards constituting a base station device, the board-to-board communication device is adapted to increase transmission / reception efficiency by reducing unnecessary waiting time due to sequence control. The present invention relates to a data transmission and reception apparatus and a data transmission and reception method using the same.

A code division multiple access (CDMA) base station apparatus is composed of a plurality of boards.

These boards provide call control and call resource management and status management, enhanced control processor circuit board assembly (ECPA) for alarm management, BTS alarm collection & maintenance board assembly (BAMA) for alarm detection, and system clock. BTS Timing Management Circuit Board Assembly (BTMA), Enhanced Network Interface Circuit Board Assembly (ENIA) providing base station network functionality, Multi-Channel Processing board Assembly 20 (MCPA) with CDMA digital signal processing, radio frequency (RF) devices RCPA (Radio & Channel Processing board Assembly) with control function, Base station sector conversion & Up / Down converter Assembly (L) with frequency conversion function of transmit / receive signal, PACA (Power Adjust & Control) with transmit output monitoring function Assembly-EL), High Power Amplifier Unit (HPAU) with transmit signal amplification, BADA (Base with base station transmit / receive antenna VSWR measurement) About 100 boards are configured in one base station, such as the Station Analyze & Diagnostic Assembly (L) and the High Power Amplifier Unit (HPAU) with signal amplification.

These boards are connected with 31 slave boards and one master board to exchange data between boards. Such data includes program data, signal data, and downloading data necessary for operation on a board, and such boards exchange data through a data bus.

Hereinafter, a board-to-board data transmission / reception method of a conventional base station apparatus will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a connection state of boards of a conventional base station apparatus.

The connection state of the boards of the conventional base station apparatus includes a master board unit 50 for generating a frame synchronization signal and a reference clock signal, and first to thirty-first slave boards that together with the master board 50 form a base station of a mobile communication system. In the subordinate board part 40 which consists of (1-31), it shows that the master board part 50 and the 1st-31st subordinate boards 1-31 are connected by the shared global bus.

The global bus includes a frame synchronization signal (FRS) bus and an assert clock (ASTCLK) for generating a frame synchronization signal and a reference clock required for the operation of the first to thirty-first slave boards 1 to 31. Assertion that transmits a signal bus and a signal for occupying the data bus to the master board unit 50 when its order comes from the first to thirty-first slave board units 1 to 31 according to the frame synchronization signal ( Assert: AST signal bus, a bit rate clock signal (BRCLK) bus for indicating the bit rate (bit rate) of the data to be transmitted, and a data bus (DATA) for transmitting data.

The master board unit 50 and the first to thirty-first slave boards 1 to 31 may each include a field programmable gate array 50b for controlling a global bus, and A first to thirty-first slave FPGAs 1b to 31b and an input / output unit 50c connected to a serial bus to transmit and receive data to and from the master board unit 50 or the first to thirty-first slave boards 1 to 31; Central processing unit (CPU) 50a for controlling the first to thirty-first slave input / output units 1c to 31c, the driver unit 50d, the first to thirty-first slave driver units 1d to 31d, and the master board unit 50. And first to thirty-first slave central processing units 1a to 31a which control the first to thirty-first slave board units 1 to 31.

Here, the master board unit 50 and the first to thirty-first slave boards 1 to 31 have respective addresses, and the master board 50 and the first to thirty-first slave boards 1 to 31 according to respective addresses. 31) has a certain transmission order.

FIG. 2 is a detailed configuration diagram of slave boards among the boards of the base station apparatus shown in FIG. 1.

The detailed configuration of the slave board of the conventional base station apparatus will be described taking the first slave board 1 as an example.

The slave FPGA 1b compares the frame synchronization signal FRS, the assert clock signal ASTCLK, and its own board IDs ID 0 to 4 with the master board 50 to determine the order in which it transmits data. Decide

When there is data to be transmitted, the slave input / output unit 1c asserts the RTS signal low to request data transmission. When the slave FPGA Ib is ready to transmit, the slave input / output unit 1c The furnace asserts the CTS signal low to permit transmission, and supplies the slave drive unit 1d with TX_BRCLK for data transmission. It also asserts an AST signal to notify other slave boards that it is transmitting data, while the other boards receive data addresses in High Level Data Link Control Pressure (HDLC) format that is matched to RX_BRCLK. The area is compared with its address to receive the data sent to it.

3 is a detailed block diagram of a programmable gate array (FPGA) of the slave board shown in FIG.

The slave FPGA 1b receives a frame synchronizing signal FRS, an assert clock signal ASTCLK, a receiving assert signal RX_AST, and a counter 1ba, which is a state machine that determines an order for data transmission, and a slave input / output unit ( And a logic section 1bb for generating a signal for data transmission in accordance with the IDs (IDs 0 to 4) and the output of the RTS signal from 1c and the counter 1ba.

4 is a timing diagram illustrating board-to-board data transmission of the base station apparatus shown in FIG. 1.

The master board unit 50 and the first to thirty-first slave boards 1 to 31 operate in synchronization with the frame synchronizing signal Frs and the assert clock signal Astclk. Each of the CPUs 50a and 1a to 31a of the slave boards 1 to 31 refers to its own address in the data signal to determine whether it is data to be received or not to receive data.

Then, when the master board section 50 and the first to thirty-first slave boards 1 to 31 transmit their own addresses according to their own addresses defined by 5-bit transmission numbers 0 to 31, it is determined. In a round-robin manner, data generated from each transmission board is sequentially transmitted to one or more receiving boards.

That is, as shown in Fig. 4, when the frame synchronizing signal FRS becomes high, the assert clock signal ASTCLK also operates, and the transmission number 0 is the board (for example, the master board unit 50). Starts transmitting to the other board. At this time, if there is data to be transmitted, the assert signal AST is activated low and then data is transmitted. However, when there is no data to transmit, the board having the transmission number 1 (for example, the first slave board 1) is in turn to transmit at the next rising edge of the assert clock signal ASTCLK. This transmission operation continues to the board having the transmission number 31 (for example, the 31st slave board 31).

In this way, when one board wants to send data to another board, it waits until its turn comes and then activates the assert signal AST on the rising edge of the assert clock signal ASTCLK when its turn comes. It notifies that there is data to be transmitted to another board, and transmits data in the format of high level data link control pressure (hereinafter abbreviated as HDLC) according to the bit rate clock signal (BRCLK). At this time, the bit rate clock BRCLK uses 2M or 4M, and the board transmitting the data also supplies the bit rate clock signal BRCLK together with the data.

One or more receiving boards receive data according to the bit rate clock signal BRCLK generated by the transmitting board, and compare the address included in the data of the HDLC format with its own to receive the data in the same case.

In addition, the board transmitting the data transmits all the data to be transmitted and then deactivates the assert signal, so that the board having the next transmission number has a transmission authority. Subsequently, as described above, when there is no data to be transmitted by the board having the next transmission number, data transmission proceeds in a round robin manner in which the board having the next transmission number has a transmission authority.

In the conventional data transmission / reception method of a plurality of boards connected by a serial bus, a round robin method using a serial bus is used to transmit data from one board to another board. In the data transmission / reception using the round robin method, after data is transmitted once, at least 31 clocks of the assert clock (ASTCLK) are consumed according to the order control, and thus the right to transmit the next data is obtained. There is a problem that data transmission is not efficient because the user waits for a predetermined time until order comes next time.

An object of the present invention has been made in view of the above-mentioned problems of the prior art, the board-to-board data transmission and reception apparatus of the communication device that can increase the data transmission and reception efficiency by reducing unnecessary waiting time according to the order control and data transmission and reception method using the same It is to provide.

According to a feature of the present invention for achieving the above object, in a device in which a plurality of slave boards having a different address with one master board is connected to a shared global bus, the master board or a plurality of slave boards Data to be newly transmitted from any one or more of the boards to any one or more other boards is generated while data is being transmitted from any one board to any one or more of the master board or other dependent boards using the global bus. A global bus controller is configured to control an OWN_REQ signal to transmit a signal to the master board.

In addition, according to another feature of the present invention for achieving the above object, in the board-to-board data transmission and reception method of the device consisting of a plurality of slave boards having a different address and one master board, the master board or multiple A first step of transmitting data from any one of the slave board of the master board or one or more of the other dependent boards, any one or more of the other boards except the board that is transmitting the data while the data is being transmitted A second step of transmitting a signal indicating that data to be newly transmitted has been generated to the master board when data to be newly transmitted from the board is generated; The third step of waiting in sequence, the first step When the transfer is the end of the data it takes place in response to the standby procedure as Step 4 of the board are to transmit new data in a certain order in one or more of the master or slave board Board.

According to the present invention as described above, there is an advantage that the transmission efficiency is improved when transmitting data from each board to another board when transmitting data between the master board and each slave board of the base station.

1 is a block diagram showing a connection state of boards of a conventional base station apparatus

FIG. 2 is a detailed configuration diagram of slave boards among the boards of the base station apparatus shown in FIG.

3 is a detailed block diagram of a programmable gate array (FPGA) of the slave board shown in FIG.

4 is a timing diagram showing board-to-board data transmission of the base station apparatus shown in FIG.

5 is a block diagram showing a connection state of the boards of the base station apparatus according to the present invention;

FIG. 6 is a detailed configuration diagram of slave boards among the boards of the base station apparatus shown in FIG.

FIG. 7 is a detailed block diagram of a programmable gate array (FPGA) in the slave board shown in FIG.

8 is a diagram illustrating a global bus occupancy request signal scanning timing in the board of the base station apparatus shown in FIG.

FIG. 9 is a diagram illustrating the configuration of logic circuits in a slave board for generating the global bus occupancy request signal shown in FIG. 8; FIG.

FIG. 10 is a timing diagram showing global bus occupancy confirmation on the board of the base station apparatus shown in FIG. 5; FIG.

FIG. 11 is a schematic diagram of a logic circuit in a slave board for generating the global bus occupancy confirmation message shown in FIG. 10.

12 is a logic circuit diagram of a master board of the base station apparatus shown in FIG.

FIG. 13 is a timing diagram illustrating a plurality of board-to-board data transfers shown in FIG. 5.

* Description of the symbols for the main parts of the drawings *

60: slave board 70: master board

71: master CPU 72: master FPGA

73: master input and output unit 74: master drive unit

81, 91: counter 82, 92: logic

83, 93: latch portion 84, 94: buffer portion

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

5 is a block diagram showing a connection state of the boards of the base station apparatus according to the present invention.

In the base station apparatus of the base station apparatus having a slave board unit 60 consisting of one master board unit 70 and the first to nth slave boards 60a to 60n, the connection state of the boards of the base station apparatus according to the present invention is a master. The board unit 70 and the slave board unit 60 are connected to a shared global bus (eg, a serial bus).

The global bus includes a frame synchronization signal (FRS) bus and an assert clock signal (ASTCLK) bus for generating a frame synchronization signal and a reference clock required for the operation of the first to nth slave boards 60a to 60n. And an assert signal for transmitting a signal for occupying the data bus to the master board unit 70 when the first to n-th slave boards 60a to 60n receive their order in accordance with the frame synchronization signal. Bus, Bit Rate Clock Signal (BRCLK) Bus, Data Bus for Data Transfer, Own Frame Sync Signal (OWN_FRS) Bus and Own Clock (OWN_CLK) Bus as Reference Clock Signals An oun bus OWN_BUS, which is a control signal bus, and an oun request bus OWN_REQ, which transmits a signal for requesting bus occupancy from each slave board 60a to 60n to the master board unit 70.

The master board unit 70 and the first to nth slave boards 60a to 60n respectively include a global bus controller 70b and first to nth slave global bus controllers 60a _{2 to} 60n _{2 for} controlling the global bus. And an input / output unit 70c and first to n-th slave input / output units 60a _{3 to} 60n ₃ connected to the global bus to transmit and receive data, and a driver 70d and first to n-th slave drives 60a ₄ to ₄ . 60n ₄ ), a central processing unit (CPU) 70a for controlling the master board unit 70 and the first to nth subordinate board units 60a to 60n, and the first to nth subordinate central processing units 60a _{1 to} 60n. ₁ ). In this case, the global bus controllers 70b and 60a _{2 to} 60n ₂ may be configured as FPGAs.

6 is a detailed block diagram of a slave board among the boards of the base station apparatus shown in FIG. 5, and FIG. 7 is a detailed block diagram of a programmable gate array among the slave boards shown in FIG. 6.

The detailed configuration of the slave board of the base station apparatus according to the present invention will be described taking the first slave board 60a as an example.

The slave global bus controller 60a ₂ is provided from the frame synchronization signal FRS, the assert clock signal ASTCLK provided by the master board 50, its IDs ID 0-4, and other boards connected to the global bus. The state machine as shown in FIG. 7 is maintained in accordance with the received assert (RX_AST) signal.

In addition, the global bus control unit 60a ₂ is configured to determine a next frame to transmit during a transmission, such as an Own Frame Synchronization Signal (OWN_FRS), an Own Clock (OWN_CLK) Signal, an Own Bus (OWN_BUS) Signal, and an Own Request (OWN_REQ). There is a state machine (which will be described with reference to FIGS. 9 and 11) using a signal. The state machine to be described with reference to FIGS. 9 and 11 is driven while any one board asserts the assert signal LOW to transmit data and the other board is the master board 70. It operates in accordance with the Own Frame Synchronization (OWN_FRS) signal and the Own Clock (OWN_CLK) signal.

Subsequently, as shown in FIG. 6, when there is data to be transmitted from any one board (eg, the first slave board 60), the slave input / output unit 60a ₃ transmits the RTS to the slave global bus controller 60a ₂ . By asserting a signal low to request data transmission, the slave global bus controller 60a ₂ uses the request (OWN_REQ) signal that one board is busy during transmission to use the master board ( 70), the master board 70 checks the OWN_REQ signal and gives the bus occupancy right through the OWN_BUS signal to the board having the highest priority among the boards requesting transmission. The board that receives the bus occupancy rights transmits the data immediately after the current board finishes transmitting. Then, the CTS signal is asserted low to the slave input / output unit 60a ₃ of its own board to allow data transmission, and the transmission bit rate clock TX_BRCLK signal for transmission is supplied to the slave driver 60a ₄ . do. In addition, the global bus controller 60a ₂ asserts the transmit assert signal TX_AST to LOW to the slave driver 60a ₄ to indicate that the board is transmitting data.

The global bus controller 60a ₂ of the slave board as shown in FIG. 7 is connected to the frame sync signal FRS, the assert clock signal ASTCLK, and the global bus controller 60a ₂ provided from the master board 70. The counter 60a ₂₁ , which is a state machine, is maintained in accordance with the receiving assert (RX_AST) transmitted from any other board, and the output of the counter 60a ₂₁ , the board IDs ID0 to 4, and the bus OWN signal There is a logic unit 60a ₂₂ which determines the data transmission order in accordance with this.

Therefore, one board compares the output of the state machine 60a ₂₁ with the board address, which is the board address, and transmits data by asserting the transmit assert (TX_AST) low when it is its turn, or by requesting a cool request ( Requests to occupy the bus through OWN_REQ, and transmits data by asserting the transmit assert (TX_AST) low when receiving the bus occupancy authority through the OWN_BUS.

8 is a scanning timing diagram for a global bus occupancy request signal in the board of the base station apparatus shown in FIG. 5.

In this case, the scanning timing diagram for the global bus occupancy request signal on the board will be described with an example of 31 slave boards.

The global bus occupancy request signals generated by the plurality of boards are transmitted to the master board unit 70, and the master board unit 70 generates a global bus occupancy signal according to the transmitted global bus occupancy request signals. The scanning of the global bus occupancy request signal is performed in synchronization with the Own frame sync signal OWN_FRS and the Own clock signal OWN_CLK. The first to thirty-first slave boards 60a to 60n are formed in order.

Each board generates a low signal (a board having sequence number 3) when there is data to be transmitted at the time allocated to it, and a high signal when there is no data to transmit. 1 OWN_REQ). In this case, a low signal indicating that there are data to be transmitted by several boards may be generated in one cycle of the OLD_FRS signal. In FIG. 8, it can be seen that the boards having sequence numbers 5 and 29 generate a low signal indicating that there is data to be transmitted at the time allocated to the board (second OWN_REQ).

FIG. 9 is a logic circuit diagram of a slave board for generating the global bus occupancy request signal shown in FIG. 8.

The logic circuit in the slave board receives a receive assert (RX_AST) signal, an oak frame sync signal (OWN_FRS), and an o clock (OWN_CLK) signal from an arbitrary board transmitting data, and receives a currently-owned frame sync signal (OWN_FRS). ), A counter unit 81 that is a state machine that counts the OWN_CLK signal, which is a reference signal, the current sequence number counted by the counter unit 81, and the slave boards 60a to 60n. A logic unit 82 for comparing the order numbers (IDs 0 to 4) of the first, a latch unit 83 for latching an RTS signal for requesting data transfer from each slave board 60a to 60n, and As a result of the comparison of the logic unit 82, if the current sequence number according to the reference clock is the same as the slave board's own address, it is buffering the data signal in the latched state. low( And a buffer 84 for outputting a LOW signal and generating a request signal OWN_REQ signal to the master board 70. Such a logic circuit is configured in the first slave global bus controller 60a ₂ to the nth slave global bus controller 60n ₂ of the slave boards 60a to 60n.

FIG. 10 is a timing diagram illustrating global bus occupancy confirmation in the plurality of boards shown in FIG. 5.

At this time, a timing diagram showing the confirmation of the global bus occupancy request on the board will be described using 31 sub-boards as an example.

First of all, the global bus occupancy check of the plurality of boards generates a low signal indicating that there is data to be transmitted from the board having sequence number 3 during scanning as shown in FIG. 6, and thus, the Own frame sync signal (OWN_FRS) and the Own bus (OWN_BUS). ) Signal is sent at the time of the board with the corresponding sequence number 3, and the rest is kept low (OWN_BUS).

Here, when requesting bus occupancy from several boards at the same time, the master board 70 compares the current counter value and sequence number of each board to determine a board to give bus occupancy rights. For example, although not shown in the drawing, when a board with transmission number 10 is currently transmitting data, when the boards with transmission numbers 3 and 20 request data transmission simultaneously in the same scanning cycle, the current counter values of these boards are used. Compare As a result of the comparison, if the boards with sequence numbers 3 and 20 requested the first bus occupancy in the current scanning cycle, both boards had a count value of 0. Then, the bus number was given to the board with sequence number 20, the board with the later sequence number. do. If one of the boards has a counter value that is pending, then the board with the pending counter value gives bus occupancy rights.

FIG. 11 is a logic circuit diagram of a slave board for generating the global bus occupancy confirmation message shown in FIG. 10.

The logic circuit in the slave board 60 receives a receive assert (RX_AST) signal, an oval frame sync signal (OWN_FRS), and an o clock (OWN_CLK) signal transmitted from an arbitrary board transmitting data, and receives a current frame sync signal. Counter unit 91, which is a state machine that counts the (OWN_FRS) and the Own Clock (OWN_CLK) signals, the current sequence number counted by the counter unit 91 and its slave boards 60a to 60n. When the logic portion 82 for comparing the sequence numbers (ID 0 to 4) and the bus occupancy permission signal corresponding to the bus occupancy request are input (OWN_BUS), in the case of its own turn, it is low by the open collector. A buffer 84 for generating a signal to the latch unit 83 and a latch unit 83 for outputting a signal indicating that the bus signal has been checked to the master board 70 when a low signal is input from the buffer 84. do.

12 is a logic circuit configuration diagram of the master board of the base station apparatus shown in FIG. 5.

The logic circuit of the master board 70 receives a clock frame synchronization signal QWN_FRS and clock clock OWN_CLK, and counts a counter unit 91 for counting a current frame synchronization signal OWN_FRS and a clock clock OWN_CLK. A logic unit 92 for outputting a read enable signal to any one of the slave boards 60a to 60n of the slave boards 60a to 60n countered by the counter 91; The latch unit 93 generates a bus occupancy confirmation signal DATA to an arbitrary subordinate board according to the read enable signal of the unit 92, the Own Request signal OWN_REQ, and the Own Bar Clock / OWN_CLK signal. .

Such a logic circuit is configured in the first slave global bus controller 60a ₂ to the nth slave global bus controller 60n ₂ of the slave boards 60a to 60n.

FIG. 13 is a timing diagram illustrating a plurality of inter-board data transfers shown in FIG. 5.

The master board unit 70 and the first to nth slave boards 60a to 60n operate in synchronization with the frame synchronization signal Frs and the assert clock signal Astclk. In the CPUs 70 and 60a to 60n of the master board unit 70 and the first to nth slave boards 60a to 60n, the address of the master board 70 or the nth slave boards 60a to 60n in the data signal is given. Receive the data by determining whether it is data to be received or not.

The master board unit 70 and the first to n-th subordinate boards 60a to 60n are defined as n-bit transmission numbers (for example, 5 bits) as their addresses, and then round robin determined when to transmit accordingly. -Robin) sends data in order.

First, when the frame synchronizing signal FRS becomes high, the assert clock signal ASTMCLK also operates, and the board having the transmission number 0 (for example, the master board unit 70) starts transmitting to another board. At this time, if there is data to be transmitted, the assert signal AST is active low and then data is transmitted (DATA). In the middle of transmitting data from the board having the transmission number 0 to the other board, the master board 70 checks whether a request signal OWN_REQ is generated from the other board.

Such a check is generated by the master board 70 in accordance with the Own Frame Synchronization signal OWN_FRS and the Own Clock signal OWN_CLK in one of the remaining boards except the currently transmitting board. OWN_REQ

Then, the master board 70 informs that the board that has generated the request signal on the Own bus OWN_BUS while the data is being transferred is allowed to occupy the bus.

As described above, the present invention eliminates the time spent waiting for an order on the global (serial) bus by reserving the data bus while the next board is sending a message, and the sequence number and counter By calculating the order and determining the order, the data can be transmitted as soon as possible when the data is generated, thereby improving the data transmission efficiency.

Claims (9)

In a device in which multiple slave boards having different addresses from one master board are connected to a shared global bus, Any one or more of any one or more of the boards while transferring data using the global bus from one of the master board or any of a plurality of slave boards to any of the master boards or other of the other dependent boards. And a global bus controller configured to control an OWN_REQ signal to transmit a signal indicating that data to be newly transmitted to another board has been generated to the master board. The apparatus of claim 1, wherein the global bus controller comprises: a frame synchronization signal bus, an assert clock signal bus, an oval frame synchronization signal bus for generating a frame synchronization signal and a reference clock required for operation between the master board and the plurality of slave boards; An asserted clock bus, an assert signal bus for transmitting a signal for occupying the data bus of the global bus in accordance with the frame synchronization signal in the plurality of slave boards to the master board, and between the master board and the plurality of slave boards. A data bus for transmitting data and an OWN bus that transmits a signal indicating that the data bus is occupied by one of the master board or a plurality of slave boards to the plurality of slave boards. Board-to-board data transceiver of a communication device. 3. The owl request bus and the owl bus are operated in synchronization with the owl frame synchronization signal OWN_FRS and the own clock signal OWN_CLK generated by the owl frame synchronization bus and the owl clock bus, respectively. Board data transmission and reception device of the communication device. The counter board of claim 2, wherein the master board receives a new frame synchronization signal OWN_FRS and a clock signal OWN_CLK and counts a current frame frame synchronization signal OWN_FRS and a clock signal OWN_CLK. A logic unit for outputting a sequence number of any subordinate board counted by the counter unit through a read enable signal, and a request signal (OWN_REQ) generated to occupy the data bus in one or more subordinate boards of the subordinate boards; A buffer for buffering the < RTI ID = 0.0 > and < / RTI > the clock signal OWN_CLK, the read enable signal of the logic section and the request signal OWN_REQ from the buffer section to generate a bus request signal. A board-to-board data transmission / reception device of a communication device, characterized in that the latch unit for transmitting occupancy confirmation data. The counter board of claim 2, wherein the slave board receives the right frame synchronization signal OWN_FRS and the right clock signal OWN_CLK, and counts a current frame synchronization signal OWN_FRS and a reference signal OWN_CLK. A logic unit for receiving the current sequence number counted by the unit and comparing the current sequence number with an address number of its own board, a latch unit for latching a data signal in the slave board, and a comparison of the logic unit Result If the current sequence number according to the reference clock is the same as the slave board's own address, the data signal in the latched state is buffered, and if there is data to be transmitted in its turn, the request signal OWN_REQ is sent to the master board. Board-to-board data transmission and reception device of a communication device, characterized in that consisting of a buffer for generating a signal. In the board-to-board data transmission and reception method of a device consisting of a plurality of slave boards having a different address from one master board, A first step of transferring data from any one of the master board or a plurality of slave boards to any one or more boards of the master board or other slave boards; A second step of transmitting a signal indicating that data to be newly transmitted to the master board is generated when data to be newly transmitted are generated from at least one board other than the board to which the data is being transmitted while the data is being transmitted; A third step of waiting, by the master board, the boards having transmitted a signal indicating that data to be newly transmitted have occurred in a predetermined order; And a fourth step of allowing the boards to transmit new data to one or more master boards or slave boards in a predetermined order when transmission of the data is terminated in the first step. How to send and receive data between boards. The method of claim 6, wherein the scanning of the newly transmitted data in the second step comprises: generating a frame synchronization signal and a reference clock from the master board to the plurality of slave boards; And transmitting a bus occupancy request signal indicating that there is data to be transmitted from the at least one board of the master board or the plurality of subordinate boards to the master board. The board of claim 6, wherein the board is waiting for a predetermined order when the board that has transmitted the signal to be newly transmitted has been generated in the third step. Characterized in that the board having the next address is waited first than the address Method of transmitting and receiving data between boards of communication device. 7. The communication apparatus according to claim 6, wherein in the third step, the board having the pending value is first waited when the board that has transmitted the signal that the new data to be transmitted has been waited in a certain order. To send and receive data between boards.