KR100301835B1 - Method for block matching motion estimation and apparatus for the same - Google Patents

Abstract

A method and apparatus for estimating motion using a block matching algorithm, in particular, a first step of calculating a measurement function for all candidate vectors in a search region with the most significant bits of a candidate block in a search region of a current frame and a previous frame; And a second step of comparing the calculation result of the measurement function to extract candidate blocks having a minimum value, and a third step of performing again from the first step with the next most significant bit only for the extracted candidate blocks. This process is repeated until the number of candidate vectors becomes one or the upper bits used in the calculation become smaller than the preset threshold, thereby reducing the number of gates and increasing the motion estimation error. In addition, the lower bits may not be used in the block matching process, It has a low pass filtering effect on the data, thereby reducing the effects of noise.

Description

METHOD FOR BLOCK MATCHING MOTION ESTIMATION AND APPARATUS FOR THE SAME}

The present invention relates to a system requiring video compression transmission, and more particularly, to a motion estimation method and apparatus using a block matching algorithm.

In the video compression transmission system, a method of eliminating temporal redundancy of image data using a block matching algorithm has been generalized and widely used. This is because data reduction by block matching algorithm is very effective and relatively easy to implement and shows good performance compared to other motion estimation methods.

This block matching algorithm finds a motion vector (V _x , V _y ) that minimizes the measurement function represented by Equation 1 below.

Here, B is a set of block data coordinates to be estimated currently, and SA is a set of search area coordinates in a previous frame. And, r (x, y) and s (x + v _x , y + v _y ) are respectively the position of the position shifted by (v _x , v _y ) from the reference block data and the reference block position at ( _x , _y ) Candidate block data in the search region is shown. Various structures have been proposed as a method of implementing a Very Large Scale Intergrated Circuit (VLSI), and one of them, a primary systolic array structure, is illustrated in FIG. 1.

FIG. 1 illustrates a case where a block size is 4 × 4 pixels, and the structure of a processing element (PE) is shown in FIG. 2. If 16 × 16 pixels, which are macroblock units, are processed, the execution elements are connected to 16 serial units.

In this case, since each pixel is 8 bits, 8 bit data of the corresponding pixel of the reference block for which the current motion is to be estimated and 8 bit data of the pixel at the same position of the candidate block in the search area are temporarily latched through the respective latches. It is input in parallel to the subtractor of each performance element.

That is, the difference between the pixel value (= 8 bit data) of the reference block for which the current motion is to be estimated and the pixel value (= 8 bit data) at the same position of the candidate block in the search area is output from the subtractor 21. The difference value between the two pixels output from the subtractor 21 is absolute valued in the absolute value unit 22 and then input to the adder 23. The adder 23 adds the partial sum output from the previous PE and the output of the absolute value unit 22 and latches the latch 24 and outputs the partial sum to the next PE. At this time, since the PE located on the uppermost side has no previous PE, the input partial sum is zero. When this process is sequentially performed at each PE and the subtotal is input to the PE located at the lowermost side, the PE is output to the accumulator by adding the absolute value and the subtotal to the difference value of the two pixel values, and the accumulator is transferred to the input subtotal. Add data

If this process is repeated and all pixel values of the reference block for which current motion is to be estimated and all pixel values of the candidate block in the search area are processed in each PE and then output through the accumulator, this value is the smallest minimum value among the candidate blocks. Determine if it is. If the minimum value, the candidate block is determined to be the most similar block to the current reference block. When the most similar candidate block is determined, the difference signal between the candidate block and the reference block and the motion vector (v _x , v _y ) at that time are transmitted to the decoder through an encoding process.

However, in general, since the motion estimation methods including the block matching algorithm generally require a large amount of computation and high cost, many studies have been conducted to solve this problem. One of them is not a method of matching all blocks existing in the search area as shown in FIGS. 1 and 2 but instead of matching some blocks and searching for an optimal block step by step based on the result. However, this method has a problem of lowering the compression efficiency by greatly increasing the motion compensation error in image compression, and has a disadvantage that it is not suitable to implement a parallel structure systolic array structure in the VLSI implementation.

Meanwhile, another method has recently been studied. This is a method of simplifying and processing image data represented by 8-bit pixels into a binary image. That is, since the pixel has 8 bits, each pixel value has any value between 0 and 255. Therefore, the threshold value is determined and the pixel value is simplified to 1 if the pixel value is larger than the threshold value and to 0 if the pixel value is smaller than the threshold value. In this case, 8-bit subtraction and absolute value operations are simplified to 1-bit exclusive ora operation in the measurement function of Equation 1 above.

However, this method also simplifies 8-bit image data to 1 bit, which makes it difficult to find the most similar block, resulting in poor motion estimation performance and thus lowering compression efficiency. In addition, a threshold value is very important in the process of simplifying a binary image, and the determination of the threshold value is very difficult and requires a large amount of computation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to perform a block-matched motion estimation step by bit, thereby reducing the number of gates without reducing the image compression efficiency method and apparatus In providing.

Another object of the present invention is to provide a block matching motion estimation method and apparatus for reducing a motion estimation error due to noise.

1 is a block diagram showing a first systolic array structure of a conventional block matched motion estimation apparatus

2 is a detailed block diagram of each performance element of FIG.

3 is a block diagram showing a structure of a first order systolic array of a block matched motion estimation apparatus according to the present invention;

4 is a detailed block diagram of each performance element of FIG.

Explanation of symbols for main parts of the drawings

41: exclusive oar gate 42: adder

43: latch

In order to achieve the above object, the block matching motion estimation method according to the present invention calculates a measurement function for all candidate vectors in a search region with the most significant bits of the reference block of the current frame and the candidate block in the search region of the previous frame. And a second step of comparing the calculation result of the measurement function to extract candidate blocks having a minimum value, and having the next most significant bit only for the extracted candidate blocks again from the first step. A third step is performed, and the process is repeated until the number of candidate vectors becomes one or the most significant bit value becomes smaller than a preset threshold.

In the block matched motion estimation apparatus according to the present invention, a plurality of performance elements are serially connected, and in each performance element, data corresponding to one pixel of a reference block of a current frame and a candidate block within a search range of a previous frame are received in parallel. The serial register outputting serially by 1 bit is connected, and the accumulator is connected to the lowest performing element.

Each of the performing elements may include an exclusive ora gate for receiving an exclusive ora operation by receiving 1 bit of pixel values at the same positions of the reference block of the current frame and the search region candidate block of the previous frame, and outputting and transferring the exclusive ora gate. And an adder for adding an output of the performing element, and a latch for outputting the output of the adder to the next performing element.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention uses that the influence on the calculation result of the measurement function differs depending on the bit position of the image data. That is, the higher bits have a greater influence on the measurement function. Table 1 below shows an absolute difference value that can be calculated for one pixel when only the upper 3 bits are compared.

Range of measurements per pixel q ₇ q ₆ q ₅ Range of | r-s | 0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1 0 to 3132 to 3264 to 6396 to 127 128 to 159160 to 191192 to 223224 to 255

Where q _i = r _i s _i , which indicates whether the i-th bit of the reference block data and the candidate block data of the previous frame are identical. In other words, 0 means the same, 1 means different. R _i represents the i-th bit of the reference block data, and s _i represents the i-th bit of the candidate block data in the search region. If the image data is 8 bits, the bit position represents the most significant bit (MSB) if i = 7, and the least significant bit (LSB) if i = 0.

In Table 1, it can be seen that the measurement function value (range of = | rs |) has a larger value than the case in which the upper bits are the same without having to consider the lower bits when the upper bits are different. For example, if the upper three bits (q ₇ , q ₆ , q ₅ ) are all the same (000), the measurement function value is between 0 and 31, with only the most significant bit (q ₇ ) and the next bit (q ₆ , q). ₅ ) are different (011), it can be seen that the measurement function value is between 96 and 127. That is, the larger the measurement function value, the more likely it is not a similar block. The present invention takes full advantage of this fact and reduces the complexity of the hardware with the stepwise motion estimation method in units of bits, thereby reducing the performance degradation.

FIG. 3 is a block diagram illustrating a first systolic array structure of a block matching motion estimation apparatus according to the present invention. In the block matching process, only one bit is used in each step, and the block size is 4 × 4 pixels. It is shown.

That is, a plurality of, for example, four execution elements are serially connected, and in each execution element, 8 bits of data corresponding to one pixel of the candidate block in the search range of the reference block and the previous frame are parallelly inputted, and each bit is serially transmitted. The serial register to output is connected. Then, the process of inputting the partial sum calculated in one execution element to the next connected execution element proceeds sequentially to the last connected execution element. An accumulator is connected to the last execution element to perform a process of adding a partial sum input from the last execution element and a previous value in macroblock units. Here, since there is no previous PE in the first execution element, 0 is entered as the subtotal.

In this case, since the motion estimation is performed in macroblock units, 16 performance elements are actually required.

In FIG. 3 configured as described above, each performing element receives data in bit units for one pixel. That is, pixel values at the same positions of the reference block of the current frame and the candidate block in the search area of the previous frame are input to the performing element from the most significant bit through each serial register.

In this case, as shown in FIG. 4, each of the performing elements includes an exclusive ora gate 41 and an exclusive ora gate 41 that exclusively ora pair data of a reference block and data of a candidate block in a search region of a previous frame. An adder 42 that adds an output and a partial sum input from the previous PE, and a latch 43 that temporarily latches the output of the adder 42 and then outputs it to the next PE.

Therefore, the performing element has a reference block of the current frame and the most significant bit (MSB) of the candidate block in the search region of the previous frame, and a measurement function represented by Equation 2 for all candidate vectors in the search region. Calculate

Here, r_i (x, y) and s_i (x + v_x, ~ y + v_y) are respectively equal to (v _x , v _y ) at the i-th bit of the reference block data at the (x, y) position and the position of the reference block. It represents the i-th bit of the candidate block data at the displaced position. In the first step, this process is performed from the most significant bit (i = 7).

Then, the candidate block having the minimum value, that is, candidate vectors, is extracted using the calculation result of the measurement function. This is because several candidate vectors may have the same measurement value because only one bit is used to calculate the measurement function. Here, the candidate vector represents a difference in coordinate values between the candidate block and the reference block to be estimated.

Therefore, the above described processes are performed again with respect to the next most significant bit i = i-1 with the extracted candidate vectors. This process is repeated until the number of candidate vectors becomes one or the value of i becomes smaller than the minimum value.

Here, the minimum value of i is arbitrarily set and may be greater than or equal to zero. In addition, even if the least significant bit is not included, the candidate vector may be one.

Therefore, the lower bit may not be used in the block matching process, which has a low pass filtering effect on the image data, thereby reducing the influence of noise. That is, since the noise usually affects the lower bits, the influence of the noise can be reduced by not using the lower bits.

As described above, since the present invention can perform the conventional 8-bit adder and the absolute value operation as the 1-bit exclusive OR operation, the hardware complexity can be greatly reduced, and thus, the gate count in the VLSI implementation is significantly reduced.

In terms of the conventional method and the number of gates required per performance element of the present invention, the conventional method requires two adders (8 bits, 12 bits), a 12 bit latch, and 12 bits of inversion logic for absolute operation. . On the other hand, in the case of the present invention, it can be seen that there is a large amount of gate saving effect because it is implemented with an exclusive OR gate, an adder (5 bits), and one 5-bit latch. In practice, the adder requires two exclusive oar gates, two end gates, and one oar gate per bit, and a latch requires six NAND gates per bit. As shown.

Compare the Number of Gates Required per Performing Element Conventional method The present invention Exclusive OR gates and gates OR gates NAND gate inverters 40 pieces 40 pieces 20 pieces 72 pieces 12 pieces 11 pieces 10 pieces 5 pieces 30 pieces

In addition, when the sequential motion is estimated from the most significant bit to the least significant bit of the image data, and the estimation is no longer necessary, that is, when the candidate vector is one or the minimum value of i is determined, the estimation is stopped. Can be reduced.

As described above, according to the method and apparatus for block matching motion estimation according to the present invention, a system requiring video compression transmission, i.e., digital TV, camcorder, DVD, The cost of implementing a motion estimator in a video conferencing system can be reduced. In addition, the lower bit may not be used in the block matching process, which has a low pass filtering effect on the image data, thereby reducing the influence of noise.

Claims (5)

A first step of calculating a measurement function for all candidate vectors in the search region with the most significant bits of the reference block of the current frame and the candidate block in the search region of the previous frame; Comparing the calculation result of the measurement function and extracting candidate blocks having a minimum value; And a third step of repeating the first step with the next most significant bit only for the extracted candidate blocks, and repeating the process until the number of candidate vectors becomes one. Motion estimation method. The method of claim 1, wherein the measurement function of the first step is obtained by applying the following equation. Here, B is a set of block data coordinates to be estimated currently, SA is a set of search area coordinates in a previous frame, and r_i (x, y) and s_i (x + v_x, ~ y + v_y) are respectively (x, y) represents the i th bit of the reference block data at the position and the i th bit of the candidate block data at the position shifted by (v _x , v _y ) from the position of the reference block. The method of claim 1, wherein the third step And repeating the first step with the next most significant bit only for the extracted candidate blocks until the most significant bit value becomes smaller than a preset threshold value. 4. The method of claim 3, wherein the threshold is The block matching motion estimation method, characterized in that the value is set to greater than or equal to zero. A plurality of performance elements connected in series, A serial register connected to each of the plurality of performance elements and receiving data corresponding to one pixel of a reference block of a current frame and a candidate block in a search range of a previous frame in parallel and serially outputting each bit; And an accumulator connected to the lowest performing element among the performing elements, Each of the plurality of performance elements may include an operation unit configured to perform an exclusive ord operation on one bit of pixel values at the same positions of the reference block of the current frame and the candidate block in the search region of the previous frame; An adder for adding the output of the operation unit and the output of a previous performing enzyme; And a latch for outputting the next performing element after temporarily latching the output of the adder.