KR100299818B1 - Integrated circuit chip carrier insert - Google Patents

Abstract

The present invention relates to inserts for chip carriers that can be used universally for a variety of device shapes and purposes, wherein the chip carrier inserts of the present invention can be used in a general carrier floor and / or in the frame of various conventional carriers. Both types of integrated circuit chips can be integrated into a single integrated circuit chip carrier if it is capable of accommodating both integrated and thin-quad-flat-pack (TQFP) integrated circuit chips or if a separate dedicated integrated circuit chip carrier must be used. It acts as an adapter insert that makes the frame available.

Description

Integrated Circuit Chip Carrier Inserts

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit chip carriers for use in the transportation and handling of integrated circuit chips, and more particularly to inserts for chip carriers that can be used universally for a variety of device types and purposes.

In the manufacture of electronic devices such as integrated circuits, there is a demand for a manufacturing method that can reduce manufacturing costs, reduce the size of the device, and at the same time increase the density of electronic functions of the device. To reduce the unit cost associated with manufacturing these devices, manufacturers have tested multiple devices simultaneously to increase device test speeds.

The semiconductor industry has typically done a method of placing a plurality of electronic devices to be tested on a test tray and then coupling the electronic devices to a test head plate having a corresponding plurality of test contacts. Each device is placed on a seat of a device, which will be described later, called a chip carrier, and then a number of such chip carriers are arranged in a matrix on a test tray. Thus arranged test trays arranged with a plurality of chip carriers are arranged in a line (ie, located above or below) perpendicular to the test fixture. The test fixture includes test contacts (test pins) that contact the pins of each device to be tested to supply test signals to and receive test signals from the device. Each of the test contacts has a corresponding carrier module arranged in a row so that the contactor is engaged with an electronic element located in the carrier module when the test tray and the test fixture move relative to each other in the vertical direction.

The contact is provided with a number of test pins or test leads in electrical communication with the leads of the electronic elements to be tested. In an electronic device test system, for example, an integrated circuit device tester, an automatic test processor is electrically connected. The electric device test system includes a test signal generator for supplying a test signal to an electronic device, and a signal comparator for analyzing a test result. Include. Based on these results, the electronics are transferred to another location in the test process and then sorted for proper processing.

The size and configuration of standard electronic chips are currently rapidly changing. Some high-speed integrated circuit devices use short signal wires instead of relatively long signal wires used in conventional package types such as quad-flat-pack (QFP) devices. For example, newer types of integrated circuit devices are molded into a package called a thin-quad-flat-pack (TQFP). If a test tray is used to test such integrated devices, there is a need to use a new carrier module suitable for fixing the electrical insulators between the conductors and for preventing deformation of the conductors.

Typically, integrated circuit device carriers are fairly complex three-dimensional devices typically fabricated from a given thermoset or thermoplastic material using a variety of means, often because of the complex three-dimensional microstructure of the carrier that often causes the carrier to break. Or cracking occurred. In addition, as described above, even a slight change in the integrated circuit device package or a slight change in the application environment requires redesigning or rearranging the carrier itself, which increases the cost.

The present invention solves the above-mentioned problems related to the prior art by providing an insert for an integrated circuit chip carrier which can be universally used for various device shapes and purposes at low design and manufacturing costs.

In a suitable embodiment, the insert of the present invention acts as an adapter insert to accommodate the integrated circuit chips of both QFP and TQFP types in a general carrier floor and / or in the frame of various existing carriers. In another embodiment, the insert of the present invention allows the integrated circuit chips of both the QFP type and the TQFP type to use a frame of a single integrated circuit chip carrier, which must use a general carrier floor and / or a separate dedicated integrated circuit chip carrier. Acts as an adapter insert. In a suitable embodiment of the present invention, the integrated circuit chip insert is made of a metal (eg stainless steel) that is inexpensive and in addition to malleable. In another embodiment of the present invention, the integrated circuit chip insert may be made of a material such as plastic or polyimide.

In a suitable embodiment, the insert of the present invention is formed of a metal (stainless steel) blank of a two-dimensional structure and includes insulated windows formed in the blank to provide protruding tabs and access to the leads of the associated integrated circuit chip. do. The insulating windows also provide DC insulation between the leads of the integrated circuit chip and the insert itself. The protruding tabs of the metal blank of the two-dimensional structure are bent to form a three-dimensional shape with respect to the embodiment applied to secure the insert to the chip carrier. In another embodiment of the invention, the insert is secured to the carrier by glue, screws, rivets, or the like.

1 is a plan view showing a preferred embodiment of the present invention chip carrier insert in a bent state;

2 is a longitudinal cross-sectional view of a suitable embodiment of the chip carrier insert in a bent state;

3 is a partial view of the chip carrier insert floor of the present invention in a state after bending;

4 is a partial view of the bottom corner of the chip carrier insert;

5 is a plan view of the chip carrier support frame;

6 is a plan view of a support frame of a chip carrier having a chip carrier insert fixed thereto;

FIG. 1 is a plan view showing a preferred embodiment of the present invention chip carrier insert in a bend state, in which a malleable two-dimensional blank 10 is shown. The blank 10, which can be made of metal, is designed to act as a common carrier floor and / or adapter insert that can accommodate both QFP type and TQFP type integrated circuits in the frame of various existing carriers. . The metal blank 10 is preferably made of stainless steel (eg 0.015 "302 stainless steel) with good malleability. Stainless steel is also inexpensive and provides good strength. For other embodiments of the present invention, the blank Can also be made of other materials such as plastic, polyimide and the like.

In a suitable embodiment of the invention the metal blank 10 consists of a main body having a generally rectangular shape, from which two protruding tabs 12, 14 extend in the longitudinal direction. These protruding tabs 12, 14 are later bent to provide a means for securing the metal blank 10 to the chip carrier support frame. In another embodiment of the present invention, other fixing sections such as glue, screws, rivets, etc. may be used to fix the metal blank 10 to the chip carrier support frame. The metal blank 10 has four rectangular insulating windows 16, 18, 20, and 22, which are QFPs. It is dimensionally positioned within the surface of the metal blank to accommodate the leads of the shaped and / or TQFP shaped packages.

In a preferred embodiment of the present invention, the length of the metal blank 10 is about 50 mm when including the lengths of the two protruding tabs 12, 14, and includes the length of the two protruding tabs 12, 14. If not, about 43mm. This metal blank 10 has a width of about 38 mm. Each protruding tab 12, 14 has a width of about 3 mm and a length of 20 mm.

The metal blank 10 is bent to form a three-dimensional structure that is wound around a predetermined portion of the chip carrier support frame so that it can be attached to the chip carrier support frame. In a preferred embodiment of the present invention, two bent portions of about 14 mm length are formed which are bent at about 90 ° at the bent positions 24 and 26 on the left and right sides of the longitudinal center of the metal blank 10. Further, two bent portions of about 21.5 mm in length which are bent at about 90 ° at the bent positions 28 and 30 on the left and right sides of the longitudinal center of the metal blank 10 are formed.

Figure 2 shows a longitudinal cross-sectional view of a suitable embodiment of the chip carrier insert in a bent state. When the metal blank 10 is bent as described with reference to the above drawings, the resulting chip carrier insert 34 has a three-dimensional structure. The floor 36 of this insert 34 has a length of about 28 mm and a width of about 38 mm. In the bend positions 24, 26 the carrier insert walls 34, 35 are bent from the carrier insert floor 36 at a height of about 8 mm and a height of about 8 mm.

In the bent positions 28 and 30, the protruding tabs 12 and 14 are bent at an angle of about 90 ° toward the center of the carrier insert 34 in a state substantially parallel to the carrier insert floor 36. After bending, the protruding tabs 12, 14 will extend about 2.3 mm in length toward each other.

The dimensions given for the carrier insert 34 are merely exemplary, and the carrier insert 34 may have various sizes and bending configurations depending on the size and shape of the chip carrier. Fig. 3 is a partial view of the chip carrier insert floor of the present invention in a state after bending. As described with reference to FIGS. 1 and 2 above, four insulating windows 16, 18, 20, and 22 are formed in the chip carrier insert to accommodate the conductors of the QFP and TQFP type packages. It is. These insulating windows 16, 18, 20, and 22 act as entrances to the conductors of the chip when the associated integrated circuit chip is located in the chip carrier. The insulating windows 16, 18, 20, and 22 also act as DC insulators between the leads of the integrated circuit chip and the chip carrier insert 34 itself.

In a preferred embodiment of the invention, the insulating windows 16, 18, 20, and 22 formed on the carrier insert floor 36 are dimensioned to fit a 100-pin QFP chip. In this configuration, the insulating windows 16 and 18 have a length of about 20 mm and a width of 6.7 mm, and the insulating windows 20 and 22 have a length of about 13.4 mm and a width of 6.7 mm. The insulating windows 16 and 18 are spaced apart by about 13.4 mm, and the insulating windows 20 and 22 are spaced about 19.4 mm apart.

4 The chip carrier insert floor 36 formed by the inner circumference of the insulating windows 16, 18, 20, and 22 has a length of about 19.4 mm and a width of 13.4 mm. Each of the insulating windows 16, 18, 20, and 22 is separated from the adjacent insulating window by metal bridges 55, 57, 59, and 61.

In a suitable embodiment of the invention, the chip carrier insert floor 36 is dielectric. In the illustrated case, the carrier insert floor 36 is formed to be non-conductive through oxidation or by applying a non-conductive coating to the surface.

The dimensions given to the insulator windows 16, 18, 20, 22 and the chip carrier insert floor 36 are illustrative, such insulator windows 16, 18, 20, 22 ) And the chip carrier insert floors 36 may have various sizes and configurations depending on the size and shape of the integrated circuit chips.

4 is a partial view of the chip carrier insert floor 36, showing the metal bridge 59 positioned between two adjacent insulating windows 18,22. In a suitable embodiment of the present invention, the metal bridges 55, 57, 59, and 62 serve to separate two adjacent insulating windows and at the same time the carrier insert floor located inside the insulating windows. Acts to connect to the seating portion of the chip carrier insert assembly 34.

In the illustrated embodiment, the metal bridge 59 extends about 45 ° with respect to the longitudinal direction of two adjacent insulating windows 18, 22 and has a width of about 0.375 mm.

In a suitable embodiment of the present invention, the metal bridges 55, 57, 59, 62 can be "cuttable". That is, when excessive force is applied to the chip seated on the chip carrier floor portion (part 36 in FIG. 3) inside the insulating windows, the metal bridges 55, 57, 59, 62 are formed. The floor portion is deformed or completely separated from the seating portion of the chip carrier insert assembly 34. This feature is particularly useful in test environments where malfunctions occur during the test process. This cutability prevents the destruction of expensive chips such as test sockets, chip carrier processing devices, test fixtures, or integrated circuits to be tested by sacrificial destruction or deformation of the chip carrier insert assembly 34.

For example, by changing the thickness, width, or material of the metal bridges 55, 57, 59, 62, the pressure level causing the cut can be adjusted. These examples are merely illustrative and various additional devices and / or methods may be used to adjust the sacrificial break or strain point of the floor of the chip carrier insert assembly that occurs when excessive pressure is applied.

5 is a plan view showing a chip carrier assembly 70 having a support frame. This chip carrier assembly 70 is used to transport and handle integrated circuit chips for a variety of applications, including testing. There is a costly problem in refurbishing such a chip carrier because of the comparatively complicated structure of the chip carrier, strict dimension tolerances, and various types of packaging of integrated circuits.

In the illustrated embodiment, the integrated circuit is seated on a shelf 78 located inside the chip carrier 70. In addition, the chip carrier 70 has coupling surfaces 80 and 82 on which the chip carrier insert 34 is fixed. The shelves 72, 78 act as floors that support the integrated circuit in a floating state. Since the shelves 72, 78 are formed with fixed dimensions in the chip carrier 70, the chip carrier 70 supports a limited number of integrated circuit chips (often only one) having an appropriate dimension. I can only do it.

The description given for the chip carrier assembly 70 described above is merely illustrative, and of course, may have a variety of sizes, shapes, and configurations in connection with the present invention.

6 is a plan view of the chip carrier 70 in which the chip carrier insert 34 is fixed. According to a preferred embodiment of the present invention, the chip carrier insert 34 may include the protruding tabs 12 and 14 of the coupling surface 80 of the chip carrier insert 34 to the chip carrier 70 (chip carrier support frame). Is bent as shown in FIG. Engagement surfaces 80 and 82 of the chip carrier support frame are grooved so that they act as anchors for attaching the chip carrier insert to the chip carrier support frame, as well as alignments for properly placing the insert on the support frame. Formed. It may also have other configurations that may allow the chip carrier insert 34 to be properly aligned with the chip carrier 70. When the chip carrier support frame is properly engaged with the chip carrier insert 34, the chip carrier insert floor 36 remains floating along the bottom surface of the chip carrier 70, wherein the insulating window 16, ( 18, 20, 22 will be properly positioned for insertion of the integrated circuit chip into the chip carrier 70.

As such, the chip carrier insert 34 of the present invention illustrated so far allows the chip carrier 70 to be easily adapted to support a new packaged integrated circuit chip. In another embodiment of the present invention, the chip carrier insert 34 allows the use of a single integrated circuit chip carrier for integrated circuit chips of both QFP and TQFP types. Of course, at present, two dedicated integrated circuit chip carriers are needed.

By changing the horizontal position and / or thickness of the chip carrier insert floor 36 used in the present invention, it is possible to accurately determine the vertical position of the conductors of the integrated circuit chip seated on the insert floor 36. In other words, according to the high orderability of the chip carrier floor 36 of the present invention, it is possible to accurately position the lead plane of the integrated circuit seated on the chip carrier floor 36 according to a specific use.

While the embodiments of the present invention have been described so far, the present invention is not limited thereto, and various changes can be made within the scope of the invention described in the appended claims.

Claims (14)

In an insert used for an integrated circuit chip carrier having a frame, An integrated circuit chip carrier having an interior in which an integrated circuit including a plurality of leads is received; A blank that is malleable and initially has a planar structure in which one of the opposing faces partially acts as a carrier floor for an integrated circuit chip package; Means for attaching the blank to the frame of the integrated circuit chip carrier, the means including one or more protruding tabs formed in the blank; An insert arranged to constrain or partially seal the integrated circuit chip with means for shaping the blank to dimensionally fit the integrated circuit chip carrier to a particular type of integrated circuit package to be carried by the integrated circuit chip carrier; Integrated circuit chip carrier insert comprising a. The method of claim 1, And the carrier floor is separated from the integrated circuit chip carrier when excessive force is applied. The method of claim 1, And the carrier floor deforms when excessive force is applied. The method of claim 1, And the carrier floor is processed to be non-conductive. The method of claim 1, And the carrier floor establishes a position plane for a set of leads extending from the integrated circuit chip package. The method of claim 1, The blank is an integrated circuit chip carrier insert, characterized in that made of metal. The method of claim 1, The blank is an integrated circuit chip carrier insert, characterized in that made of plastic. The method of claim 1, The blank has one or more insulated windows formed therethrough to provide an entrance to one set of leads of the integrated circuit chip package, the insulating means including insulation means for providing DC insulation between the set of conductors and the blank. Integrated circuit chip carrier inserts. The method of claim 1, And the protruding tabs engage with a support frame surface of the integrated circuit chip carrier to secure the blank to the integrated circuit chip carrier. The method of claim 1, And the protruding tabs engage with the surface of the support frame of the integrated circuit chip carrier at a position such that the insert is properly aligned with the integrated circuit chip carrier. The method of claim 1, And the protruding tabs are bent to define a three-dimensional dimension of the blank to secure the blank to the integrated circuit chip carrier support frame. In the insert device used for the integrated circuit chip carrier support frame, A metal member having a floor supporting the integrated circuit; At least one protruding tab formed on the metal member to fix the metal member in a state aligned with the integrated circuit chip carrier support frame; At least one insulating window formed through the surface of the metal member to provide an entrance to a set of leads of the integrated circuit chip and at the same time provide DC insulation between the set of conductors and the metal member. Integrated circuit chip carrier insert device. The method of claim 12, And said metal is stainless steel. In the method of converting an existing integrated circuit chip carrier to support various types of integrated circuit chip, (A) coupling a chip carrier member to a body of the integrated circuit chip carrier; (B) mounting the integrated circuit chip on a floor formed by the chip carrier member; (C) entering and exiting a set of leads of the integrated circuit chip through at least one insulating window formed in the chip carrier member; And (d) providing DC insulation of the set of wires of the integrated circuit chip from the chip carrier member using the at least one insulating window.