KR100297604B1 - Internal Clock Generation Circuit and Its Generation Method Suitable for Synchronous Semiconductor Memory Devices - Google Patents

Abstract

An internal clock generation circuit capable of reducing power consumption after obtaining an internal clock phase locked to an external clock is disclosed. The internal clock generation circuit suitable for a synchronous semiconductor memory device includes a clock buffer which receives the external clock, adjusts and level-shifts the output, and outputs the first clock as a first clock, and a time delay amount corresponding to the time delay of the clock buffer. A main delay delaying the amount of time delay and outputting it as a second clock, and having a plurality of delay sets connected to each other and continuously shifting the first clock and the second clock by a set unit time delay amount, respectively; A delay set group having a plurality of output nodes for generating comparison signals, each of which is compared with each other as a phase of the shifted second clocks, and outputting an internal clock synchronized with the external clock, and a logic state of the comparison signals In response to the first operation mode, the first clock is provided to the main delay unit as it is, and after the second operation mode, Since the first clock is provided after the special delay has a delay synchronization circuit including a monitoring unit for performing a delay hopping operation for power saving.

Description

Internal Clock Generation Circuit and Synchronization Method Suitable for Synchronous Semiconductor Memory Devices

The present invention relates to an internal clock generation circuit suitable for a semiconductor memory device such as a synchronous dynamic random access memory (Synchronous DRAM), in particular an internal having a delay locked circuit (Delay Locked Loop) using a synchronous delay line (Synchronous Delay Line) It relates to a clock generation circuit.

Historically, DRAMs have been controlled asynchronously by control devices such as processors. This means that the processor places the addresses on the DRAM input terminals and strobes them using the row and column address strobe signal pins. The addresses are held for the minimum time required. During this time, the DRAM accesses the addresses addressed in the memory and, after a predetermined time (access time), writes new data from the processor into the memory or provides it to its output for the processor to read the data stored in the memory. Therefore, the processor must wait while the DRAM performs various internal operations such as precharge, decoding addresses, sensing data, and outputting data through the output buffer. This wait state of the processor causes the entire system to slow down. Synchronous type DRAMs have been recently developed in the art to free the processor from such latency to allow the processor to perform other tasks and to perform data input / output operations at higher speeds. Such synchronous DRAMs are described, for example, in the journal IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 4, pages 529-533, under the title “16-Mb Synchronous DRAM with 125-Mbyte / s DATA Rate” issued in April 1994.

Figure 1 shows a simplified view of the SDRAM published in the journal. As shown in FIG. 1, an internal clock generation circuit 30 is installed in the timing generator 20-6 in the SDRAM chip 20 to receive the system clock CLK applied through the line 12 from the processor or controller 10 to generate the internal clock PCLK. Initially, the internal clock generation circuit 30 typically has a structure of a clock buffer that receives an applied system clock CLK and simply converts it to a level suitable for an internal circuit. By employing the clock buffer described above, each device in the chip eventually operates in response to the system clock. However, since the clock buffer simply serves to buffer the external clock, which is a system clock supplied from the outside, to generate the internal clock required inside the chip, the phase between the external clock and the internal clock due to the delay of the buffer. A difference inevitably occurs. Due to this phase difference, when time skew occurs between clocks, the operation of the I / O buffer 20-7 inside the chip is performed with time skew when the external clock is applied. Therefore, especially for the preferable operation of I / O buffer 20-7, the internal clock having the same phase as the external clock supplied from the outside, that is, the internal readout of the phase difference "0" in which time skew does not occur in full synchronization with the external clock. Research for generating a clock has been steadily and variously progressed in this field.

Conventional early methods attempted to obtain an internal clock synchronized with an external clock include a phase locked loop (PLL) or an initial delay locked circuit (DLL), as shown in FIG. It was installed in the internal clock generation circuit 30 of 20 to minimize the time skew between clocks. However, the initial phase synchronization method using the above-described PLL, initial DLL, and the like is not suitable for SDRAM 20 or the like connected to the high-speed processor 10 due to the long locking time (time taken for phase matching), and the memory cell array in the chip 20. There is a disadvantage in that 20-4 is not accessed, i.e., a standby current is increased during a stand-by. In addition, there has also been a drawback that a slower internal clock may be generated at certain frequencies than without a PLL or DLL.

As a result of researches and efforts to obtain a better phase synchronization method by compensating the disadvantages of the above-described synchronization circuits that can be employed in the internal clock generation circuit 30 of FIG. A digital type delay synchronization circuit constructed using a Synchrous Delay Line (SDL) has finally been disclosed in the art. An internal clock generation circuit having such a delay locked loop is disclosed in Korean Patent Application No. 96-67415 or 96-67416 filed on December 18, 1996 by the applicant of the present application.

However, as shown in the above-described prior arts, the internal clock generation circuit consisting of a clock buffer and a delay type synchronization circuit of digital type generates an internal clock which is more accurately and quickly synchronized with the system clock than a typical conventional circuit. However, there is a problem in that power consumption is high in the synchronization delay lines and the plurality of phase delay detectors configured in the circuit. That is, even after the phase comparison operation is performed by a specific phase detector and the internal clock is generated, the unit delays and the phase detectors in the first and second synchronization delay lines installed in the rear stage still perform delay and comparison operations, respectively. In more detail, the first and second unit delay units installed in the rear stage continue unit delay operations, and the first and second latches in the phase detectors installed in the rear stage continue to latch operation, thus consuming unnecessary power. . In this case, the amount of power consumed is increased or decreased depending on the number of installations of the first and second unit delayers and the phase detectors, that is, the number of taps. When the unit time delay amounts of the unit delay units are the same as described above, the number of taps of the unit delay units is small at high frequencies and relatively high at low frequencies. In addition, in order to obtain an internal clock more accurately synchronized with the external clock, the number of taps must be increased, thereby increasing power consumption.

In the synchronous DRAM which obtains an accurate internal clock by reducing the unit time delay of the unit delay unit, a plurality of unit delay units and phase detectors may be provided. Therefore, the amount of power consumed unnecessarily in the delay synchronization circuit is generally increased proportionally, which in turn increases the power consumption of the entire chip.

Therefore, there is a strong demand for a technique capable of minimizing power consumption while obtaining an internal clock more accurately synchronized with an external clock, and a technique capable of having a minimum number of taps for a set clock frequency.

An object of the present invention is to provide an internal clock generation circuit suitable for a synchronous semiconductor memory device that can solve the above problems.

Another object of the present invention is to provide an internal clock generation circuit for generating an internal clock more accurately and quickly synchronized to an external clock as well as reducing power consumption in a synchronous semiconductor memory device.

It is still another object of the present invention to provide an internal clock generation circuit for a semiconductor memory device capable of minimizing power consumption and having a minimum number of taps for a set clock frequency.

Another object of the present invention is to provide an internal clock generation circuit that can further reduce power consumption even after obtaining an internal clock phase-locked to the external clock.

It is another object of the present invention to block the operation of the unit delay units and the phase detectors installed after the internal clock synchronized with the external clock in the delay synchronization circuit having the synchronization delay line after being generated through a specific unit delay unit. The present invention provides a delay synchronization circuit having a power saving function.

Still another object of the present invention is to shift the output of the clock buffer immediately after the internal clock phase-locked to the external clock is output from the unit delay unit located at the second predetermined delay line, so that the internal clock is shifted to the unit. The present invention provides a delay synchronization circuit and a method for generating an internal clock according to the present invention, in which a unit delay unit installed at a front end of a delay unit is moved out and the operation of elements installed at a rear end thereof is blocked, thereby significantly reducing power consumption. .

Another object of the present invention is to output the internal clock phase-locked to the external clock through the interval delay set once, so that the output of the clock buffer passes through the special delay, so that the internal delay in the interval delay set as many times as the number of taps of the coarse special delay The present invention provides a method of reducing unnecessary power consumption in a delay synchronization circuit by obtaining a clock.

It is still another object of the present invention to provide an internal clock generation circuit and a method thereof for synchronizing semiconductor memory devices having a minimum number of taps for a set clock frequency to increase operation margin for low frequencies and minimize power consumption.

According to one aspect of the present invention for achieving the above object, a circuit for synchronizing the phase of the internal clock with the phase of the external clock received:

A clock buffer which receives the external clock and adjusts and level-shifts it and outputs it as a first clock; And a main delay unit delaying the first clock to a time delay amount corresponding to the time delay amount of the clock buffer and outputting the second clock as a second clock, and having a plurality of delay sets connected to the first clock and the second clock. A plurality of shifts for successively shifting by a time delay amount, generating comparison signals that compare the phase of the first clock with the phase of the shifted second clocks, and outputting an internal clock synchronized with the external clock; A delay set group having an output node and the first clock is provided to the main delay unit in a first operation mode in response to a logic state of the comparison signals, and after the second operation mode, the first clock is provided after a special delay. It is provided with a delay synchronization circuit including a monitoring unit for performing a delay hopping operation for power saving by.

According to another aspect of the present invention for achieving the above object, the internal clock generation circuit applied to the semiconductor memory device for accessing data in synchronization with the external clock; A clock buffer which receives the external clock and adjusts and level-shifts it and outputs it as a first clock; A main delay delaying the first clock to a time delay amount corresponding to a time delay amount of the clock buffer and outputting the second clock as a second clock, and delaying the first clock and the second clock for a predetermined unit time, respectively; A unit delay set having an output node for generating a phase comparison signal representing a phase match between one clock and a second clock delayed during the unit time and outputting an internal clock, and an interval delay set in which a plurality of unit delay sets are cascaded. Each of the at least two interval delay set group for generating a phase comparison signal, and in order to reduce power consumption in response to the phase comparison signal and the phase comparison signal in the first operation mode, the first clock is the main clock; The first clock is provided to the delay unit, and after the second operation mode, the first clock is After the delay by a predetermined multiple of the delay amount is provided to the main delay in the second delay mode in the interval delay set located in front of the internal clock generated in the interval delay set located in the predetermined second position in the interval delay set group And a delay synchronizing circuit including a monitoring unit which causes the operation of the unit delay sets in the interval delay set located at the rear end to be blocked by being generated in phase synchronization with the external clock.

Here, the monitoring unit has a special delay having a time delay amount equal to the time delay amount of the interval delay set as the number of the interval delay set in order to control the delay hopping operation in the interval delay set, and includes the first clock. To the receiving end of the first clock and to the outputs of the cascaded special delay to provide the first clock directly to the main delay or to provide the first clock to the main delay after a predetermined multiple of the time delay amount of the interval delay set. Combining a plurality of switches corresponding to each other and the logic state of the phase comparison signal and the interval phase comparison signal to generate switching signals for opening and closing the plurality of switches and to correspond to the generated switching signals to the plurality of switches. Including a switching controller This is preferable also.

The method for generating an internal clock phase locked to an external clock in a circuit having first and second synchronization delay lines each including a plurality of unit delays may include: an internal clock phase locked to the external clock; Immediately after being output from the n-th unit delay line of the line, the internal clock is continuously output from the nm-th unit delay unit and the operation of the devices installed at the later stage is blocked. Here, m and n are natural numbers of at least 2, and m is a number smaller than n.

According to still another aspect of the present invention, a method for generating a phase of an internal clock to be supplied to a destination in synchronization with a phase of an external clock includes: receiving and setting an external clock having a frequency relatively lower than a frequency of a set operating range. Even if the internal clock synchronized with the number of taps of the unit delay unit cannot be obtained, the internal clock phase-locked to the external clock is obtained by performing the frequency extension operation by monitoring the last switching signal. The method further comprises that, immediately after the internal clock is output from the predetermined unit delay unit of the second synchronization delay line, the internal clock synchronized with the external clock is continuously continued again in the unit delay unit located at a predetermined front end therefrom. Output, so that the operation of the elements installed at a later stage can be further blocked.

1 is a block diagram showing a conventional synchronous semiconductor memory device.

2 is a block diagram of an internal clock generation circuit in accordance with one embodiment of the present invention, applicable to FIG.

FIG. 3 is a detailed view of the internal clock generation circuit of FIG. 2, which is composed of the combination of FIGS. 3 (a) to 3 (e).

4 is a detailed circuit diagram of a clock buffer 310 of FIG. 2.

5 is a timing diagram of signal waveforms appearing at each terminal of FIG.

6 is a detailed circuit diagram of the main retarder 320 of FIG.

7 is a detailed circuit diagram of the monitoring unit 400 in FIG.

8 is a timing diagram of signal waveforms appearing at each terminal of FIG.

9 is a timing diagram of signal waveforms presented for explaining the detailed operation of the internal clock generation circuit according to FIG.

10 is a block diagram of an internal clock generation circuit in accordance with another embodiment of the present invention applicable to FIG. 1 and improving low frequency margin.

FIG. 11 is a detailed circuit diagram of the last switching signal detector 370 of FIG.

12 and 13 show operating timings according to the operating methods of FIG.

14 is a detailed circuit diagram of the monitoring unit 400-1 in FIG.

15 (a) and 15 (b) are timing diagrams of signal waveforms presented for explaining the detailed operation of the internal clock generation circuit according to FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Components that perform the same function in each other in the accompanying drawings are labeled with the same or similar reference numerals or names for convenience of understanding even if in different drawings. In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details. In addition, the operation of MOS transistors so well known in the art, the output logic of various gates such as NAND gates, and the operation of general digital logic circuits are not described in detail in order not to obscure the subject matter of the present invention.

2 is a block diagram of an internal clock generation circuit applicable to FIG. 1 and in accordance with one embodiment of the present invention. Referring to FIG. 2, an internal clock generation circuit 30 including a clock buffer 310 and a delay synchronization circuit (DLL) 300 is shown. The delay synchronization circuit 300 includes a main delay unit 320, a delay set group 370, and a monitoring unit 400. The delay set group 370 includes a unit delay set 350 and a plurality of interval delay sets 360-i (i is a natural number of two or more). The clock buffer 310 converts an external clock CLK (or system clock) having a TTL level provided by a microprocessor or DRAM controller into a signal level used in a semiconductor memory device, for example, a CMOS level, and outputs the first clock BD. The main delay unit 320 has a time delay amount corresponding to the time delay amount of the clock buffer 310 and outputs a second clock D1. The unit delay set 350 receives the input clock SD of the first clock BD, the second clock D1, and the main delay unit 320, and the second clock D1 and the input clock for a preset unit time. Output for outputting the internal clock PCLK synchronized with the external clock CLK while generating a phase comparison signal T2 indicating the phase matching between the first clock BD and the second clock D1 delayed for the unit time while simultaneously delaying the SD. Has node D1 '. One interval delay set 360-1 is configured in a configuration in which a plurality of unit delay sets 350 are cascaded, and generates an interval phase comparison signal T6. The monitoring unit 400 selects the first clock BD in the first operation mode in response to the phase comparison signal T2 and the interval phase comparison signals T6, T10, T14, and T18 in order to reduce power consumption in the circuit. After the second operation mode, the first clock BD is provided to the input terminal of the main delay unit 320 by a predetermined multiple of the time delay amount for one interval delay set 360i. The internal clock generated at the predetermined interval set in the delay set group 370 is generated at the interval delay set located at the front end so that the operation of the unit delay sets in the interval delay set located at a later stage is blocked. do. In the drawing, the first clock BD inverted by the first clock BD and the phase inverting inverter 322 is a unit delay set 350 and an interval delay set in the delay set group 370 for the purpose of controlling switching of a transmission gate. (PDS) are all applied to 360-1, 360-2, 360-3, 360-4.

Details of the internal clock generation circuit 30 in FIG. 2 are shown in FIG. 3, which is composed of the combinations of FIGS. 3 (a) to 3 (e). In addition, the detailed circuit of the clock buffer 310 of FIG. 2 is shown in FIG. 4, and FIG. 6 is a detailed circuit diagram of the main delay unit 320 in FIG. 2, FIG. 7 is a detailed circuit diagram of the monitoring unit 400 in FIG. 2, and FIG.

First, referring to FIG. 4 to explain an exemplary detailed configuration and operation of the clock buffer 310 shown in FIG. 2 or FIG. 3 (a), a TTL level external clock CLK is used for a synchronous DRAM. A clock pulse width for outputting an autoclock as the first clock BD by adjusting a duty cycle of the level-converted clock to provide a smoothing of the phase synchronization operation. The adjusting unit 310-2 is shown. In the initial operation, since the complementary power-on reset voltage VCCHB is applied at a high level until the power supply voltage Vcc reaches the set level, the PMOS transistor PM1 in the level converter 310-1 is turned off and the NMOS transistor NM3 is turned on. Node N1 to a low level, for example a ground level. After the power supply voltage Vcc reaches the set level, since the complementary power-on reset voltage VCCHB is applied at the low level, the PMOS transistor PM1 is turned on and the set operation is performed. In performing the operation, the gate of the NMOS transistor NM1 in the level converting unit 310-1 is provided with a reference voltage VREF corresponding to half of the power supply voltage Vcc, and the external clock such as waveform CLK of 5 is also applied to the gate of the NMOS transistor NM2. When CLK is applied, waveforms such as waveform N1 in FIG. 5 are level-converted to node N1 by the action according to the comparison circuit configuration as shown. The output waveform N1 of the level converting section 310-1 is pulse width adjusted by an action according to the circuit configuration of the clock pulse width adjusting section 310-2, and appears as a waveform BD of FIG. Each inverter I in the clock pulse width adjusting unit 310-2 has a configuration in which the PMOS transistor PM4 and the NMOS transistor NM4 are connected, and the capacitors C1 and C2 composed of the resistor elements R1 and R2 and the P and N-type transistors are RC. Reserved for delay. At node N2, waveform N1 of node N1 is inverted by the inverter to appear as waveform N2 in FIG. 5, and at node N3, waveform where waveform N2 is delayed by the interval DQ is displayed as waveform N3 in FIG. 5, and output of NAND gate 310-3 The NAND response waveforms of the waveform N2 and the waveform N3 are displayed as the waveform N4 at the node N4. As a result, the waveform BD of FIG. 5 appears in the output terminal BD of the output inverter 310-4, which is referred to as the first clock BD. The frequency of the first clock BD may be designed to about 150MHz.

Referring to FIG. 6 to describe an exemplary detailed configuration and operation of the main delay unit 320 shown in FIG. 2 or FIG. 3 (a), a plurality of inverters 32-1, 32-2 to 32-14 And capacitors C1, C2 consisting of resistors R1, R2 and P and N-type transistors are provided for RC delay. In this case, the delay time of the main delay unit 320 may be adjusted by changing the metal layer which is connected to the resistor elements and the capacitor by patterning or fusing the provided fuse device. In the present embodiment, the total delay time amount of the main delay unit 320 is adjusted to the time delay amount of the clock buffer 310, that is, the time delay amount equal to the interval DQ of FIG. As a result, the main delay unit 320 outputs the second clock D1 delayed by at least 2DQ through the output terminal MD.

Referring to FIGS. 3 (a) to 3 (e) to describe the detailed configuration and operation of the unit delay set (UDS) 350 and the section delay set (PDS) 360i of FIG. 2, the unit delay set 350 And a first unit delay unit 322-1 configured to receive the second clock D1 and delay output for a set unit time by receiving the second clock D1, and a NAND gate N11 and an inverter I11. The second unit delay unit 332-1 which receives the first clock D1 ', which is SD, and delays the output for a set unit time, and compares the phase of the second clock D1 with the phase of the first clock BD to compare the phase comparison signal T2. A phase detector 330-1 for generating and outputting a switching enable signal F1 upon phase matching, and a transfer switch 340 for providing the first clock D1 'as an internal clock PCLK in response to the switching enable signal of the phase detector 330-7. It consists of -1. The phase detector 330-1 includes first and second transfer gates S1 and S2 in which the PMOS and the EnMOS transistors are coupled to each other so that the level is reduced during transmission, and the inverters I1 and I2 configuring the first latch, It consists of inverters I3 and I4 which comprise two latches, inverters I5 and I6 for inversion, and NAND gates N1 and N2. Gates of the PMOS and ENMOS transistors in the first and second transfer gates S1 and S2 receive the inverted clock / BD of the first clock BD, and gates of the NMOS and PMOS transistors receive the first clock BD. Receive. The input of the transmission gate S1 becomes the second clock D1 delayed by the unit of m (where m is a natural number of 1 or more). The NAND gates N1, N2, and the inverter 16 form a carry generation unit, which receives the output Lm of the second latch and the carry information Tm applied to the carry input terminal, and enables the switching enable signal only when the logic is constant. The phase comparison signal Tm + 1 indicating whether phase coincidence between the output Dm and the BD clock is generated as a first or second logic level, for example, high or low, by activating through Fm. The transfer switch 340-1 includes an inverter I7 connected to the enable terminal F1 and a transfer gate S3 in which a PMOS and an NMOS transistor are coupled to each other. Inverters I10 and I11 in the first and second unit delay units 322-1 and 332-1, respectively, are made of a combination of a PMOS transistor and an EnMOS transistor, respectively, and have a time delay of about tens to hundreds of nanoseconds (nS). It is a delay inverter having a time delay amount of several times to several tens of times more than a conventional inverter having a quantity. Here, since the interval of the set unit time of the first unit delayer 322-1 and that of the second unit delayer 332-1 should be identical to each other, the unit delay amount is the same. The NMOS transistors Q1 and Q2 are turned on only for a predetermined time by the complementary power-on reset voltage VCCHB applied to the gate terminal during the initial power-on operation, thereby making the input node of the first and second latches low or ground level. It initializes the operation of the latch. The phase comparison signal T2 output from the inverter I6 of the carry generation unit 350 in the unit delay set 350 is applied to the monitoring unit 400 and to the phase detector 330-2 in the section delay set 360-1 provided at the rear end. For example, if the phase of the second clock D1 coincides with the phase of the first clock BD immediately after the initialization of the first and second latches is completed, the phase comparison signal T2 output from the phase detector 330-1 And the logic level of the switching enable signal F1 transitions from high to low level, so that the transmission gate S3 is turned on so that the clock appearing on the node D1 'is transmitted as the internal clock PCLK. However, if the phase of the second clock D1 and the phase of the first clock BD do not coincide, the logic levels of the phase comparison signal T2 and the switching enable signal F1 output from the phase detector 330-1 are high levels, respectively. And the transmission gate S3 remains turned off so that the clock appearing on the node D1 'is not transmitted as the internal clock PCLK. Meanwhile, the other inputs of the NAND gates N10 and N11 are connected to the power supply voltage Vcc.

The detailed configuration of the interval delay set 360-1 is shown with reference to FIG. 3 (b). The interval delay set 360-1 has a configuration in which a plurality of unit delay sets 350 are cascaded as shown in FIG. 3 (a), and the interval phase comparison signal T6 is generated at the last stage of the connection. have. That is, the interval delay set 360-1 includes four first units configured to be identical to the NAND gate N10 and the inverter I10 and to receive the second clock D1 delayed by a predetermined multiple of the unit time, respectively, and output the delayed unit by the unit time. Four second units having the same delay units 322-2 to 322-5, NAND gates N11, and inverter I11 and receiving the first clock D1 'delayed by a predetermined multiple of the unit time, respectively, and delaying the respective outputs by the set unit time. Phase comparison signals T3 by comparing the phases of the second clocks D2, D3, D4, and D5 which are sequentially increased by a predetermined multiple of the unit time with the unit delays 332-2 to 332-5 and the phases of the first clock BD. Four phase detectors 330-2, 330-3, 330-4, and 330-5 that output T4, T5, T6, and switching enable signals F2, F3, F4, F5, and the four phase detectors 330-. It consists of four transfer switches 340-2 to 340-5 connected to 2-5 respectively.

FIG. 3 (b) shows an example in which four unit delay sets 350 as shown in FIG. 3 (a) are configured in the section delay set 360-1. In the drawing, the output D5 of the first unit delay unit 322-4 installed at the front end is applied to one input terminal of the NAND gate in the first unit delay unit 322-5, and the first unit delay unit 322 installed at the front end is applied to the other input terminal. The phase comparison signal T2, which is a carry output of the phase detector 330-1 connected to the first unit delay unit 322-1 located at a predetermined front end of -4, is applied to the internal clock PCLK after the second operation mode. The operation of the first unit delay unit and the corresponding phase detector in the unit delay set provided after the specific unit delay set to be output is prohibited. Similarly, an output D5 ′ of the second unit delay unit 332-4 provided at the front end is applied to one input terminal of the NAND gate in the second unit delay unit 332-5, and the second unit delay installed at the front end of the other unit delay unit 332-5. The phase comparison signal T2, which is a carry output of the phase detector 330-1 connected to the second unit delayer 332-1 located at a predetermined front end of the device 332-4, is applied to the internal clock after the second operation mode. The operation of the second unit delay unit in the unit delay set provided after the specific unit delay set outputting the PCLK is prohibited. For example, if a phase match is detected by the phase detector 330-1, the phase comparison signal T2 is at a low level. Accordingly, the other input of the NAND gate in the first and second unit delayers 322-5 and 332-5 is at a low level. Since the outputs D6 and D6 'are fixed at a low level, the operation of the unit delay set in the interval delay set provided at the rear end is not useful, and the output of the corresponding first and second unit delayers is actually high to low level. It is fixed at the low level rather than transition, so there is little power consumption at the rear end. In the present embodiment, the first and second unit delay units are composed of NAND gates and inverters that generate NAND responses, which are different from those of the related art, for realizing power saving. The NAND gate is merely implemented by way of example in this embodiment, and can be changed by other logic elements, for example, by the configuration of the Noah gate or the combination of the Noah gate and the inverter. The term first synchronization delay line 322i is often used when the first unit delayers are collectively referred to, and the term second synchronization delay line 332i is often used when the second unit delayers are also referred to collectively. will be.

Referring to FIGS. 3 (c), 3 (d), and 3 (e), only the connection positions are different, and the detailed configuration is the same as that of the delay set 360-1. -3, and 360-4 are shown in turn. Although the interval delay sets are separately named in the drawings, this is for convenience of description and for simplicity to explain the function and operation of the monitoring unit 400 which performs the core functions of the present invention. Based on the above descriptions, when the drawings 3 (a)-(e) are connected as shown in FIG. 3, the overall connection relationship between the unit and the interval delay set will be more clearly understood. The monitoring unit 400 will now be described in detail.

Referring to FIG. 7, the detailed circuit of the monitoring unit 400 in FIG. 2 or 3 (a) is shown as an example. In FIG. 7, the monitoring unit 400 controls the time delay amount of the first clock BD in response to the gating output of the phase comparison signal T2 and the interval phase comparison signals T6, T10, T14, and T18. Allow delay hop operation to occur within the interval delay set 360i. To this end, the monitoring unit 400 has a special delay 410i having a time delay amount equal to the time delay amount for one of the section delay sets 360i in proportion to the number of the section delay sets 360i, and further comprising a first clock according to the gating output. A plurality of switches and a switch control unit 470 for determining the delay path of the BD is provided. The special delays 410-1, 410-2, and 410-3 respectively include two inverters 411 and 412, two resistors 413 and 414 connected between the power supply voltage and ground of the inverter 411, and blood connected to the output terminal of the inverter 411. N-type capacitors 415 and 416. The resistors 413, 414 and capacitors 415, 416 determine the RC time constant, thereby adjusting the time delay amount of the special delay. The special delay 410i has the same amount of time delay as the time delay amount of the section delay set 360i.

In FIG. 7, the plurality of switches and the plurality of switches in the switch control unit 470 include the passing output terminal NO1 of the first clock and the output terminals NO2 of the special delays 410-1, 410-2, and 410-3 that are cascaded. Main switches 431, 432, 433, and 434 respectively connected to NO3, NO4, bypass gate switch 430 for bypassing the first clock BD as an output SD of the output stage, and a plurality of sub-switches 437, 438, 439, 440, 449 and input gate switch 405 and output gate switch 455. The switching controller in the plurality of switches and the switch controller 470 combines the logic states of the phase comparison signal T2 and the interval phase comparison signals T6, T10, T14, and T18 to the main switches 431, 432, 433, and 434; To generate switching signals A12, A13, A14, A15, and A16 for selectively opening and closing the NOA gate switch 430 and correspondingly applying them to the plurality of sub-switches 437, 438, 439, 440, and 449 , Inverters 420-423, NAND gates 425-428, 406. In addition, the switching control unit may include the first to fourth latch units L1 to L4 respectively configured by the two inverters 441 and 442, the sub switch control unit including the NAND gate 435 and the inverter 436, the discharge transistors 451, 453, 456, and the like. And a discharge section including an inverter 450 and a NAND gate 452.

In FIG. 7, the reason why three special delays 410i are configured is that four interval delay sets 360i are set to, for example, four in FIG. Of course, it can be added or subtracted according to the resolution depending on the unit delay time of the unit delay unit. In FIG. 7 shown as an embodiment, the first clock BD is commonly applied to one side input of a NAND gate serving as the input gate switch 405 and one side input of a Noah gate 430 serving as a bypass NOR gate switch 430. do. The interval phase comparison signals T6, T10, T14, and T18 are provided to an input of the NAND gate 406 and the inverters 423, 422, 421, 420 in the switching controller. The section phase comparison signals T6, T10, T14, and T18 are phase comparison signals applied from the phase detector 330i located at the far end of the section delay set 360i. The monitoring unit 400 generates a clock SD outputting the first clock BD without delay in the first operation mode to be defined in the following description, and after the second operation mode, sets the first clock BD as one interval delay set. A special delaying first clock SD outputted after a delay of a predetermined amount of time delay for 360i is generated. Accordingly, the internal clock PCLK, which is generated at the predetermined interval located in the delay set group 370, 360i, is generated at the interval delay set 360i-n located at the front end. Therefore, since the internal clock PCLK synchronized to the external clock CLK is moved to the interval delay set at the front end, the operation of the unit delay sets in the interval delay set located at the rear end is interrupted to obtain the internal clock PCLK first. The power saving operation is further performed later.

Referring to FIG. 7 to describe in more detail the operation principle, the bypass switch 430 and the main switches 431, 432, 433, and 434 are S0, S1, S2, S3, and S4, respectively. The conditions of the switch turn-on operation according to the logic state of the phase comparison signal T2 and the interval phase comparison signals T6, T10, T14, and T18 are shown in Table 1 below.

TABLE 1

For example, the monitoring unit 400 of FIG. 7 performing the switching operation according to the logic state shown in Table 1 may be configured to set the logic state of the phase comparison signal T2 and the interval phase comparison signals T6, T10, T14, and T18 for a predetermined time. If all of them are received as logic level "H", and after a certain time, only the logic states of the section phase comparison signals T10, T14, and T18 are received as logic level "L", the monitoring unit 400 receives the first clock BD of FIG. The waveform is converted to SD according to the timing and output. 8 is a timing diagram of signal waveforms appearing at each terminal of FIG. 7 and is an example according to the above condition. The overall operation of the circuit of FIG. 2 will be described below. First, a specific operation of the monitoring unit 400 will be described with reference to FIGS. 7 and 8.

First, the discharge transistor 456 is turned on only for a predetermined time by the complementary power-on reset voltage VCCHB applied to the gate terminal during the initial power-on operation. Accordingly, the node A21 is at the low level, that is, the ground level, and the sub switches 437, 438, 439, 440, and 449 are all turned on, and the nodes A17-A20 are at the high level. Then, the outputs of the first to fourth latch parts L1 to L4 are all initialized to the high state, and the outputs of the NAND gate 435 are at the low level. After this initial operation, the discharge transistor 456 is turned off. Subsequently, when the reclocked CLK is received in the clock buffer 310 of FIG. 3 with the waveform of FIG. 8, the first clock BD of the waveform of FIG. 8 applied to FIG. 7 during the first period of the external clock CLK is in phase. The logic states of the comparison signal T2 and the interval phase comparison signals T6, T10, T14, and T18 are all received as logic level “H” and are output without delay along the first path K1 since only the switch S0 in FIG. 7 is opened. This is the first pulse P1 seen in waveform SD of FIG. That is, in this case, the logic “L”, which is the output of the NAND gate 406 of FIG. 7, and the logic state of the first clock BD are provided to the Noah gate 430, so that the output of the Noah gate 430 is responsive to the arrow symbol a1 in FIG. It is shown as waveform A16 of 8 degrees, which is applied to the other input terminal of the output NOR gate 455. At this time, as the output of the NAND gate 452 becomes “H” and the discharge transistor 453 is turned on, the node A11 serving as an input terminal of the NOR gate 455 becomes “L”. Thus, the Noah gate 455 outputs the pulse P1 in response to the arrow a2 in FIG. 8 as the clock SD. Then, during the second cycle (2'nd) of the external clock CLK, the logic state of the interval phase comparison signals T10, T14, T18 is provided changed to a logic level "L". However, just before the logic state of the interval phase comparison signals T10, T14, and T18 is changed to the logic level “L”, a waveform BD as shown in FIG. 8 is generated for the second time, which is also the first path through the switch S0 of FIG. Output without delay along K1. Thus, the second pulse P2 shown in waveform SD of FIG. 8 is shown. That is, since the logic "L" which is the output of the NAND gate 406 of FIG. 7 and the logic state of the first clock BD are provided to the Noah gate 430, the output of the Noah gate 430 is in response to the arrow symbol a3 in FIG. Appears as waveform A16, which is applied to the other input of the output NOR gate 455. The node A11, which is an input terminal of the NOR gate 455, becomes “L”, and the NOR gate 455 outputs the pulse P2 corresponding to the arrow symbol a4 of FIG. 8 as the clock SD. By the logic states of the interval phase comparison signals T10, T14, and T18 changed during the second cycle, the noble operation of the monitoring unit 400 begins to appear as a ratio in the third cycle.

The NAND gate 406 of FIG. 7 outputs high logic according to the logic states of the interval phase comparison signals T10, T14, and T18 changed during the 2'nd cycle, and the sub-switch 449 is driven by the high logic of the phase comparison signal T2. Because of maintaining turn-on, the output of the NAND gate 406 is passed to node A10, which transitions from logic "L" to logic "H", as shown by waveform A10 in FIG. Accordingly, the other input of the NAND gate 405 is provided high, and the logic of the node NO1 transitions low when the logic of one input, that is, the logic of the first clock BD is applied high. In other words, the NAND gate 405 becomes an inverting device capable of outputting a logic low when the input is high in this case. Further, the first path K1 is now closed because the bypass switch S0 outputs only the logic "L", i.e., the cutoff state, due to the logic "H" of waveform A10. In other words, the bypass operation stops. Importantly, the switch S2 is now opened by the logic state of the interval phase comparison signals T10, T14, T18 that are changed during the second cycle. The reason why only the main switch S2 is opened is because the sub-switch 438 transfers the low logic shown at the output node A14 of the NAND gate 427 to the output node A19 of the sub-switch 438. As a result, the second path K2 is opened so that the logic of the node A11 depends on the node NO2. On the other hand, the logic of node A21 is now transitioned high according to the change of node A19. Then, the sub-switches 437-440 are blocked so as not to monitor the logic state of the section phase comparison signals from now on. This is because the monitoring operation for power saving has already been completed. The logic of the node A11 and the logic of the node A16 are applied together to the output NOA gate 455 to finally output the pulse TP in response to the arrow a8 in FIG. 8 as the clock SD. Note that the clock SD does not output a pulse FP. The sub-switches 437-440 are all shut off, but the main switch S2 is kept open by the latch operation of the third latch part L3 to transfer the logic appearing at the node NO2 to the node A11. The pulse period of the clock SD to appear periodically after the pulse TP is the same as the period of the external clock CLK. As a result, the monitoring unit 400 performs the same function as outputting the first clock BD delayed by the delay FSD time of the first special delay 410-1 when the third pulse is output. The above operation is an example of assuming that the logic states of the interval phase comparison signals T10, T14, and T18 are low, and may vary according to Table 1 when the logic states are different.

By the unique operation of the monitoring unit 400 as described above, the internal clock PCLK generated in the section delay set 360-2 in the delay set group 370 is generated in the section delay set 360-1 located at the front end. Here, the first operation mode refers to an operation from the beginning of the initial state in the circuit of FIG. 2 until the first phase synchronization between the external clock CLK and the internal clock PCLK is performed. It is used to output 1 clock BD without delay. The second operation mode indicates a time point after the phase synchronization is performed, and after the second operation mode, the clock SD delays the first clock BD by a predetermined multiple of the time delay amount for one interval delay set 360i. The output becomes the special delaying first clock, and phase synchronization occurs again by another phase detector.

The overall operation of FIG. 3 in which the circuit of FIG. 2 is embodied as an example will be described with reference to FIG. 9. FIG. 9 is a timing diagram of the signal waveforms presented to explain the detailed operation of the internal clock generation circuit according to FIG. 3, and shows the effective internal clock PCLK (V1) synchronized with the fourth clock of the external clock CLK after the fourth cycle. Successive generations are shown by way of example. When the external clock CLK, such as the waveform CLK of FIG. 9, is applied to the clock buffer 310 of FIG. 3 (a), the clock buffer 310 having the detailed configuration as shown in FIG. 4 has a level converter 310-1 and a clock pulse. By having the width adjusting unit 310-2, the first clock BD that is the same as the first pulse of the waveform BD of FIG. 9 is output. The first clock BD is a clock in which the external clock CLK is level-converted and the duty ratio is adjusted, and is a clock delayed by the amount of time delay DE1 compared to the external clock CLK. The first clock BD is applied to the monitoring unit 400 and output as a clock SD. At this point in time, the first operation mode is not terminated, that is, the state before the phase match exists, so that the clock SD immediately bypasses the first clock BD. The main delay unit 320 receiving the clock SD outputs a second clock D1, which is the same as the waveform D1 of FIG. 9, to an output terminal. Here, the main delay circuit 320 having a detailed configuration as shown in FIG. 6 outputs a second clock D1 having a time delay amount DE2 equal to the time delay amount DE1 of the clock buffer 310 compared to the clock SD. That is, in FIG. 9, it can be seen that the rising edge of the second clock D1 is delayed by 2 x DE1 from the rising edge of the outer clock CLK. The second clock D1 is applied to the first unit delayer 322-1 in the first synchronization delay line 322i, delayed by the unit time UD, and then output as waveform D2 of FIG. Subsequently, in the first unit delay units 322-2 322-3 and 322-4 322-5 to 322-16 in the first synchronization delay line 322i of FIG. 3, the corresponding waveforms D3-D17 shown in FIG. It can be seen that it may appear. On the other hand, the clock SD bypassed by the first clock BD becomes D1 ', which is the other input of the second unit delay unit 322-1 in the second synchronization delay line 332i of FIG. 3 (a). That is, up to this point, the waveforms of the first clock BD, the clock SD, and the D1 'are all substantially the same. The clock SD is applied to the second unit smoker 332-1 and delayed equally by the unit time UD (about 0.4 mu s) and then output as waveform D2 'of FIG. Similarly, the corresponding waveform D3 'shown in FIG. 9 in the second unit delays 332-2, 332-3, 332-4, and 332-5 to 332-16 in the second synchronization delay line 332i in FIG. It can be seen that -D9 'may appear to be sequentially shifted. Here, if the clock SD which is the first clock BD is in phase with the output clock D9 of the first unit delayer 322-8 as in the timing example shown in FIG. 9, the phase shown in FIG. Detector 330-9 will detect this. Here, phase detection means that the node L9 of the phase detector 330-9 is changed from logic high to logic low. That is, the nodes L1-L8 of the phase detectors 330-1 to 330-8 are all changed to logic low after the node L9 of the phase detector 330-9 while maintaining logic high. Accordingly, the phase comparison signal T10 of the phase detector 330-9 of FIG. 3 (c) (actually an interval phase comparison signal) and the switching enable signal F9 transition to a logic low like the corresponding waveform of FIG. In order to clarify the principle of phase detection, the operation of the phase detector 330-9 will be described in more detail. After the clock pulse (second clock D1 has passed through the first unit delay unit eight times) in node D9 of FIG. If this pulse is equal to the first high pulse of waveform D9 in FIG. 9, the high pulse is latched in the first latches I1 and I2 through the first transfer switch S1 which opens in time. The input stage of the first latch is initially initialized to Low and then changes to High, and thus the level of the output stage of the inverter I5 connected to the output stage of the first latch is changed to high logic. However, the high logic cannot be transmitted through the second transfer switch S2 (opened when the first transfer switch is blocked due to the configuration of the switch), which is complementary when the first transfer switch S1 is open. When the second transfer switch S2 is opened in response to the falling edge of the first clock BD (SD) (in this case, the same time as the falling edge of the waveform D9), the second latch I3 as indicated by the arrow symbol b1 in FIG. The level of the output node L9 of I4) transitions from high to low level. The NAND gate N1 constituting the carry generation section receives the low level of the output node L9 and the high level of the phase comparison signal T9 as an input, thereby generating a high level as the NAND output. The logic high, which is the output of the NAND gate N1, is inverted by the inverter 16 to become logic low. This logic row becomes the output logic of the phase comparison signal T10 (actually an interval phase comparison signal). NAND gate N2 receives both inputs at logic high, providing the NAND output as logic low. This is the logic of the switching enable signal F9. As can be seen from arrows b2 and b3 of FIG. 9, in the period where the logic of the switching enable signal F9 is low, the logics of the other switching enable signals are all high, and the phase comparison signal T10 is low. When the phase comparison signals T11, T12 to T18 after that are all low. When the switching enable signal F9 goes low, only the correspondingly connected transfer switch 340-9 is turned on so that a second clock such as waveform D9 'of FIG. . Here, the second high pulse shown by the arrow symbol b4 of the waveform D9 'is the pulse which comes out after the first clock D1' passes the eighth unit delay. When the generation timing of the inner clock PCLK is closely illustrated in FIG. 9, it can be seen that the timing of the third cycle 3′rd of the outer clock CLK is exactly coincident with the start timing. This allows the internal clock, once phase-locked to the external clock, to be obtained first, but for the operation of power saving it is discarded up to the second pulse IV2 in this embodiment.

As can be seen in the above operation, phase detection compares the clocks D2, D3, D4, D5 to D18 that occur after the second clock D1 passes through the first unit delays to the first clock BD (SD). The output of the internal clock PCLK is generated by the clocks D2 ', D3', D4 ', and D5 which occur after the first clock D1' appearing at the input terminal rather than the output terminal of the main delay unit 320 passes through the second unit delays, respectively. This is done by selectively passing one of ′ to D18 ′ according to the phase detection result. In any case, the basic principle of the phase synchronization using the synchronization delay line that can obtain the internal clock PCLK phase locked to the external clock as described above is that the delay time of the clock buffer 310 and the delay amount of the main delay 320 are the same. Based on having. That is, since the delay amount DE1 and the delay amount DE2 shown in FIG. 9 are equal to each other, the phase delay amount INT1 between the BD and D9 is equal to the phase delay amount INT2 between the external clocks CLK and D9 '.

The operation described above to obtain the first pulse IV1 of the internal clock PCLK is not significantly different from the normal internal clock generation operation except that the first clock BD is bypassed through the monitoring unit 400. However, in this case, since the phase comparison signal T10 is logic low, the operations of the first and second unit delayers 322-13 and 332-13 to the end are blocked. This is because the first and second unit delay units have NAND gates therein. In other words, the NAND gate in the first unit delay unit 322-13 which inputs waveforms T10 and D13 of FIG. The connected inverter outputs only low logic. Accordingly, the first and second latches in the correspondingly connected phase detector do not change the latch output. Accordingly, the unit delay set from the unit delay set to the end in the section delay set 360-3 including the first and second delay units 322-13, 332-13, the phase detectors 330-13, and the transfer switches 340-13 are all included. Operation is blocked. Therefore, power consumption is minimized or reduced in such an operation interruption. As described above, it can be seen that power is reduced by employing NAND gates in the unit delay unit. This effect must be larger as the number of taps of the synchronization delay line increases.

At the timing of FIG. 9, the second pulse IV2 of the internal clock PCLK is generated in accordance with the arrow symbol b7 because the switching enable signal F9 remains low for a certain period. This is attributable to the fact that the monitoring unit 400 of FIG. 3 (a) operates in the same manner as the timing of FIG. 8 to bypass two pulses P1 and P2 and output a special delayed third pulse TP.

Hereinafter, the operation after the second operation mode will be described. As a result of the transition to the low level of the waveforms T10 to 18 of FIG. 9 in the first operation mode, an operation according to the arrow symbol b6 occurs in the monitoring unit 400 to generate the third pulse SDP3 of the clock SD. The pulse SDP3 is the same pulse as the third pulse TP of the waveform SD of FIG. 8, and the detailed process of generating the third pulse is as described above. The main delay unit 320 main delays the pulse SDP3 and outputs the same pulse as the third clock of the waveform D1 of FIG. 9 as the second clock D1. Here, the rising edge of the second clock D1 is delayed by DE2 than the rising edge of the pulse SPD3. The second clock D1 obtained after the second operation mode is applied to the first unit delay unit 322-1 in the first synchronization delay line 322i, delayed by the unit time UD, and output as the third pulse of waveform D2 of FIG. Subsequently, in the first unit delay units 322-2, 322-3, 322-4, 322-5 to 322-16 in the first synchronization delay line 322i of FIG. 3, the corresponding waveforms D3-D17 shown in FIG. It can be seen that it may appear shifted. On the other hand, the pulse SDP3 of the clock SD also becomes D1 'which is the other input of the second unit delay unit 322-1 in the second synchronization delay line 332i of FIG. 3 (a). That is, at this point, the clock SD is out of phase with the first clock BD and integrated with the waveform of D1 'in FIG. The clock SD is applied to the second unit delayer 332-1 and delayed equally by the unit time UD (about 0.4 mu s) and then output as waveform D2 'of FIG. Subsequently, in the second unit delay units 332-2, 332-3, 332-4, 332-5 to 332-16 in the second synchronization delay line 332i of FIG. 3, the corresponding waveforms D3'-D9 'shown in FIG. It can be seen that this may appear shifted in sequence. Here, at the timing shown in FIG. 9, it can be seen that the first clock BD is in phase with the output clock D5 of the first unit delayer 322-4. Accordingly, the phase detector 330-5 shown in FIG. That is, node L5 of phase detector 330-5 is changed from logic high to logic low. Accordingly, nodes L1 through L4 of the phase detectors 330-1 through 330-4 are further changed to logic low after the node L5 of the phase detector 330-5 while all the logic highs are maintained. Accordingly, the phase comparison signal T6 and the switching enable signal F5 of the phase detector 330-5 of FIG. 3 (b) transition to logic low, as shown by the corresponding waveform shown by the arrow 9 in FIG. The logic of the switching enable signal F9 changes from low to high according to arrow b10. The principle of the phase detection of the phase detector 330-5 is the same as the above-described operation. As can be seen from the arrows b9 and b10 of FIG. 9, in the period where the logic of the switching enable signal F5 is low, the logics of the other switching enable long signals are all high, and the phase comparison signal T6 is low. When the phase comparison signals T7, T8 ~ T18 after that is all low. When the switching enable signal F5 goes low, only the correspondingly connected transmission switch 340-5 is turned on according to the arrow b11, and a fourth pulse like the waveform D5 'of FIG. It is provided as a clock PCLK. The timing of generation of the third pulse V1 of the inner clock PCLK in detail in FIG. 9 shows that the timing coincides with the end of the fourth period 4′th of the outer clock CLK. That is, a valid internal clock synchronized with the fifth period of the external clock is obtained as the ratio. In fact, for the operation of power saving, up to the second pulse IV2 of the internal clock is discarded and effectively treated from the third pulse V1. In fact, the time to obtain the third pulse is a time that can be ignored because it is extremely short compared to the time taken to store the data in the data output buffer after applying the address to the memory.

After the second operation mode, the clock SD may be a special delaying first clock output after delaying the first clock BD by a predetermined multiple of a time delay amount for one interval delay set 360i. The phase synchronization is detected again by another phase detector by providing the delaying first clock. This is the delay delay operation unique to the monitoring unit 400 of the present invention. The unit delay in the interval delay set 360-2 including the first and second delay units 322-9, 332-9, phase detectors 330-9, and transfer switch 340-9 having the NAND gate inside by the delay hopping operation. From the set to the unit delay set within the interval delay set 360-3 including the first and second delayers 322-13, 332-13, the phase detectors 330-13, and the transfer switches 340-13, the operation is further deactivated. As such, power consumed in the internal clock generation circuit is further reduced by the function of the monitoring unit 400. This effect increases as the number of taps of the synchronization delay line increases, and increases as the number of unit delay sets in the interval delay set increases.

In the above-described embodiment of the present invention, an internal clock is generated by pulling the internal clock output from the unit delay set in the delay section of the rear section to the front end as necessary, and the operation of the rear end is completely cut off, thereby eliminating unnecessary power. Waste is thoroughly prevented. This, in turn, reduces the overall power consumption of the synchronous semiconductor memory device.

One embodiment of the present invention described above has been described and limited by way of example with reference to the drawings, but the same is possible to those skilled in the art that various changes and modifications can be made within the scope without departing from the technical spirit of the present invention. Will be obvious. For example, it is apparent that, as the case allows, the internal configuration of the interval delay set and the monitoring unit can be changed, as well as the amount and number of delays of the unit delayers can be changed.

In the following, a second embodiment is described according to another aspect of the present invention. As another embodiment, the second embodiment has an internal clock generation circuit for a synchronous semiconductor memory device for increasing the operating margin for a low frequency and minimizing power consumption by having a minimum number of taps for a set clock frequency among other purposes. And more suitable for achieving the method.

Referring to FIG. 10, there is shown a block diagram of an internal clock generation circuit 30-1 in accordance with another embodiment of the present invention that is applicable to the memory of FIG. 1 and improves low frequency margin. The configuration of FIG. 10 further includes PDS 360-n, UDS 350-1, and LSD 370, as compared to the configuration of FIG. different. The PDS 360-n is the same as the internal configuration of the interval delay set 360i shown in the first embodiment, in which each input terminal is correspondingly connected to each output terminal of the PDS 350-4. The internal structure of the UDS 350-1 is the same as the internal structure of the UDS 350, except that only the connected positions are different. Thus, the first unit delay in the UDS 350-1 and the phase detector connected thereto are located at the last stage in the circuit.

The detailed configuration of the last switching signal detector (LSD) 370 in FIG. 10 is shown in FIG. FIG. 11 is a detailed circuit diagram of the last switching signal detector 370 of FIG. 10. The first and second latches LC1 and LC2 of which the inverters are cross-connected to the last delay signal DF output from the first unit delay unit located at the last stage in the circuit. In response, a first transfer switch 372 for transmitting the last phase comparison signal TF to the first latch LC1 and an output terminal of the first latch LC1 operate in a complementary manner to the first transfer switch 372. A second transfer switch 376 is shown for transferring the output of LC1 to the second latch LC2. The inverter 371 inverts the last delay signal DF, and the PMOS transistor 375 has a gate terminal connected to the VCCH to turn on at initial power-on to initialize the output of the first latch LC1 to logic high. The last switching signal SF provided at the output of the second latch LC2 is provided as a logic high or logic low at the CMOS level, where a phase-locked internal clock is not generated in the circuit of FIG. 10 if the last switching signal SF is lower. If it is. As a result, if the last switching signal SF is low, the phase-locked internal clock is set in the case of the circuit of FIG. If there are circuits having the same number of unit delays, i.e. the same number of taps, the additional configuration of FIG. 10 having the configuration of FIG. 11 serves to increase the operating margin for low frequencies.

12 and 13 are operation timing diagrams according to the operation schemes of FIG. 11, and FIG. 12 is an arrow symbol when the last phase comparison signal TF is kept high in the interval of the first pulse of the last delay signal DF. According to a21 and a24, the timing at which the last switching signal SF is generated as high is shown. FIG. 13 shows the timing at which the last switching signal SF continues to be low in accordance with arrows a22 and a25 when the last phase comparison signal TF transitions low in the period of the first pulse of the last delay signal DF. Accordingly, FIG. 12 shows the timing relationship when the internal clock PCLK phase-locked to the external clock CLK is not generated in any second unit delay in the circuit of FIG. FIG. 13 is an external clock already performed before the special delay operation or the timing after the special delay operation is performed to improve the low frequency characteristics when the monitoring unit 400-1 in FIG. 10 monitors the timing of FIG. The timing relationship is shown when the internal clock PCLK phase locked to CLK is generated in any second unit delay in the circuit of FIG.

FIG. 14 is a detailed circuit diagram of the monitoring unit 400-1 of FIG. 10, and additional elements installed to receive the last switching signal SF and improve the low frequency characteristics thereof, as compared with the monitoring unit 400 of FIG. 7 (reference numeral 459, Except for 460, 461, 462, 463, and 465 and the replacement elements 405-1, 464, the configuration of FIG. 14 is the same as that of FIG.

In FIG. 14, when the bypass switch 430 and the main switches 431, 432, 433, and 434 are S0, S1, S2, S3, and S4, the phase comparison signal T2 and the interval phase comparison signals T6, respectively. , T10, T14, T18 and T22, and the conditions of the switch tin-on operation according to the logic state of the last switching signal SF are shown in Table 2 below.

TABLE 2

For example, the monitoring unit 400-1 of FIG. 14 performing the switching operation according to the logic state shown in Table 2 may initially include the phase comparison signal T2 and the interval phase comparison signals T6, T10, T14, T18, and T22. The switch S0 is opened when all logic states of are received as logic level "H" and SF is received as "L". Then, when the SF is received as “H” after a certain time, the low frequency is monitored and the switch S4 is opened. Here, "open" or "open" for a switch indicates that the switch delivers the signal from the input to the output.

15 (a) and 15 (b) are timing diagrams of signal waveforms provided to explain the detailed operation of the internal clock generation circuit 30-1 according to FIG. 10. Hereinafter, an example of improving the low frequency margin and minimizing power consumption will be described with reference to the timing diagram for the operation of FIG. 10. In this case, even when the internal clock is not synchronized with the number of taps of the synchronization delay line set according to the reception of the external clock CLK of the relatively low frequency, the internal clock is synchronized once by the operation of the monitoring unit 400-1. As an example, the delay hopping operation as in the first embodiment is generated to continuously generate the effective internal clock PCLK V1 synchronized with the sixth cycle of the external clock CLK.

It is assumed that a clock CLK of a relatively low frequency is applied to the clock buffer 310 of FIG. 10 as in the waveform CLK of FIG. 15 (a). Here, the low frequency reference of the low frequency clock CLK is the frequency of the clock CLK shown in FIG. That is, the frequency of the clock CLK shown in FIG. 7 is relatively high frequency. When the clock CLK is applied, the clock buffer 310 having the detailed configuration as shown in FIG. 4 has a level conversion section 310-1 and a clock pulse width adjusting section 310-2. A first clock BD equal to the first pulse of is outputted. Here, the first clock BD is a clock that is level-converted and whose duty ratio is adjusted, and is a clock delayed by a time delay amount DE1 compared to the external clock CLK. The first clock BD is applied to the monitoring unit 400-1 and output as the clock SD. Here, the clock SD is that the first clock BD is bypassed as it is without delay, for the following reason. That is, since this time point is within the first cycle of the external clock CLK, the T2, T6, T10, T14, T18, T22, and SF each represent H, H, H. H, H, H, L in turn. Therefore, the bypass switch S0 is opened in accordance with the conditions of Table 2. The main delay unit 320 receiving the clock SD outputs a second clock D1, which is the same as the waveform D1 of FIG. 15 (a), to an output terminal. Here, the second clock D1 is obtained by delaying the clock SD to a time delay amount DE2 equal to the time delay amount DE1 of the clock buffer 310. The second clock D1 is applied to the first unit delay unit 322-1 in the first synchronization delay line 322i, delayed by the unit time UD, and then output as the waveform D2 of FIG. 15 (a). The first unit delays 322-2, 322-3, 322-4 in the first synchronization delay line 322i of FIG. In 322-5 to 322-22, it can be seen that the corresponding waveforms D3-D22 shown in FIG. 15 (a) may be sequentially shifted. Where DF is D23, which is the output of block 350-1 of FIG. On the other hand, it can be seen that the clock SD, in which the first clock BD is bypassed, becomes D1 ′, which is the other input of the second unit delay unit 322-1 in the second synchronization delay line 332i of FIG. 3 (a). The clock SD is applied to the second unit delay unit 332-1 and delayed by the unit time UD equally, and then output as the waveform D2 'of FIG. 15 (a). Similarly, the corresponding waveform shown in Fig. 15 (a) in the second unit delays 332-2, 332-3, 332-4, 332-5 to 332-22 in the second synchronization delay line 332i in FIG. It can be seen that D3'-D22 'may appear to be sequentially shifted.

In the embodiment, the logic of the waveform of D23, which is DF, and the waveform of T23, which is TF is as shown in FIG. 15 (a). Therefore, in the first half of the second cycle, the LSD 370 of FIG. 11 is the falling edge of D23. In response, the transfer gate 376 is opened to transfer the logic “L” latched to the latch LC1 to the latch LC2 at a later stage. As a result, the signal SF appearing at the output terminal SF appears as a logic "H". This is because the external clock CLK is relatively low frequency, and thus the internal clock is not obtained by the number of taps (here 22) of the synchronization delay line. Such a case is shown in FIG. 15 (a) as a timing in which none of the waveforms D3 to D23 are in phase with the second pulse of the waveform BD. In the conventional circuit, since the internal clock synchronized cannot be obtained in the above-described case, it cannot function properly. However, in the present invention, the internal clock synchronized with the circuit configuration shown in FIG. 10 having the monitoring unit 400-1 can be obtained. In that case, it is clear that the low frequency margin is improved.

From now on, the frequency extension operation by monitoring the last switching signal SF is performed in the third cycle, which will be described. In short, this principle simply delays the first clock BD to the maximum amount of delay by the monitoring unit 400-1 to obtain a phase locked internal clock. Arrow K10 in FIG. 15 (a) shows that the clock SD delayed by the time delay amount TSD is obtained as compared with the first clock BD. This is because the monitoring unit 400-1 now receives all of the T2, T6, T10, T14, T18, T22 and SF in H logic. That is, at this time, the switch S4 is opened according to the conditions of Table 2. Accordingly, the first clock BD appearing at node NO4 via Noagate 405-1, special delays 410-1, 410-2, and 410-3 in FIG. 14 is transmitted to node A11 via the switch S4, which is output. The third pulse of the waveform SD of FIG. 15 (a) is obtained by passing through the switch Noah gate 455, which is the clock SD generated as a result of the frequency expansion operation. The point of time when the third pulse of the clock SD is generated is the time when the time delayed amount TSD is added in the period TP with the second pulse. In response to the generation of the clock SD in the third cycle, the main delay unit 320 outputs the second clock D1 reflecting the time delay amount TSD to the output terminal as the third pulse of the waveform D1 of FIG. At the output of the first unit delays connected in series in line 322i, the clocks D2-D23 in which the second clock D1 is sequentially delayed appear as corresponding waveforms D2-D23, respectively. It is finally shown that the waveform D13 is in phase coincidence with the first clock BD in the fourth cycle of FIG. 15 (a) by the frequency extension operation according to the present invention. If the first clock BD is in phase with the output clock D13 of the first unit delayer 322-12 as in the example of the illustrated timing, the phase detectors 330-13 shown in FIG. 3 (d) detect this. do. Here, phase detection means that the nodes L13 of the phase detectors 330-13 are changed from logic high to logic low. That is, the nodes L1-L12 of the phase detectors 330-1 to 330-12 are all changed to logic low after the nodes L13 of the phase detectors 330-13 while maintaining logic high. Accordingly, the phase comparison signal T14 (actually an interval phase comparison signal) and the switching enable signal F13 of the phase detectors 330-13 of FIG. 3 (d) transition to a logic low like the corresponding waveform. The detailed operation relating to the phase detection of the phase detectors 330-13 is the same as that of the first embodiment described above. When the switching enable signal F13 goes low, only the correspondingly connected transfer switches 340-13 are turned on, and the first pulse IV1 such as the waveform D13 'of FIG. 15 (a) shown in the node D13' is first provided as the internal clock PCLK. Here, when the generation timing of the inner clock PCLK is shown in detail in the drawing, it can be seen that the timing coincides with the start point of the fifth period 5′th of the outer clock CLK. As a result, even in the case of low frequency, the internal clock first phase-locked to the external clock was obtained. However, for the operation of power saving it is discarded until the second pulse IV2 in this embodiment.

On the other hand, the waveform SF transitions back from high to low by the logic of the falling edge of the third pulse of the waveform DF (D23) and T14, which transitions low after the time point t1. After obtaining the first pulse IV1 of the internal clock PCLK, the logic "low" of T14 is applied to the NAND gates in the first and second delay units located at the rear end, respectively, so that the first and second delay units 322-17, 332 The unit delay set in the interval delay set 360-4 including the -17, the phase detectors 330-17, and the transfer switches 347-17 to the end are all turned off. Therefore, the power consumption is primarily reduced in this operation blocking similar to the first operation mode of the first embodiment described above.

In order to maximize the power saving operation, an operation having the same identity as the second operation mode of the first embodiment described above takes place within the fifth cycle in accordance with arrow K20 in the timing diagram. However, the actual response of the internal clock thus occurs in the seventh cycle, in which the second pulse IV2, which is phase synchronized with the waveform D13 ', is still provided as the internal clock PCLK. This is because only the switching enable signal F13 remains low until time t3.

If the logic of the waveforms T14 to 23 is all low, the switch S3 is opened according to the conditions of Table 2. Accordingly, the first clock BD appearing at node NO3 via Noah gate 405-1, special delays 410-1, 410-2 in FIG. 14 is transmitted to node A11 through switch S3, which is a noah gate for an output switch. By passing through 455, it becomes the fifth pulse of the waveform SD of FIG. 15 (a), which is the clock SD generated by the second operation mode. The generation time of the fifth pulse of the clock SD is the time when the time delayed amount FSD is added in the period TP with the fourth pulse. According to the generation of the clock SD in the fifth cycle, the main delay unit 320 outputs a second clock D1 reflecting the time delay amount FSD to the output terminal as the fifth pulse of the waveform D1 of FIG. At the output of the first unit delays connected in series in line 322i, clocks D2-U23 in which the second clock D1 is sequentially delayed are shown as corresponding waveforms D2-D23, respectively. By the delay hopping operation, it is now shown that waveform D9 is in phase coincidence with the first clock BD in the sixth cycle of FIG. 15 (a). In other words, the timing that is in phase with the waveform D13 is in phase with the waveform D9.

As in the illustrated timing example, the detection that the first clock BD is in phase with the output clock D9 of the first unit delayer 322-8 is the result of the phase detector 330-9 performing the detection operation. The phase comparison signal T10 (actually an interval phase comparison signal) and the switching enable signal F9 of the phase detector 330-9 of FIG. 3 (c) transition to a logic low like the corresponding waveform. Here again, the detailed operation relating to the phase detection of the phase detector 330-9 is the same as that of the first embodiment described above. When the switching enable signal F9 goes low, only the corresponding transfer switch 340-9 is turned on so that the third pulse V1, which is the same as the waveform D9 'of FIG. 15 (a) shown in the node D9', is internally clocked in accordance with the arrow K30. It is provided as. On the other hand, the switching enable signal F13 transitions to logic high like the corresponding waveform.

When the generation timing of the third pulse V1 of the inner clock PCLK is closely illustrated in FIG. 15 (b), it can be seen that the timing 7′th of the seventh cycle of the outer clock CLK is exactly coincident with the start timing. In other words, a valid internal clock synchronized with the seventh period of the external clock is obtained as the ratio. For power-saving operation, up to the second pulse IV2 of the internal clock in memory is discarded and valid after the third pulse V1. The time taken to obtain the third pulse is a time that can be ignored since it is extremely short compared to the time taken to store the data in the data output buffer after applying an address to the memory.

Section including first and second delay units 322-13, 332-13, phase detectors 330-13, and transfer switches 340-13 having NAND gates internally by a unique delay hopping operation by the monitoring unit 400-1. From unit delay set in delay set 360-3 to unit delay set in section delay set 360-4 including first and second delay units 322-17, 332-17, phase detectors 330-13, and transfer switches 340-17. Is further disabled. As such, power consumed in the internal clock generation circuit is further reduced by the function of the monitoring unit 400-1. This effect becomes larger as the number of taps of the synchronization delay line increases, and as the number of unit delay sets in the interval delay set increases.

In another embodiment of the present invention described above, the operation margin and reliability for the low frequency are guaranteed, and the internal clock is generated by pulling the internal clock output from the unit delay set in the delay section of the rear section as necessary as the front end through the delay hopping operation. Since the operation of the next stage is completely blocked, unnecessary waste of power is prevented. As a result, the overall power consumption of the synchronous semiconductor memory device is reduced, and even when a relatively low frequency is applied, an internal clock synchronized with an external clock can be generated, thereby improving the low frequency margin.

Although the above-described second embodiment of the present invention has been described and limited by way of example with reference to the drawings, the same may be changed and modified in various ways without departing from the technical idea of the present invention to those skilled in the art. It will be obvious. For example, as long as the matter allows, the internal configuration of the interval delay set and the monitoring unit may be different, as well as to change or change the delay amount and the number of unit delays.

As described above, according to the present invention, immediately after the internal clock phase-locked to the external clock is output from the predetermined unit delay unit of the second synchronization delay line, the unit delay unit installed at the predetermined front end of the unit delay unit Since the internal clock is continuously output and the operation of the devices installed at the rear end is cut off, the internal clock is synchronized exactly with the external clock, and the unnecessary power is prevented, thereby reducing the power of the synchronous semiconductor memory device. It has the effect of reducing consumption. In addition, it is possible to have a minimum number of taps for a set clock frequency in addition to minimizing power consumption while obtaining an internal clock more accurately synchronized with an external clock, thereby ensuring an operation margin and reliability at a low frequency.

Claims (24)

A circuit for synchronizing a phase of an internal clock with a phase of a received external clock, the circuit comprising: a clock buffer which receives the external clock and adjusts and level-shifts it and outputs it as a first clock; And a main delay unit delaying the first clock to a time delay amount corresponding to the time delay amount of the clock buffer and outputting the second clock as a second clock, and having a plurality of delay sets connected to the first clock and the second clock. A plurality of shifts for successively shifting by a time delay amount, generating comparison signals that compare the phase of the first clock with the phase of the shifted second clocks, and outputting an internal clock synchronized with the external clock; A delay set group having an output node and the first clock is provided to the main delay unit in a first operation mode in response to a logic state of the comparison signals, and after the second operation mode, the first clock is provided after a special delay. It is provided with a delay synchronization circuit including a monitoring unit for performing a delay hopping operation for power saving by Internal clock generating circuit of ranging. An internal clock generation circuit adapted to a semiconductor memory device that accesses data in synchronization with an external clock, the internal clock generation circuit comprising: a clock buffer which receives the external clock, adjusts and level-shifts it, and outputs the first clock as a first clock; A main delay delaying the first clock to a time delay amount corresponding to a time delay amount of the clock buffer and outputting the second clock as a second clock, and delaying the first clock and the second clock for a predetermined unit time, respectively; A unit delay set having an output node for generating a phase comparison signal representing a phase match between one clock and a second clock delayed during the unit time and outputting an internal clock, and an interval delay in which the plurality of unit delay sets are cascaded. An interval delay set group having at least two sets, each generating an interval phase comparison signal, and in response to the phase comparison signal and the phase phase comparison signals in order to reduce power consumption, the first clock in the first operation mode; Provided to the main delayer, and after the second operation mode, the first clock After the delay by a predetermined multiple of the delay amount is provided to the main delay in the second delay mode in the interval delay set located in front of the internal clock generated in the interval delay set located in the predetermined second position in the interval delay set group And a delay synchronizing circuit including a monitoring unit which causes the operation of the unit delay sets in the interval delay set located at the rear end to be blocked by being generated in phase synchronization with the external clock. The method of claim 2, wherein the monitoring unit has a special delay having a time delay amount equal to the time delay amount of the interval delay set in proportion to the number of interval delay sets in order to control the delay hopping operation in the interval delay set. The slave terminal and the slave end of the first clock to provide the first clock directly to the main delayer or to provide the first clock to the main delayer after a predetermined multiple of the time delay amount of the interval delay set. Combining a plurality of switches connected to the output terminals of the special delay, respectively, and a logic state of the phase comparison signal and the interval phase comparison signal to generate switching signals for opening and closing the plurality of switches and generating the switching signals. Switching control unit correspondingly applied to a plurality of switches Internal clock generation circuit which has the features. The apparatus of claim 3, wherein the unit delay set comprises: a first unit delay unit configured to receive a second clock delayed by a predetermined multiple of the unit time according to an installed position, and to delay output the unit clock during the unit time; A second unit delayer receiving a first clock delayed by one clock or a predetermined multiple of the unit time and outputting a delayed output during the unit time, and a phase of the delayed second clock output from the first unit delayer; A phase detector for generating the phase comparison signal and outputting a switching enable signal in comparison with a phase of the output signal, and a delayed first clock output from the second unit delayer in response to the switching enable signal of the phase detector; And a transfer switch for providing the node as the internal clock. 5. The logic unit of claim 4, wherein the first unit delay unit comprises a logic gate and an inverter connected to an output of the logic gate, and an output of a first unit delay unit installed at a front end is applied to one input of the logic gate, and the other input to the other input. The unit for outputting the internal clock after the second operation mode by applying the phase comparison signal, which is a carry output of the phase detector corresponding to the first unit delay unit located at the front end of the first unit delay unit installed at the front end And an operation of the first delay unit and the phase detector in the unit delay set provided at a rear end of the delay set is prohibited. The method of claim 5, wherein the second unit delay unit comprises a logic gate and an inverter connected to the output of the logic gate, the input of one side of the logic gate is applied to the output of the second unit delay unit provided in the front end and the other input The unit for outputting the internal clock after the second operation mode by applying the phase comparison signal, which is a carry output of the phase detector corresponding to the first unit delay unit located at the front end of the first unit delay unit installed at the front end And an operation of preventing the operation of the second unit delay unit in the unit delay set provided at the rear end of the delay set. 7. The method of claim 6, wherein when the first operation mode indicates a state until the first phase coincides with a phase coincident between any one of the second clocks continuously delayed during the unit time and the first clock. And an operation mode indicating an operation after the first operation mode and outputting an internal clock synchronized with the external clock since a phase coinciding again. 8. The internal clock generation circuit according to claim 7, wherein the delay hopping operation in the interval delay set is performed in the second operation mode. The internal clock generation circuit of claim 8, wherein the main delay unit comprises a plurality of inverters connected in cascade. The internal clock generation circuit of claim 9, wherein the external clock is applied from a memory controller. 11. The internal clock generation circuit according to claim 10, wherein the external clock is applied from a microprocessor having a program processing capability. 6. The internal clock generation circuit as set forth in claim 5, wherein the logic gate is composed of SeaMOS transistor elements generating a NAND response. 5. The phase shifter of claim 4, wherein the phase detector latches an output of the first transmission gate and a first transmission gate configured to pass one of the delayed second clocks in response to the first transition state of the first clock. A first latch, an inverter for inverting the output of the first latch, a second transfer gate for passing the output of the inverter in response to a second transition state of the first clock, and an output of the second transfer gate. Receiving a latch latch and the carry information applied to the output of the second latch and the carry input stage to activate the switching enable signal only when a certain logic and the carry output stage to indicate whether or not the phase match And a carry generator for generating a phase comparison signal as a first or second logic level. The internal clock generation circuit of claim 13, wherein the constant logic of the carry generation unit indicates a state in which the output of the second latch and the carry information are logically low and high, respectively. A digital delay synchronization circuit for generating an internal clock having the same phase as the external clock by being connected to a clock buffer for delay buffering the external clock and outputting the first clock, wherein the first clock is the time delay amount of the clock buffer. A main delay unit which delays by and outputs the second clock; First and second synchronous delay lines each having unit delays connected to each other in a symmetrical structure to sequentially delay and output the first and second clocks by a predetermined unit time interval; A first transmission delayed by a predetermined multiple of the unit time interval in response to a received switching enable signal having a plurality of transfer switches respectively connected between each output terminal of the unit delay units in the second synchronization delay line and an output terminal of the internal clock; A transmission switching unit for transmitting a clock to an output terminal of the internal clock; A phase representing a result of comparing a phase of a delayed second clock of each output terminal between each output terminal of the unit delay units and the enable terminal of the transmission switches in the first synchronization delay line and the phase of the first clock; A phase detector comprising a plurality of phase detectors each generating a comparison signal and outputting the switching enable signals; The first clock is delayed by a predetermined multiple of the predetermined time interval in response to the signals extracted for each constant time period among the phase comparison signals, and is provided to the main delayer to be located at the predetermined second in the second synchronization delay line. Unit delayers located at a predetermined rear end of the unit delay unit for generating the current internal clock by causing the internal clock generated at the output of the unit delay unit to be generated at one of the unit delay units located at the front end and connected thereto And a delay hopping control unit for blocking operation of phase detectors. 16. The logic gate device of claim 15, wherein the unit delay unit is coupled to an output of the logic gate and the logic gate for commonly receiving the phase comparison signal, which is output from the phase delay unit provided at the first front end of the phase delay unit connected to the other side, as the other input. And a unit inverter connected to the rear end of the unit delay unit and a phase detector corresponding to the rear end unit. 17. The circuit of claim 16 wherein the logic gate is a NAND gate. The method of claim 16, wherein the delay jump controller has a special delay having a time delay amount equal to the delay amount of the time interval, and providing the main delay to the main delay after the first clock as it is or by a predetermined multiple of the time delay amount. Switching for opening / closing the plurality of switches by combining a plurality of switches respectively corresponding to the receiving terminal of the first clock and the output terminals of the special delay connected to each other and the logic state of the extracted signals for each predetermined time period. And a switching controller for generating signals and correspondingly applying the signals to the plurality of switches. 17. The MOS transistor of claim 16, wherein each of the plurality of transfer switches has a gate terminal receiving the switching enable signal, a source terminal connected to an output terminal of the unit delay unit, and a drain terminal connected to an output terminal of the internal clock. Circuit, characterized in that consisting of. A method for generating an internal clock phase locked to an external clock in a circuit having first and second synchronous delay lines each consisting of a plurality of unit delays, the method comprising: converting the external clock to a predetermined level to create a first clock Wow; Delaying the first clock by the amount of time delay required to perform the conversion operation to make a second clock; Continuously delaying the first and second clocks by a predetermined unit time interval; Comparing phases of the successively delayed second clocks with the phases of the first clocks to obtain phase comparison signals and switching enable signals indicating the results; Outputting, as the internal clock, a first clock delayed by a predetermined multiple of the unit time interval according to at least one valid signal of the switching enable signals; The second clock is delayed by a predetermined multiple of the predetermined time period in response to the logic state of the signals selected for each of the predetermined time periods of the phase comparison signals, and the second clock is re-created in the first synchronization delay line. By providing the internal clock generated in the unit delay unit located at a predetermined position in the second synchronization delay line to be generated in one of the unit delay units located at the front end of the unit delay unit to generate the current internal clock. And a power saving step of prohibiting the operation of the unit delay units located at a predetermined rear end and the detectors connected thereto to output the phase comparison signals. A circuit for generating a phase of an internal clock to be supplied to a destination in synchronization with a phase of an external clock in a circuit having first and second synchronization delay lines, the method comprising: an external clock having a frequency relatively lower than a frequency of a set operating range Even if the internal clock synchronized with the number of taps of the unit delay unit received and set in the first and second synchronization delay lines cannot be obtained, the internal clock phase-locked to the external clock is performed by performing a frequency extension operation by monitoring the last switching signal. Obtaining; Immediately after the internal clock is once output from the predetermined unit delay unit of the second synchronization delay line, the internal clock synchronized with the external clock is continuously output again from the unit delay unit located at a predetermined front end therefrom. And further preventing the operation of the elements installed at a later stage. A digital delay synchronization circuit for generating an internal clock having the same phase as the external clock connected to a clock buffer for outputting an external clock as a first clock, the digital delay synchronization circuit comprising: delaying the first clock by the amount of time delay of the clock buffer; A main delay outputting as two clocks; First and second synchronization delay lines each having unit delays connected to each other and forming a symmetrical structure in order to continuously output the first and second clocks by a predetermined unit time interval; A first transmission delayed by a predetermined multiple of the unit time interval in response to a received switching enable signal having a plurality of transfer switches respectively connected between each output terminal of the unit delay units in the second synchronization delay line and an output terminal of the internal clock; A transmission switching unit for transmitting a clock to an output terminal of the internal clock; A phase representing a result of comparing a phase of a delayed second clock of each output terminal between each output terminal of the unit delay units and the enable terminal of the transmission switches in the first synchronization delay line and the phase of the first clock; A phase detector comprising a plurality of phase detectors each generating a comparison signal and outputting the switching enable signals; Receives the last phase comparison signal output from the phase detector corresponding to the last delay signal output from the first unit delay unit located at the last stage in the circuit, and receives an external clock having a frequency relatively lower than the frequency of the set operating range. A last switching signal detector for generating a last switching signal of a set logic indicating a case in which a synchronized internal clock is not obtained with the number of taps of a unit delay set in the first and second synchronization delay lines; Frequency extension operation by monitoring the last switching signal to cause the internal click phase-locked to the external clock to be output once from the predetermined unit delay unit of the second synchronization delay line, and then the unit located at the front end therefrom. And a frequency expansion and delay hopping control unit for causing the internal clock synchronized with the external clock to be continuously output again from the delay unit, thereby further blocking the operation of the devices installed at the rear end thereof. 24. The system of claim 22, wherein the last switching signal detector comprises a first phase in response to a last delay signal DF output from first and second latches LC1 and LC2 having an inverter cross-connected and a first unit delay unit located at the final stage. A first transfer switch 372 for transmitting a comparison signal TF to the first latch LC1, and connected to an output terminal of the first latch LC1 and operating complementarily to the first transfer switch 372, and outputting the output of the first latch LC1. And a second transfer switch 376 for transferring to the second latch LC2. A circuit for synchronizing a phase of an internal clock with a phase of a received external clock, the circuit comprising: a clock buffer which receives the external clock, adjusts and level-shifts it, and outputs it as a first clock; And a main delay unit delaying the first clock to a time delay amount corresponding to the time delay amount of the clock buffer and outputting the second clock as a second clock, and having a plurality of delay sets connected to the first clock and the second clock. A plurality of shifts for successively shifting by a time delay amount, generating comparison signals that compare the phase of the first clock with the phase of the shifted second clocks, and outputting an internal clock synchronized with the external clock; And a last switching signal indicating whether a synchronized internal clock is obtained with the set number of taps by receiving a comparison signal corresponding to the last delay signal output from the delay set located at the last stage and a delay set group having an output node. The last switching signal detection unit generated, and the frequency extension by monitoring the last switching signal Operation to cause the internal clock phase-locked to the external clock to be output once in the predetermined delay set of the delay set group, and then the internal clock synchronized to the external clock continuously in the delay set located at the first leading edge therefrom. And a delay synchronizing circuit including a monitoring unit for outputting the control unit to further block operation of elements installed at a rear end thereof.