KR100297513B1 - Method for changing Line-erase in Plasma Display Panel &Apparatus therefor - Google Patents

Abstract

According to the present invention, a write voltage, a scan voltage, and a sustain voltage according to input image data on a panel in which a cell is formed at a portion orthogonal to an address electrode, a scan electrode, and a sustain electrode in order to overcome a luminance difference occurring for each bit line of a screen And a method of displaying an image by applying a line erasing voltage, wherein the input image data is separated bit by bit, the image data of each bit separated by bit is added in units of one line, and then an average value for each bit is calculated. According to the average value of each bit, the line with heavy load decides the line erasing position in the direction of increasing the sustain number, and the line with low load determines the line erasing position in the direction of decreasing the number of sustain, Therefore, the erase position is applied to each bit line by one line or two lines. By erasing the sustain discharge, the line erase position of the cell recorded for each line block of the screen can be changed from line to line to brighten or darken a specific part of the screen, thereby overcoming the difference in luminance of each part of the panel. The present invention provides a method and apparatus for erasing a line of a plasma display panel, which can implement an improved image quality by resolving an abnormal luminance difference according to the load of the present invention.

Description

Method for erasing line of plasma display panel and apparatus therefor {Method for changing Line-erase in Plasma Display Panel & Apparatus therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display system, which is one of flat panel displays, in particular, a position for compensating the luminance of each line according to the load of input image data without erasing recorded lines at the same position at one time. The present invention relates to a line erasing method and apparatus of the plasma display panel capable of compensating for a luminance difference generated for each line by erasing sustain discharge for each line.

For example, a variety of methods are known for the construction of a plasma display panel (hereinafter, abbreviated as 'PDP'). However, in order to achieve a thin shape, a discharge glass is formed by enclosing the surrounding glass of the opposing front and rear glass substrates with a seal glass. It is generally employed to construct an airtight container to accommodate, and the front and rear glass substrates are usually made of low-cost soda-lime glass.

In a color PDP having a small number of display cells, a spacer is used to prevent error discharge or color penetration between adjacent cells, or to withstand pressure differences between panels and to define a distance between electrodes for discharge. A partition wall is formed between the front and rear glass substrates, and the display cell is formed in a space surrounded by the partition wall and the front and rear glass substrates. Phosphor is coated on the inner surface of the display cell, and the phosphor generates visible light of each color by ultraviolet rays generated by the discharge.

In a color PDP having a plurality of fine display cells capable of displaying an image, a rectangular cell array in which cells and electrodes are easily formed is usually employed.

Discharge electrodes are arranged in rows and columns of the panel, and cells are formed at intersections of the row electrodes and the column electrodes.

In the PDP, a discharge is obtained by adjusting a voltage applied between a row electrode and a column electrode of a cell constituting a pixel, and the amount of discharged light is changed by adjusting the number of discharges in the cell.

In general, one frame corresponding to one screen is divided into eight sub-fields, and an output time of one frame is about 16.7 ㎳ (60 Hz) in the case of NTSC.

Each subfield consists of a reset period, an address period, and a sustain period in the address display separation (ADS) method, and a write period in the address while sustain method (AWS). , An address period, a sustain period, and a line erasing period (Erase Period), and there are usually eight subfields in one frame.

The entire screen includes a write pulse and an input video signal that turn on all the cells of the panel to the X-side address electrode (X electrode), Y-side scan electrode (Y electrode), and Z-side sustain electrode (Z electrode) of each cell. Accordingly, a scan pulse for scanning a cell, a sustain pulse for maintaining a discharge, and a line erase pulse for stopping the discharge of a discharged cell are applied to each other to be driven in a matrix.

The gray level required to display the image provides a different length of time for which individual cells are discharged within a given time required to display the entire image, for example 1/30 seconds for an NTSC TV signal. Let's do it.

At this time, the brightness of the screen is determined by the brightness when each cell is driven to the maximum, and in order to increase the brightness, the discharge time of the cell is maintained as long as possible within the given time for constructing one screen. Must be authorized.

As described above, the PDP displays an image by surface discharge by the voltage difference applied to the X electrode on the column side and the Y / Z electrode on the row side.

FIG. 1 is a schematic view showing a general plasma display panel and a driving apparatus thereof, and includes a panel 10, a Y side scan driving circuit 20, a Z side sustain driving circuit 30, and an X side address driving circuit 40. Consists of.

As shown in the figure, scan electrodes Y1 to Ym and Z side sustain electrodes Z1 to Zm are formed on the row side of the panel 10, and address electrodes X1 to Zm on the column side of the panel 10. As shown in FIG. Xn) is formed.

The cells 15 are formed at points where the address electrodes X1 to Xn on the column side, the scan electrodes Y1 to Ym on the row side, and the sustain electrodes Z1 to Zm cross at right angles.

The scan electrodes Y1 to Ym on the row side are independently separated from each other to receive write pulses, scan pulses, sustain pulses, and line erase pulses from the Y-side scan driver circuit 20, and the sustain electrodes on the row side ( Z1 to Zm receive sustain pulses supplied from the Z side sustain driver circuit 30, and address electrodes X1 to Xn on the column side are address pulses synchronized with the scan pulse from the X side address driver circuit 40. It is configured to be authorized.

FIG. 2 is a timing diagram illustrating a method of configuring a screen based on unit cells of the PDP panel of FIG. 1, and includes an address period, a sustain period, and a line erase period.

As shown in the drawing, the unit cell 15 has no wall charge in the discharge cell before the time point? Of the address period. If the write discharge occurs between the address electrode X and the scan electrode Y at the time point? After the write discharge, wall charges are formed on the scan electrode Y and the sustain electrode Z inside the cell.

The write pulse applied to the address electrode X has a pulse width of 2 s or more, which is a time for forming wall charges, and a sustain discharge occurs between the scan electrode Y and the sustain electrode Z at the time point ㉰. .

The wall charges after the sustain discharge at the time point 반대로 are opposite to the wall charges shown at the time point 정전, and electrostatic charges and negative charges are formed. The sustain potential difference between each of the electrodes Y and Z is between the address electrode X and the scan electrode Y. Use a voltage of a potential lower than the difference of the write voltages.

The time points ㉲ and ㉳ represent sustain discharges caused by the sustain pulse, and wall charges at this point of time generate static charges and negative charges as opposed to time point ㉱.

Therefore, one sustain period is from the time point? To the time point?, And the number of discharges during one sustain period is two times.

The line erase discharge occurs at the time V, the pulse width of the line erase pulse is 1 m or less, the voltage is lower than the sustain voltage, and the cell has no wall charge at the time V.

Of course, in a cell without wall charge, no discharge occurs even when a sustain pulse is applied.

3 is a timing diagram illustrating a method of erasing a PDP panel according to the prior art, which will be described below with reference to FIGS. 1 to 2.

If a row of cells arranged in rows and columns of a PDP panel is called one line, the conventional method combines several lines (typically 4 to 8 lines) to record, scan, sustain, and line erase each cell, thereby performing the entire screen. Inject

Here, line erasing means a total erase that erases a plurality of lines at a time for each line block after performing writing, scanning, and sustain operations.

For example, in the case of writing and scanning cells in units of four lines (1 Line to 4 Lines), four lines are sequentially written from one line to four lines after four writing lines are simultaneously discharged. After scanning (scan1 to scan4) and performing sustain for a set time, the method of erasing four lines at the same time is used.

As described above, in the method of writing and erasing for each line block, the voltage level applied to each cell varies slightly depending on the turn-on number of the cells formed along each line, that is, the load amount.

For example, if there are a large number of cells turned on in one line, the voltage applied to each cell due to the parasitic resistance of the electrode and the current flowing through each cell is considerably leveled down than the voltage supplied to the line. Due to the drop, the brightness of each cell is darker than when the line is lightly loaded.

Therefore, in the prior art, when a plurality of lines are erased at the same time after writing the line blocks, scanning the recorded lines sequentially, executing a predetermined sustain period, and deleting a plurality of line blocks at the same time, the luminance difference of each line is severely generated. As a result, there is a problem in that the image quality is somewhat degraded for each bit line.

Accordingly, an object of the present invention is to determine a position to erase sustain discharge for each line of each bit (subfield) in the direction of compensating luminance according to the load of input image data without erasing the recorded lines at the same position at one time. The present invention provides a method and apparatus for erasing a line of a plasma display panel which can further improve image quality by reducing luminance differences generated by lines of each bit by erasing at different positions for each bit line.

1 is a view schematically showing a general plasma display panel and a driving device thereof;

FIG. 2 is a timing diagram illustrating a method of configuring a screen based on unit cells of the PDP panel of FIG. 1.

3 is a timing diagram illustrating a method of erasing a PDP panel according to the related art.

4 is a block diagram showing a line erasing variable device of a plasma display panel according to the present invention;

FIG. 5 is a conceptual circuit diagram illustrating a luminance state of a unit cell according to whether cells in each line of the panel are discharged. FIG. 5A is a diagram illustrating a voltage state applied to each cell when a load is high. FIG. 5B Is a diagram showing the voltage applied to each cell when the load is light,

FIG. 6 is a diagram illustrating a method of erasing cell discharge for each bit line according to an embodiment of the present invention.

7 is a diagram illustrating a method of erasing cell discharge for each bit line according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: PDP control unit (panel control unit) 110: automated small level unit

130: bit separation unit 150: memory

170: memory controller 190: data output unit

210: bit erasing positioning unit 230: erasing position generating unit

250: electrode timing control unit 300: plasma display panel

350: X-side address driver 355: address electrode (X electrode)

370: Y-side scan driver 375: Scan electrode (Y electrode)

390: Z side sustain driver 395: sustain electrode (Z electrode)

SF: subfield (bit)

The line erasing method of the present invention for achieving the above object, applying a write voltage, a scan voltage, a sustain voltage and a line erase voltage to each electrode of the panel according to the input image data, and write period, address period, A method of displaying an image by performing a sustain period and a line erase period:

Every subfield in the line erasing period,

(1) After discharging all the cells by applying a write pulse having a voltage value and a width for discharging all cells between the first electrode and the second electrode, the applied voltage between the first and second electrodes is set to zero. A recording period for accumulating wall charges on the dielectric;

(2) an address period after the write discharge to discharge between the first electrode or the second electrode and the third electrode to erase and write wall charges on the dielectric;

(3) a sustain period in which sustain discharge is performed by applying an alternating voltage between the first electrode and the second electrode after the addressing and using wall charges accumulated on the dielectric; And

(4) After performing the sustain period, the erase position of each line is determined using the average value for each bit according to the input image data, and then the line erasing period is executed while varying the corresponding line for all the cells of the panel. .

In addition, another method of the present invention for achieving the above object, the write voltage, the scan voltage, the sustain voltage and the line erase voltage is applied to each electrode of the panel according to the input image data, the write period, the address period of each subfield In a method for displaying an image by performing a sustain period and a line erasing period,

(1) After discharging all the cells by applying a write pulse having a voltage value and a width for discharging all cells between the first electrode and the second electrode, the applied voltage between the first and second electrodes is set to zero. A recording period for accumulating wall charges on the dielectric;

(2) an address period after the write discharge to discharge between the first electrode or the second electrode and the third electrode to erase and write wall charges on the dielectric;

(3) a sustain period in which sustain discharge is performed by applying an alternating voltage between the first electrode and the second electrode after the addressing and using wall charges accumulated on the dielectric; And

(4) After performing the sustain period, the line erase position is determined according to the average value of each bit according to the input image data, and then the erase position is varied by two lines in the unit line block of the panel. A line erasing period is performed for every subfield.

In addition, in the line erasing apparatus of the present invention for achieving the above object, a panel in which an address, a scan and a sustain electrode are arranged in a row and column matrix form, and a cell is formed at a portion orthogonal to each electrode and each electrode of the panel In a plasma display circuit for generating a write pulse, a scan pulse, a sustain pulse, and a line erase pulse according to a circuit for driving and an input image data and applying them to the cell through each electrode of the panel:

A panel control unit which separates and loads image data input from the outside for each bit and generates recording, scanning and sustain control signals;

A bit-by-bit erasure positioning unit which receives the image data separated for each bit from the panel control unit, calculates an average value by adding bits to each line, and then determines a position to be erased for each line of bits according to the average value of each bit;

An erase position generator for generating an erase position variable signal for each bit line in accordance with an erase position signal output from the bit erase position determiner; And

After generating the cell write, scan, and sustain discharge timing control signals according to the control signal output from the panel controller, an erase variable signal for each bit corresponding to each line output from the erase position generator is provided at the time of erasing the sustain discharge. And an electrode timing controller for generating a control signal for erasing the sustain discharge of the cell at different positions for each line.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a block diagram illustrating an apparatus for changing an erasing position of a plasma display panel according to an exemplary embodiment of the present invention, wherein the PDP controller 100, the bit-by-bit erasure positioning unit 210, the erasing position generating unit 230, and the electrode timing controller 250 are shown. ), A panel 300 and a plurality of electrode driving units 350, 370, and 390.

The PDP control unit 100 receives an automatic small level unit 110 that receives R, G, and B image data for each line according to a predetermined blank signal and a control signal Hsync, Vsync, and CLK. And a bit separator 130 for separating data for each bit (subfield) suitable for driving the PDP from the image data output from the automation small level unit 110, and the image data for each bit output from the bit separator 130. A memory 150 for temporarily storing the memory 150; and a memory controller 170 for outputting and controlling image data stored in the memory 150 by receiving horizontal and vertical synchronization signals Hsync and Vsync according to an external clock signal CLK. And a data output unit 190 which receives image data stored in the memory 150 and outputs the image data stored in the memory 150 to the X-side address driver 350 in accordance with the control signal output from the memory controller 170.

In addition, the bit-by-bit erasure positioning unit 210 receives the image data output through the bit separation unit 130, adds the bits for each line, calculates the average of each bit, and then calculates the average of each bit according to the average value of each bit. A position to be erased is determined for each line, and the erase position generator 230 generates an erase position variable signal for each bit line corresponding to the bit erase position signal output from the bit erase position determiner 210. The electrode timing controller 250 is provided with an erase position variable signal for each line output from the erase position generator 230 according to a control signal output from the memory controller 170 to write-discharge the cell. And a driving timing signal for erasing write discharge to each electrode (X electrode, Y electrode, Z electrode) on the panel.

The panel 300 includes a cell 310 at a point where the address electrodes 355 (X electrodes) on the column side, the scan electrodes 375 (Y electrodes) on the row side, and the sustain electrodes 395 (Z electrodes) cross at right angles. ), And each of the electrode drivers 350, 370, and 390 receives image data output from the data output unit 190 according to an electrode timing control signal output from the electrode timing controller 250. An X-side 350, a Y-side 370, and a Z, which drive the address electrode 355, the scan electrode 375, and the sustain electrode 395, respectively, to record, scan, sustain, and line erase the cell 310 thereon. The side drive part 390 is comprised.

The PDP control unit 100 of the present invention configured as described above separates the data for each bit suitable for driving the PDP from the input image data and loads the data into the X-side address driver 350, and the bit-by-bit erasure positioning unit 210 After receiving the image data from the bit separator 130 of the PDP controller 100, the average value of each bit is calculated, and then the position to be erased for each line of each bit is determined according to the average value.

The erase position generator 230 generates an erase position variable signal corresponding to the erase position signal of each bit output from the bit erase position determiner 210 and outputs it to the electrode timing controller 250. The electrode timing controller 250 outputs the erase position control signal to the Y-side scan driver 370 when generating a signal for controlling the address, scan, and sustain electrodes, thereby erasing the recorded lines line by line.

FIG. 5 is a conceptual circuit diagram illustrating a luminance state of a unit cell according to whether cells in each line of the panel are discharged. FIG. 5A is a diagram illustrating a voltage level applied to each cell when a load is high. FIG. 5B Is a diagram showing the voltage level applied to each cell when the load is light.

As shown in FIG. 5A, when a large number of cells are discharged and a large amount of current flows through the scan electrode (Y electrode) and the sustain electrode (Z electrode), a voltage (180V) applied to the scan electrode of a specific line is a resistance. Due to the virtual resistance of the scan and sustain electrodes (Y, Z) represented and the resistance of each cell represented by a capacitor, a large voltage drop occurs, and the voltage applied to each cell due to the voltage drop is greater than 180 V as in an exemplary embodiment. That's a much lower 158V.

This is because when the load of each cell is high in a particular line, the voltage applied to each cell is low, which causes the luminance of each cell to be relatively low.

In addition, as shown in FIG. 5B in a specific line, when there are few cells to discharge and the current flowing through the scan electrode (Y electrode) and the sustain electrode (Z electrode) is small, the voltage applied to the scan electrode Y of the specific line ( 180V) is a voltage drop is less and the voltage applied to a specific cell is applied to a unit cell of the line is less load than the cell of the load line of Figure 5a is applied to a voltage of 178V as in the embodiment Is higher.

Therefore, the luminance of the cells of the line which are under load is higher than that of the cell of the line which is heavily loaded.

FIG. 6 is a diagram illustrating a method of erasing cell discharge for each bit line according to an embodiment of the present invention, and FIG. 7 is a diagram for erasing cell discharge for each bit line according to another embodiment of the present invention. As shown in FIG. 4, the present invention will be described in more detail with reference to FIGS. 4 and 5.

The bit-by-bit erasure positioning unit 210 of FIG. 4 receives the image data output from the bit separation unit 130 and adds each bit for each blank representing the RGB image data for one line, thereby adding an average value for each bit. To calculate.

In addition, the bit-by-bit erasure positioning unit 210 determines a position to erase the discharge of the discharging cell according to the average value of each bit (sub field SF), and the average value of each bit is previously determined. If it is higher than the set reference value, the bit is heavily loaded as shown in FIG. 5A. In this case, since the luminance of the cell is lowered in the line, the luminance of the cell is determined by determining the erase position in the direction of increasing the number of sustains. In contrast, if the average value is lower than the setting reference value, the bit is less loaded as shown in FIG. The erase position is determined to determine the line erase position of the sustain discharge so that the luminance is somewhat dark.

In the same manner as described above, after calculating and determining a position to erase each line for each bit, the erase position generator 230 outputs an erase position signal for each line.

The erase position generator 230 generates an erase position variable signal for each bit (subfield) line from the erase position signal, and the electrode timing controller 250 generates a cell according to a control signal output from the memory controller 170. The Y-side scan driver 370 receives bit-by-bit erase position data output from the erase position generator 230 at the erase point after writing, scanning, and sustaining discharge of the memory. The discharge of the cell is erased line by line for each bit.

For example, as shown in FIG. 6, when the four lines are bundled and written and scanned, the X-side address driver 350 is connected to the data output unit 190 according to the control signal of the electrode timing controller 250. After receiving the address signal related to the output image data and outputting a write pulse for simultaneously recording four lines (1 Line to 4 Line), the four lines are simultaneously written, followed by a predetermined scan and sustain period. The Y-side scan driver 270 does not erase the recorded lines at the same position at the same time for each line block, but through the bit-by-bit erasure positioning unit 210, the erasing position generating unit 230, and the electrode timing controller 250. An erase pulse is output to erase at a different position for each bit line in accordance with the output erase position data.

However, as shown in FIG. 6, by adjusting the erase position for each line of each bit, fine adjustment is required and a somewhat rough image may be obtained with respect to the original image.

FIG. 7 is another embodiment to remedy this vulnerable portion of FIG. 6, which writes, scans by four lines, and erases at different positions by bits, as in the embodiment. The erase positions are determined for each line by tying the erase positions by two lines (1 Line-2Line) (3Line-4Line) according to the screen image data.

For example, in the case of recording and scanning by four lines, the bit-by-bit erasure positioning unit 210 sets the bit-by-bit erasure position in units of two lines according to the image data output from the bit separation unit 130. The Y-side scan driver 270 determines two lines (1Line-2Line) and 3Line-4Line according to the erase position data output through the erase position generator 230 and the electrode timing controller 250. The erase position is varied for each line.

Therefore, by eliminating and deleting a plurality of lines at the same fixed position for each bit, the erase position is determined and adjusted for each line of each bit in units of two lines according to the displayed image data, thereby generating each line. By reducing the difference in luminance, the luminance of each line can be adjusted to the optimal state.

When the erase position is adjusted based on two lines, the difference in luminance is not only reduced by line but also a smoother and smoother image can be obtained than adjusting the erase position by one line as in the embodiment of FIG. 6. Can be implemented.

Therefore, in the present invention, an average value is calculated for each bit (subfield) according to the input image data, and a line having a heavy load determines a position for eliminating sustain discharge in a direction in which the number of sustains increases, and a line having a low load has a sustain value. By determining the position of erasing the sustain discharge in the direction of decreasing number and changing the erasing position of the cell for each line of each bit, it is possible to lighten or darken a specific part of the screen to overcome the luminance difference for each part of the panel. In addition, there is an effect that can improve the image quality by eliminating the abnormal luminance difference according to the load of the screen.

Claims (7)

A method of displaying an image by applying a write voltage, a scan voltage, a sustain voltage, and a line erase voltage to each electrode of the panel according to the input image data, and perform a write period, an address period, a sustain period, and a line erase period of every subfield. In: Every subfield in the line erasing period, (1) After discharging all the cells by applying a write pulse having a voltage value and a width for discharging all cells between the first electrode and the second electrode, the applied voltage between the first and second electrodes is set to zero. A recording period for accumulating wall charge on the dielectric; (2) an address period after the write discharge to discharge between the first electrode or the second electrode and the third electrode to erase and write wall charges on the dielectric; (3) a sustain period in which sustain discharge is performed by applying an alternating voltage between the first electrode and the second electrode after the addressing and using wall charges accumulated on the dielectric; And (4) After performing the sustain period, the erase position of each line is determined with the average value for each bit according to the input image data, and then the line erasing period is executed while varying the corresponding line for all the cells of the panel. Line erasing method of plasma display panel. The method of claim 1, The line erase position of the line erase period is, And a bit erasing position is determined in a direction in which the number of sustain increases when the average value of each bit is higher than a preset reference value. The method of claim 1, The line erase position of the line erase period is, And a bit erasing position is determined in a direction in which the number of sustain decreases when the average value of each bit is smaller than a preset reference value. A method of displaying an image by applying a write voltage, a scan voltage, a sustain voltage, and a line erase voltage to each electrode of the panel according to the input image data, and perform a write period, an address period, a sustain period, and a line erase period of every subfield. In: (1) After discharging all the cells by applying a write pulse having a voltage value and a width for discharging all cells between the first electrode and the second electrode, the applied voltage between the first and second electrodes is set to zero. A recording period for accumulating wall charge on the dielectric; (2) an address period during which the write period is discharged between the first electrode or the second electrode and the third electrode to erase wall charges on the dielectric after performing the write period; (3) a sustain period of performing sustain discharge using wall charges accumulated on the dielectric by applying an alternating voltage between the first electrode and the second electrode after performing the address period; And (4) After performing the sustain period, the line erase position is determined according to the average value of each bit according to the input image data, and then the erase position is varied by two lines in the unit line block of the panel. And a line erasing period is performed for each subfield. The method of claim 4, wherein The line erase position of the line erase period is, And a bit erasing position is determined in a direction in which the number of sustain increases when the average value of each bit is higher than a preset reference value. The method of claim 4, wherein The line erase position of the line erase period is, And a bit erasing position is determined in a direction in which the number of sustain decreases when the average value of each bit is smaller than a preset reference value. The address, scan, and sustain electrodes are arranged in a row and column matrix, and a panel in which cells are formed at orthogonal portions of the electrodes, a circuit for driving each electrode of the panel, and a write pulse, scan pulse, In a plasma display circuit which generates a sustain pulse and a line erase pulse and applies it to a cell through each electrode of the panel: A panel control unit which separates and loads image data input from the outside for each bit and generates recording, scanning and sustain control signals; A bit-by-bit erasure positioning unit that receives the image data separated by bits from the panel controller and calculates an average value by adding bits to each line, and then determines a position to erase each line of each bit according to the average value of each bit; An erase position generator for generating an erase position variable signal for each bit line in accordance with an erase position signal output from the bit erase position determiner; And After generating the cell write, scan, and sustain discharge timing control signals according to the control signal output from the panel controller, an erase variable signal for each bit corresponding to each line output from the erase position generator is provided at the time of erasing the sustain discharge. And an electrode timing control unit for generating a control signal for erasing the sustain discharge of the cell at different positions for each line.