KR100296962B1 - Chip size package manufacturing method - Google Patents

Abstract

The present invention discloses a method for manufacturing a chip size package. In the disclosed invention, the support plates 20 made of metal are disposed on both left and right sides of the pad 31 disposed at the center of the semiconductor chip 30, and are disposed at predetermined intervals from the semiconductor chip 30. The part of encapsulant 40 is etched so that the whole is molded with encapsulant 40 and the pad 31 is exposed. Metal lines 50 electrically connected to the pads 31 are deposited on the surface of the encapsulant 40 on each support plate 20. The upper portion of the entire structure is molded with the encapsulant 40 again, and the encapsulant 40 portion of the upper portion of the metal line 50 is etched to form a ball land. The diffusion barrier layer 60 is deposited on the ball lands, and the solder balls 70 are mounted on the diffusion barrier layer 60.

Description

Chip size package manufacturing method

The present invention relates to a method for manufacturing a chip size package.

Chip size packages have the advantage that the size of the package can be set to the size of the chip, research is being continued in accordance with the trend of light and short package. Such a chip size package uses a rigid substrate, or a pattern tape.

Among the above methods, a method using a tab tape is mainly proposed recently because a method using a substrate is very difficult to manufacture. A structure of a conventional chip size package using a tab tape will be described below with reference to FIG. 1.

As shown in the drawing, the tab tape 1 has a structure in which a solder resist 1a, a metal wiring 1b, an adhesive 1c, and an elastomer 1d: elastomer are sequentially stacked from the bottom. The semiconductor chip 2 is attached on the elastomer 1d. The pad 2a of the semiconductor chip 2 is electrically connected to the metal wiring 1b of the tab tape 1 with a copper ribbon 3: Cu ribbon. On the other hand, a ball land is formed in the soldering resist 1a, and the whole is molded with the sealing agent 4 so that this ball land may be exposed and the surface of the semiconductor chip 2 may be exposed. Solder balls 5 mounted on the substrate are attached to the exposed ball lands.

However, the chip size package using the tab tape as described above has a complicated structure of the tab tape, and thus, the package shown in FIG.

As illustrated, the intermediate layer 11 is attached to the bottom surface of the semiconductor chip 10, and the solder ball 12 is directly attached to the bottom surface of the intermediate layer 11.

However, the chip size package shown in FIG. 1 has the following disadvantages.

First, as described above, since the structure of the tab tape consists of four layers, the structure is complicated and the manufacturing process is complicated. In particular, the price of the tab tape is expensive, and also has the disadvantage that the strength is weak due to the material properties.

In addition, although the pads of the pattern tape and the semiconductor chip are bonded with a copper ribbon, the copper ribbon is often broken under high temperature processes. In addition, when epoxy series is used as an encapsulant to secure water resistance, a disconnection accident of the copper ribbon becomes a more serious problem.

On the other hand, since the package shown in Figure 2 does not use a tab tape has the advantage of a simple structure and short electrical connection, but also has the following disadvantages.

First, since both sides of the semiconductor chip are exposed, they are very vulnerable to infiltration of foreign matters or mechanical external shocks.

In addition, since the solder bonding force depends solely on the solder ball since the solder ball is directly attached to the intermediate layer, there is a disadvantage in that the size of the solder ball is increased to increase the bonding force, that is, the thickness of the package is increased. In addition, there is a high possibility that the solder ball supported by the jig in the package electrical test may be damaged, and in order to prevent the solder ball, the material of the solder ball must be expensive copper.

In particular, since the grounding function is not provided, the electrical characteristics may be deteriorated.

Accordingly, the present invention has been made to solve all the disadvantages of the conventional chip size packages, and provides a method of manufacturing a chip sage package that is not complicated in structure and can enhance foreign matter penetration or mechanical strength. The purpose is to.

Another object is to improve the electrical characteristics by making the electrical signal transmission path very short and providing a grounding function.

1 and 2 are cross-sectional views showing a conventional chip size package.

3 illustrates a chip size package according to the present invention.

4 to 19 are diagrams sequentially illustrating a chip size package manufacturing process according to Embodiment 1 of the present invention.

20 is a view showing a package finally completed according to the second embodiment of the present invention

21 is a view showing a package finally completed according to the third embodiment of the present invention

FIG. 22 is a diagram showing the configuration of a multi-chip package using the package presented in the present invention according to Example 4. FIG.

-Explanation of symbols for the main parts of the drawing-

20; Support plate 21; Opening

30; Semiconductor chip 31; pad

40; Sealing agent 50; Metal lines

60; Diffusion barrier layer 70; Solder ball

In order to achieve the above object, a method for manufacturing a chip size package according to the present invention consists of the following steps.

Several openings are formed in the support plate at equal intervals. The support plate is molded with an encapsulant, and several semiconductor chips with a pad disposed in the center are attached to the encapsulant surface so as to be located between each opening, and then the upper part of the entire structure is molded with the encapsulant. The whole is inverted and the encapsulant and the support plate are etched using the photoresist patterned on the surface to expose the pad of the semiconductor chip.

Metal is deposited on top of the entire structure, before which a via hole is formed between the metal and the support plate, so that the metal is embedded in the via hole, so that the metal and the support plate are electrically connected so that the support plate functions as a ground plane. The metal is etched in a predetermined pattern so that only a portion of the surface of the encapsulant remains from one pad to form a metal line. The upper part of the entire structure is again molded with an encapsulant, and then etched using a photo mask to form a ball land so that the metal line on the support plate is exposed. The diffusion barrier layer is deposited on the ball lands, and the solder balls are mounted on the diffusion barrier layer. Finally, it cuts along the opening part of a support plate, and isolate | separates into individual semiconductor chips.

According to the above-described configuration of the present invention, since the pad of the semiconductor chip is connected to the solder balls through a metal line which can be formed into a very short length, the electric signal transmission path is very short, and thus the structure of the package is very simple. do. By supporting the grounding plate, the electrical characteristics of the package are improved.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

Example 1

3 is a view showing a chip size package according to the first embodiment of the present invention, Figures 4 to 19 is a view showing a package according to the first embodiment in the order of manufacturing process.

First, as shown in FIG. 3, the semiconductor chip 30 is disposed so that the pad 31 disposed at the center thereof faces upward. A pair of support plates 20 are disposed on both sides of each pad 31, and the support plates 20 are conductors through which electricity can flow, that is, a kind of metal plate, with a predetermined distance from the surface of the semiconductor chip 30. Is placed. One end of the metal line 50 is bonded to the pad 31, and the other end extends to the upper portion of each support plate 30 to be disposed at a predetermined distance from the surface of the support plate 30.

The whole is molded with encapsulant 40 and the corresponding portion of encapsulant 40 is etched to form a ball land so that the metal lines 50 on each support plate 20 are exposed. The solder balls 70 mounted on the substrate are mounted on the ball lands.

On the other hand, the metal line 50 is a single layer structure of any one of aluminum, copper, nickel, chromium, titanium, gold, platinum, palladium, lead, or tin, or a multilayer structure in which several pieces are stacked.

However, when the metal line 50 and the solder ball 70 are bonded to each other, the metal atoms of the metal line 50 diffuse into the lead-tin-based solder ball 70, whereby an intermetallic compound may be formed at the interface. have. Since this intermetallic compound weakens the adhesive force between the metal line 50 and the solder ball 70, it is preferable that the diffusion prevention layer 60 is formed in a ball land.

The diffusion barrier layer 60 is a single layer structure such as the material of the metal line 50, or copper and nickel and gold, copper and nickel and gold and chromium, copper and nickel and gold and cobalt, copper and nickel and gold and tin, It is a multilayered structure consisting of copper, nickel, gold, chromium, tin, copper, nickel, gold, cobalt, tin, or copper, nickel, and lead. On the other hand, if the metal line 50 is a multilayer structure selected from those mentioned as materials, such as the diffusion barrier layer 60, since the metal line 50 itself exhibits a diffusion barrier function, it is necessary to form a diffusion barrier layer 60 separately There is no.

Hereinafter, a method of manufacturing a chip size package having the above structure will be described in detail with reference to the accompanying drawings.

First, the support plate 20 shown in FIG. 4 is prepared. In the support plate 20, several openings 4 are formed long at equal intervals in this embodiment. Each of the openings 21 is a central portion of the semiconductor chips, that is, a region in which pads are disposed in a subsequent process, and a portion between the openings 21 serves as a reference line of the cutting process of separating the individual chips into semiconductor chips when the package is finally completed. .

Subsequently, the encapsulant 40 is applied onto the rotating flat plate 80 as illustrated in FIG. 5A, and the supporting plate 20 is adhered to the encapsulant 40 surface as illustrated in FIG. 5B. Again, the encapsulant 40 is spin-coated on the entire structure as shown in FIG. 5C, and the entire supporting plate 20 is molded with the encapsulant 40 as shown in FIG. 5D.

Then, the semiconductor chips 30 are attached to the surface of the encapsulant 40 as shown in FIG. 6A so that the pad is located at the center of each opening 21. Fig. 6B shows this structure in side cross-section.

Subsequently, as shown in FIG. 7, the encapsulant 40 is spin-coated again on the entire structure, and as shown in FIG. 8, each semiconductor chip 30 and the support plate 20 are molded into one encapsulant 40. Then, the encapsulant 40 is cured. Subsequently, when the rotating plate 80 is removed, it becomes as shown in FIG. 9.

Then, as shown in FIG. 10A, after inverting the entirety, the photoresist 90 is applied and patterned on the surface of the encapsulant 40, and then the etching region of the encapsulant 40 is exposed to expose the pad of the semiconductor chip 30. Etch (91). FIG. 10B shows this in plan view.

More specifically, as shown in FIG. 11A, which is a detailed view of the XI portion of FIG. 10B, showing only one semiconductor chip 30, and FIG. 11B, which is a side cross-sectional view of FIG. 11A, the pad 31 of the semiconductor chip 30 is shown. ) Is exposed in the encapsulant 40.

Subsequently, a metal film is deposited on the entire structure, and the metal film is etched using a photo mask pattern so that a portion between each opening 21 and a portion between the pads 21 is etched, thereby etching the metal line 50 shown in FIG. 12A. ). That is, one end of the metal line 50 is connected to the pad 31, and the other end thereof is disposed at a predetermined interval on the support plate 20. 12B is a plan view showing such a structure, and as shown, metal lines 50 having one end connected to the pad are formed on the encapsulant 40. On the other hand, via holes 51 (see FIG. 13 which is an enlarged view of the XIII portion of FIG. 12B) are formed at the other end position of the metal line 50 so that the support plate 20 serves as a grounding function, and the via holes 51 also have metal lines. As the 50 is embedded, the metal line 50 and the support plate 20 are electrically connected.

The subsequent process is almost the same as a general packaging process. That is, as shown in FIG. 14, the upper portion of the entire structure is molded with the encapsulant 40, and the surface of the encapsulant 40 is etched using the patterned photoresist 91 as shown in FIG. 15. Then, as shown in FIG. 16, the ball land 71 is formed by exposing the metal line 50. Next, as illustrated in FIG. 17, the diffusion barrier layer 60 is deposited on the ball land 71 and the solder balls 70 are mounted on the diffusion barrier layer 60, as shown in FIG. 18.

Finally, cutting along the cut line shown in dashed line in FIG. 19A, that is, along the portion between each opening 21, as shown in FIG. 19B, completes the chip size package according to the first embodiment shown in FIG.

Example 2

20 is a view showing a package finally completed according to a second embodiment of the present invention.

As shown, instead of the metal lines used in Example 1, a pattern film 100 is used in this Example 2. That is, a pattern film 100 having a ball land already formed is attached to the support plate 20, and the conductor 101 extending from the pattern film 100 is punched to the pad 31 of the semiconductor chip 30. Bonded by. The bonding region is again molded into the encapsulant 110 and the solder balls 70 are mounted on the exposed ball lands.

The method of manufacturing a package having such a structure is the same until the step of FIG. 11B, that is, exposing the pad 31 of Example 1, and then placing the pattern film 100 on the support plate 20, A conductor 101 extending inwardly is punched out to electrically connect the pads 31 to each pad 31. Subsequently, after bonding the bonding region with the encapsulant 110, the solder balls 70 are mounted on the ball lands formed on the pattern film 100.

Example 3

21 is a view showing a package finally completed according to Embodiment 3 of the present invention. As shown in FIG. 21, the package structure is substantially the same as the package structure according to Embodiment 1, except that the bottom surface of the semiconductor chip 30 is exposed. It is a shape which grind | polished and removed the sealing material 40 of the site | part. The bottom surface of the exposed semiconductor chip 30 has a heat dissipation effect.

Example 4

FIG. 22 is a diagram illustrating a multi-chip package using the package presented in the present invention according to the fourth embodiment. As shown, several unmolded packages are disposed in the ceramic capsule 120, and a solder ball 130 is mounted on the bottom surface of the ceramic capsule 120.

As described above, according to the present invention, since the electric signal transmission path from the pad to the solder ball is made by a metal line which can be formed in a very short length without using the metal wire, it is very important to construct the electric signal transmission path very short. By doing so, the electrical characteristics are improved.

The support plate is provided inside the package, greatly strengthening the package strength, and in particular, the support plate is electrically connected through the metal line and the via hole, thereby providing a grounding function.

In the above, a preferred embodiment for carrying out the method for manufacturing a chip size package according to the present invention has been illustrated and described, but the present invention is not limited to the above-described embodiment, but deviates from the gist of the present invention claimed in the following claims. Without this, any person skilled in the art to which the present invention pertains may make various changes.

Claims (3)

Molding the entire supporting plate of the conductor having a plurality of openings formed at equal intervals with an encapsulant; Attaching several semiconductor chips to a surface of the encapsulant such that a pad disposed at the center thereof is positioned at the center of each opening, and molding the entire upper part of the structure back into the encapsulant; Etching the corresponding area of the encapsulant such that the entire surface of the encapsulant is exposed by flipping over the entire surface of the semiconductor chip; Depositing a metal film on the entire structure, and etching the metal film so that the metal film remains only on the pad and the support plate to form a metal line; Molding the entire top of the structure with an encapsulant, and then etching the encapsulant portion above the metal line to form a ball land; Mounting a solder ball on the ball land; And And cutting the portions between the openings and separating the portions into individual semiconductor chips. The method of claim 1, further comprising forming a via hole in an encapsulant portion on the upper portion of the support plate, and filling the via hole with the metal film to electrically connect the support plate to the metal film before the metal film is deposited. Chip size package manufacturing method to use. The method of claim 1, wherein before the solder ball mounting, a diffusion barrier layer is deposited on the ball lands, and a solder ball is mounted on the diffusion barrier layer.