KR100292690B1 - Active Area Separation Method for Semiconductor Devices - Google Patents
Active Area Separation Method for Semiconductor Devices Download PDFInfo
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- KR100292690B1 KR100292690B1 KR1019980020778A KR19980020778A KR100292690B1 KR 100292690 B1 KR100292690 B1 KR 100292690B1 KR 1019980020778 A KR1019980020778 A KR 1019980020778A KR 19980020778 A KR19980020778 A KR 19980020778A KR 100292690 B1 KR100292690 B1 KR 100292690B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000926 separation method Methods 0.000 title abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000011810 insulating material Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
Abstract
본 발명은 반도체장치의 활성영역 분리방법에 관한 것으로서, 특히, 표준매몰형 콜렉터(standard buried collector)를 갖는 바이폴라트랜지스터 등을 형성하기 위하여 에피층을 형성한 다음 분리영역이 형성될 부위의 에피층을 제거하여 트렌치를 형성한 다음 여기에 절연물질을 매립하여 분리영역을 형성하므로서 공정을 단순화하고 또한 서브-마이크론 단위의 소자를 구현할 수 있도록한 반도체장치의 분리영역 형성방법에 관한 것이다. 이를 위하여 본 발명의 반도체장치의 활성영역 분리방법은 제 2 도전형 불순물로 고농도로 도핑된 매몰층이 표면의 소정부위에 형성된 제 1 도전형 반도체기판 위에 에피층을 형성하는 단계와, 에피층의 소정 부위를 제거하여 분리영역을 정의하는 트렌치를 형성하는 단계와, 트렌치를 절연물질로 매립하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for separating active regions of a semiconductor device, and in particular, to form a bipolar transistor having a standard buried collector and the like, and then forming an epi layer at a portion where a separation region is to be formed. The present invention relates to a method for forming a separation region of a semiconductor device, which can simplify the process and implement a sub-micron device by forming a separation region by removing trenches and then filling an insulating material therein. To this end, the method for separating an active region of a semiconductor device of the present invention comprises forming an epitaxial layer on a first conductive semiconductor substrate having a buried layer heavily doped with a second conductivity type impurity formed on a predetermined portion of the surface, Removing a predetermined portion to form a trench defining an isolation region; and filling the trench with an insulating material.
Description
본 발명은 반도체장치의 활성영역 분리방법에 관한 것으로서, 특히, 표준매몰형 콜렉터(standard buried collector)를 갖는 바이폴라트랜지스터 등을 형성하기 위하여 에피층을 형성한 다음 분리영역이 형성될 부위의 에피층을 제거하여 트렌치를 형성한 다음 여기에 절연물질을 매립하여 분리영역을 형성하므로서 공정을 단순화하고 또한 서브-마이크론 단위의 소자를 구현할 수 있도록한 반도체장치의 분리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for separating active regions of a semiconductor device, and in particular, to form a bipolar transistor having a standard buried collector and the like, and then forming an epi layer at a portion where a separation region is to be formed. The present invention relates to a method for forming a separation region of a semiconductor device, which can simplify the process and implement a sub-micron device by forming a separation region by removing trenches and then filling an insulating material therein.
바이폴라 트랜지스터 제조공정중 소자의 활성영역을 위한 제 1 도전형 에피층의 성장이 끝나면 그 위에 얇은 두께의 산화막을 키운 다음 분리영역이 형성될 부위에 제 2 도전형 불순물 이온의 확산을 선확산 및 후확산의 과정으로 수행한다.물론 이러한 분리 영역이 트랜지스터의 동작에 능동적으로 참가하지는 않는다.After the growth of the first conductive epitaxial layer for the active region of the device during the bipolar transistor manufacturing process, a thin oxide film is grown thereon, followed by prediffusion and diffusion of the second conductive impurity ion in the region where the isolation region is to be formed. In the course of diffusion, these isolation regions do not actively participate in the operation of the transistor.
이러한 접합분리(junction isolation)기술에서는, 트랜지스터에 있어서 내부 트랜지스터(intrinsic transistor)가 차지하는 면적이 전체트랜지스터에 소요되는 면적의 극히 일부만을 이루게 된다. 즉 분리확산은 접합의 깊이가 가장 깊고 따라서 옆으로 퍼지는 면적 또한 클 뿐만 아니라, 이 분리영역을 트랜지스터의 베이스 영역으로 부터 분리시키기 위하여 다시 n영역을 필요로 한다. 내부트랜지스터는 작은 면적만을 차지할 지라도 트랜지스터를 둘러싼 이와 같은 소모성의 주위면적은 매우 커진다.In such a junction isolation technique, the area occupied by an intrinsic transistor in a transistor constitutes only a part of the area of the entire transistor. In other words, the isolation diffusion not only has the deepest junction and therefore has a large area spreading laterally, but also needs n regions to separate the isolation region from the base region of the transistor. Although internal transistors occupy only a small area, this consumable peripheral area around the transistors becomes very large.
물론 분리영역의 접합 깊이를 낮추어서 옆으로 퍼지는 면적을 줄이는 방법도 있으나 이는 매몰층이 베이스 영역에 밀착하게 되어 항복전압이 낮아지게 되므로 이와 같은 방법은 한계에 부닥치게 된다.Of course, there is also a method of reducing the area spreading laterally by lowering the junction depth of the separation region, but this method is limited because the buried layer is in close contact with the base region and the breakdown voltage is lowered.
따라서 후확산 공정을 사용하지 아니하고 분리영역을 형성할 수 있는 트렌치를 형성한 다음 여기에 절연물질을 매립하여 분리영역을 형성하는 방법이 더욱 효과적이다.Therefore, a method of forming a separation region by forming a trench for forming an isolation region without using a post diffusion process and then filling an insulating material therein is more effective.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 활성영역 분리방법을 도시하는 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of separating active regions of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판인 p형 실리콘기판(1)의 소정 부위에 n형으로 고농도 도핑된 매몰층(2)을 마스크공정과 이온주입 또는 스핀-온 방법 그리고 선확산 및 후확산(drive-in)을 실시하여 형성한다.Referring to FIG. 1A, a buried layer 2 heavily doped n-type in a predetermined portion of a p-type silicon substrate 1, which is a semiconductor substrate, is subjected to a mask process, an ion implantation or spin-on method, and a pre-diffusion and post-diffusion (drive) method. formed by -in).
그리고 매몰층(2) 표면을 포함하는 기판(1)의 전면에 제 1 산화막(3)을 약 7000Å 두께로 형성한 다음 제 1 포토레지스트패턴을 형성하는 사진식각공정으로 제 1 산화막의 소정부위를 제거하여 분리영역이 형성될 부위의 기판(1) 표면을 개방시킨다. 그리고 제 1 포토레지스트패턴을 제거한다.Then, a predetermined portion of the first oxide film is formed by a photolithography process in which the first oxide film 3 is formed to a thickness of about 7000 포함 on the entire surface of the substrate 1 including the buried layer 2 and then the first photoresist pattern is formed. It removes and opens the surface of the board | substrate 1 of the site | part to form a separation area. Then, the first photoresist pattern is removed.
그다음 기판(1)의 전면에 p 형 불순물 이온주입을 고농도로 실시하여 p 형 불순물 매몰층(4)을 형성한다. 이때 주입되는 불순물이온은 이후 형성되는 에피층의 하부로 확산되어 하부분리영역(5)을 형성하는데 이용된다.Then, the p-type impurity implantation layer 4 is formed on the entire surface of the substrate 1 at a high concentration. At this time, the impurity ions to be implanted are diffused to the lower part of the epi layer to be formed and used to form the lower separation region 5.
도 1b를 참조하면, 잔류한 제 1 산화막을 제거한 다음 기판의 전 표면에 에피층(6)을 성장시켜 형성한다.Referring to FIG. 1B, the remaining first oxide film is removed and then formed by growing the epi layer 6 on the entire surface of the substrate.
한편, p 형 불순물 매몰층(4)의 불순물 이온들이 에피층(6)의 하부로 확산되어 하부분리영역(5)을 형성한다.On the other hand, impurity ions of the p-type impurity buried layer 4 diffuse into the lower portion of the epi layer 6 to form the lower isolation region 5.
도 1c를 참조하면, 다시 에피층(6)의 전면에 제 2 산화막(7)을 약 7000Å 두께로 성장시켜 형성한 다음 그 위에 포토레지스트를 도포한 후 노광 및 현상하여 제 1 포토레지스트패턴과 동일한 위치에 제 2 포토레지스트패턴을 형성한 후 이로 부터 보호되지 아니하는 부위의 제 2 산화막(7)을 제거하여 에피층(6)의 상부표면을 노출시킨다.Referring to FIG. 1C, a second oxide film 7 is formed on the entire surface of the epitaxial layer 6 to a thickness of about 7000 Å, and then a photoresist is applied thereon, followed by exposure and development to produce the same photoresist pattern as the first photoresist pattern. After forming the second photoresist pattern at the position, the second oxide film 7 at the portion not protected from it is removed to expose the upper surface of the epi layer 6.
노출된 에피층(6)의 표면을 포함하는 잔류한 제 2 산화막(7)의 전면에 BSG(Boron Silicate Glass)층(8)를 증착하여 형성한 다음 여기서 붕소이온이 노출된 에피층(6) 표면을 고농도로 도핑되게 한다.A BSG (Boron Silicate Glass) layer 8 is formed on the entire surface of the remaining second oxide film 7 including the surface of the exposed epi layer 6, and then the boron ion-exposed epi layer 6 is formed. Causes the surface to be heavily doped.
도 1d를 참조하면, BSG층(8)을 제거한 다음 후확산공정을 실시하여 상부분리영역(9)을 형성한다. 이때 상부분리영역(9)은 하부분리영역(5)과 만나게 되어 하나의 분리영역을 형성하게 된다.Referring to FIG. 1D, the BSG layer 8 is removed and then a post diffusion process is performed to form the upper separation region 9. At this time, the upper separation region 9 meets the lower separation region 5 to form one separation region.
이후 도시되지는 않았으나, 분리영역사이에 형성된 활성영역에 베이스, 이미터, 콜렉터 등을 형성하여 바이폴라트랜지스터 등을 형성한다.Subsequently, although not shown, a bipolar transistor or the like is formed by forming a base, an emitter, a collector, and the like in an active region formed between the isolation regions.
그러나, 상술한 종래의 반도체장치의 활성영역 분리방법은 소자의 분리영역을 형성하기 위하여 두개의 산화막 형성공정, 한개의 이온주입공정, 두개의 사진식각공정 및 한개의 유리(glass)제거공정을 필요로 하므로 공정이 복잡하고 공정시간이 매우 길어지게 되고, 복잡한 공정에서 초래되는 웨이퍼 오염등이 발생하며, 또한 확산현상을 이용한 후확산공정을 사용하므로 분리영역의 크리티칼 디멘션(critical dimension)이 커지게 되어 소자의 체적 역시 커지게 되어 서브-마이크론 단위의 소자를 제조하는데 곤란한 문제점이 있다.However, the active region separation method of the conventional semiconductor device described above requires two oxide film formation processes, one ion implantation process, two photolithography processes, and one glass removal process to form the isolation region of the device. As a result, the process is complicated and the processing time becomes very long, wafer contamination caused by the complicated process occurs, and the post-diffusion process using diffusion phenomenon is used to increase the critical dimension of the separation region. As a result, the volume of the device is also increased, which makes it difficult to manufacture a device having a sub-micron unit.
따라서, 본 발명의 목적은 소자의 활성영역이 형성될 에피층을 형성한 다음 분리영역이 형서될 부위의 에피층을 제거하여 트렌치를 형성한 후 여기에 절연물질을 매립하므로서 분리영역을 형성하는 방법을 제공하는데 있다.Accordingly, an object of the present invention is to form an isolation region by forming an epi layer on which an active region of the device is to be formed, and then removing the epi layer of the region where the isolation region is to be formed to form a trench, and then filling an insulating material therein. To provide.
상기 목적을 달성하기 위해 본 발명의 반도체장치의 활성영역 분리방법은 제 2 도전형 불순물로 고농도로 도핑된 매몰층이 표면의 소정부위에 형성된 제 1 도전형 반도체기판 위에 에피층을 형성하는 단계와, 에피층의 소정 부위를 제거하여 분리영역을 정의하는 트렌치를 형성하는 단계와, 트렌치를 절연물질로 매립하는 단계를 포함하여 이루어진다.In order to achieve the above object, an active region separation method of a semiconductor device of the present invention includes forming an epitaxial layer on a first conductive semiconductor substrate having a buried layer heavily doped with a second conductive impurity formed on a predetermined portion of the surface; And removing a predetermined portion of the epi layer to form a trench defining an isolation region, and filling the trench with an insulating material.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 활성영역 분리방법을 도시하는 공정단면도1A to 1D are cross-sectional views illustrating a method of separating active regions of a semiconductor device according to the related art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 활성영역 분리방법을 도시하는 공정단면도2A through 2D are cross-sectional views illustrating a method of separating active regions of a semiconductor device according to the present invention.
본 발명은 소자 활성영역의 하부에 위치하는 매몰층을 종래기술로 형성한 다음 에피층을 형성한 후 에피층의 분리영역이 형성될 부위를 사진식각공정으로 제거한 다음 여기에 질화막을 매립하므로서 후확산공정 없이 분리영역을 형성한다.The present invention forms a buried layer located below the active region of the device according to the prior art, and then forms an epi layer, and then removes a portion where the separated region of the epi layer is to be formed by a photolithography process and then diffuses it by embedding a nitride film therein. A separation zone is formed without a process.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 활성영역 분리방법을 도시하는 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of separating active regions of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판인 제 1 도전형 실리콘기판(21)의 소정 부위에 제 2 도전형으로 고농도 도핑된 매몰층(22)을 마스크공정과 이온주입 또는 스핀-온 방법 그리고 선확산 및 후확산(drive-in)을 실시하여 형성한다. 이때 제 1 도전형은 p 형으로 한다.Referring to FIG. 2A, a buried layer 22 heavily doped with a second conductivity type in a predetermined portion of the first conductivity type silicon substrate 21, which is a semiconductor substrate, is subjected to a mask process, an ion implantation or spin-on method, and a line diffusion method. It is formed by drive-in. At this time, the first conductivity type is p-type.
그리고 매몰층(2) 표면을 포함하는 기판(1)의 전면에 실리콘으로 에피층(23)을 요구되는 두께로 성장시켜 형성한다. 이러한 에피층(23)의 완숙도가 트랜지스터의 수율에 매우 큰 영향을 미치므로 경우에 따라서는 에피층 표면의 식각이 요구되기도 한다. 보통의 경우 SiCl4를 써서 수소를 운반기체로 하여 1120℃ 이상의 온도에서 형성시키거나 SiH4를 사용하여 1080℃ 정도에서 형성된다.The epitaxial layer 23 is formed on the entire surface of the substrate 1 including the buried layer 2 by growing the epitaxial layer 23 to the required thickness. Since the maturity of the epi layer 23 greatly affects the yield of the transistor, etching of the surface of the epi layer may be required in some cases. Usually, hydrogen is used as a carrier gas using SiCl 4 to form at a temperature of 1120 ° C. or higher, or at about 1080 ° C. using SiH 4 .
도 2b를 참조하면, 에피층(23)의 표면에 포토레지스트를 도포한 다음 분리영역을 정의하는 마스크로 포토레지스트패턴(24)을 에피층(23) 위에 형성한다. 포토레지스트패턴(24)으로 보호되지 아니하는 부위의 에피층(23)을 제거하여 기판(21)의 표면을 노출시키는 트렌치를 형성한다.Referring to FIG. 2B, a photoresist is applied to the surface of the epitaxial layer 23, and then a photoresist pattern 24 is formed on the epitaxial layer 23 using a mask defining a separation region. The epitaxial layer 23 of the portion not protected by the photoresist pattern 24 is removed to form a trench that exposes the surface of the substrate 21.
도 2c를 참조하면, 포토레지스트패턴을 제거한 다음, 트렌치를 충분히 매립하는 질화막(25)을 트렌치 내부 및 잔류한 에피층(23)의 표면에 증착하여 형성한다.Referring to FIG. 2C, after the photoresist pattern is removed, a nitride film 25 sufficiently filling the trench is formed by depositing the inside of the trench and the surface of the remaining epitaxial layer 23.
도 2d를 참조하면, 이후 에피층(23)의 표면이 노출될 때까지 씨엠피 또는 에치백 공정을 질화막(25)의 표면에 실시하여 평탄화시킨다. 이때 트렌치에 잔류한 질화막(23)과 매몰층(22)으로 둘러싸인 활성영역이 정의 된다.Referring to FIG. 2D, the CMP or etch back process is performed on the surface of the nitride film 25 until the surface of the epitaxial layer 23 is exposed to planarize. In this case, an active region surrounded by the nitride film 23 and the buried layer 22 remaining in the trench is defined.
이후 도시되지는 않았으나, 분리영역사이(25)에 형성된 활성영역(23)에 베이스, 이미터, 콜렉터 등을 형성하여 바이폴라트랜지스터 등을 형성한다.Although not shown in the drawings, a base, an emitter, a collector, and the like are formed in the active region 23 formed between the separation regions 25 to form a bipolar transistor.
따라서, 본 발명은 소자의 활성영역이 형성될 에피층에 트렌치를 형성하여 여기에 절연물질을 매립하므로서 분리영역을 형성하여 다수의 공정을 생략하게 하여 공정의 단순화를 이룩하였으며, 또한 후확산공정이 필요하지 아니하므로 공정시간을 크게 단축시킴과 동시에 확산공정에서 요구되는 넓은 디자인 룰을 개선하여 소자의 크기를 감소시키는 장점이 있다.Therefore, in the present invention, a trench is formed in the epi layer in which the active region of the device is to be formed, and an isolation material is buried therein to form a separation region, thereby eliminating a plurality of processes, thereby simplifying the process. Since it is not necessary, the process time is greatly reduced, and the size of the device is reduced by improving the wide design rule required in the diffusion process.
Claims (5)
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| KR1019980020778A KR100292690B1 (en) | 1998-06-05 | 1998-06-05 | Active Area Separation Method for Semiconductor Devices |
| US09/840,515 US7178160B2 (en) | 1998-06-05 | 2001-04-23 | Device for receiving satellite broadcast and a receiving method therefor |
| US10/007,743 US20020083457A1 (en) | 1998-06-05 | 2001-11-08 | Device for receiving satellite broadcast and a receiving method therefor |
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