KR100290866B1 - Arithmetic device capable of speed detection - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides an arithmetic operation apparatus capable of detecting a speed suitable for a system having a relatively low margin due to a process change. The present invention provides an arithmetic operation apparatus having an arithmetic operation unit for calculating two data of n bits. The first and second registers for storing the data input through the bus and then outputting the first and second registers and the n-bit first, second and third multiplexers for selecting the input of the operation unit are output from the first and second multiplexers. An operation unit that receives data and performs an actual operation, a third register that stores the calculated result, a timing generator that supplies timing signals to the first, second, third multiplexers, and third registers, the timing generator, and the first generator And a logic gate formed between the three registers and outputting a load signal to the third register. All.

Description

Arithmetic device capable of speed detection

The present invention relates to an arithmetic operation apparatus, and more particularly, to an arithmetic operation apparatus capable of detecting a speed by adding a logic to an arithmetic logic unit (ALU) to verify a change in speed according to a change in a process. It is about.

Hereinafter, the arithmetic operation apparatus according to the prior art will be described with reference to the accompanying drawings.

1 is a block diagram of a conventional arithmetic operation device.

As shown in Fig. 1, a data bus 11 for supplying data necessary for calculation, a first register 12 and a second register 13 for storing data input via the data bus 11, An arithmetic unit 14 for performing actual operations with data output from the first and second registers 12 and 13, a third register 15 for storing the calculated results, and an output from the third register 15 It consists of a Result Bus 16 for transferring the data to another block.

The first and second registers 12 and 13 receive data through the data bus 11 and receive reset and load signals as inputs, respectively, and each output is connected to two inputs of the calculation unit 14.

The operation unit 14 receives data output from the first and second registers 12 and 13, and other inputs include carry-in, and the calculation results thereof are SUM and carry. Output as Carry-out.

The operation of the conventional arithmetic operation device is as follows.

When the data of the data bus 11 is stored in the first and second registers 12 and 13 by a load signal applied from the outside, the operation unit 14 performs the first and second registers 12 and 13. Start the operation with the data output from.

At this time, the carry-in, which is another input applied, is also supplied from the outside.

Then, the calculated result value is stored in the third register 15. In this case, the speed test adjusts the time of the load signals to check how much the operation unit 14 operates.

However, the conventional arithmetic operation apparatus as described above has the following problems.

For most high-speed, high-density circuits, the arithmetic unit operates at the same speed as the system clock, so increasing the system clock to measure the speed of the arithmetic unit will determine which block gives the wrong measurement due to speed issues. I could not.

The present invention has been made to solve the above problems, and an object thereof is to provide an arithmetic operation apparatus capable of speed detection suitable for a system having a relatively small margin due to process change.

1 is a block diagram of an arithmetic operation device according to the prior art

2 is a block diagram of an arithmetic operation apparatus capable of detecting the speed of the present invention

3 is an operation waveform diagram of the arithmetic operation apparatus capable of detecting the speed of the present invention

Explanation of symbols for main parts of the drawings

21: data bus 22,23,28: first and second register

24, 25, 26: first, second, third multiplexer 27: arithmetic unit

29: timing generator 30: rebus bus

31: Logic Gate

In the arithmetic operation apparatus capable of speed detection according to the present invention for achieving the above object, in the arithmetic operation apparatus having an arithmetic operation unit for calculating two data of the input n-bit, after storing the data input through the data bus, An arithmetic unit configured to receive data output from the n-bit first, second and third multiplexers for selecting inputs of the first and second registers and the operation unit to be output, the first and second multiplexers, and to perform an actual operation; A third generator for storing a calculated result, a timing generator for supplying a timing signal to the first, second, third multiplexer and a third register, and formed between the timing generator and the third register to the third register. And a logic gate for outputting a load signal.

First, the present invention has been proposed due to the necessity of checking the speed of a custom block that may occur when manufacturing a system operating at a high speed.

When designing a part that requires a certain performance, such as a high speed arithmetic unit, the design is made in consideration of factors such as process change, but the performance after the actual implementation is changed a lot. As it has a direct impact on performance, the necessity of quantitative speed verification of these blocks was initially used for characterization and later for screening out defective products.

Therefore, it is proposed to add simple logic to the design block of arithmetic operation unit to perform simple and efficient measurement of actual performance and margin of the part affecting the speed of the system.

Hereinafter, an arithmetic operation apparatus capable of speed detection according to the present invention will be described with reference to the accompanying drawings.

In the embodiment of the present invention, the N-bit calculator is described as an example for convenience.

As shown in FIG. 2, the arithmetic operation apparatus capable of speed detection according to the present invention includes a data bus 21 for supplying data, a first register 22 for storing data input through the data bus 21, and Outputs from the second register 23, the N-bit first, second, and third multiplexers 24, 25, and 26 for selecting the input of the calculation unit, and the first and second multiplexers 24, 25. An arithmetic unit 27 for receiving actual data and performing an actual operation, a third register 28 for storing the calculated result, the first, second, third multiplexers 24, 25, 26 and the first And a timing bus 29 for supplying an appropriate timing signal to the third register 28, and a reset bus 30 for receiving the output of the third register 28 and transferring it to another block.

Here, a logic gate 31 is further configured between the timing generator 29 and the third register 28.

The input data of the first and second registers 22 and 23 is applied from the data bus 21 and has a reset signal and a load signal as inputs, respectively, and the outputs of the first and second registers 22 and 23 are first and second outputs. Are connected to inputs of second multiplexers 24 and 25, respectively.

The first multiplexer 24 has one input connected to the output of the first register 22 and another input connected to the output of the calculator 27.

The SELECT signal uses an overrun window signal (ORW) signal output from the timing generator 29.

The second multiplexer 25 has one input connected to the output of the second register 23 and another input receives an already defined INC value.

As the selection signal, an ORW signal output from the timing generator 29 is used.

One input of the third multiplexer 26 is connected to a logic value "0" and the other input is connected to a carry-in. Like the first and second multiplexers 24 and 25, the selection signal uses an ORW signal output from the timing generator 29.

The calculation unit 27 has three inputs and two outputs. That is, the outputs of the first, second, and third multiplexers 24, 25, and 26 are used as inputs, and the two outputs are connected to the inputs of the carry-out and the third register 28.

The third register 28 has a reset signal and a load signal and an output is connected to the result bus 30.

The timing generator 29 has two inputs and two outputs, one of which is connected to a trigger and the other input to a clock.

One output is connected to each of the first, second, and third multiplexers 24, 25, and 26 as an input, and the other output is connected to one input of the logic gate 31.

Referring to Figures 2 to 3 the operation of the arithmetic operation apparatus capable of detecting the speed of the present invention configured as described above is as follows.

3 is an operation waveform diagram of the arithmetic operation apparatus capable of detecting the speed of the present invention.

All registers are initialized by the reset signal (initial value = 0). In addition, the trigger and carry-in also have an initial value (initial value = 0) by the reset signal.

All internal control signals and output values are also initialized (initial value = 0).

In the case of normal operation, the value of the ORW signal output to the timing generator 29 becomes "1", and data transfer from the first and second registers 22 and 23 to the calculation unit 27 is interrupted. Instead, the operation unit ( One input of 27) is applied with its output value and the other with the already defined INC value.

And a "0" is applied to the carry-in input.

In other words, from the moment when the ORW signal output from the timing generator 29 is changed to "1", the calculation unit 27 continues the repetitive calculation periodically by adding the time required for the calculation and the time according to the transmission delay.

At this time, when the timing generator 29 generates a load signal "LOAD" at an appropriate time and makes the ORW signal "0" and outputs it, the result of the repetitive operation so far is stored in the third register 28.

It is possible to predict the repetitive period through the simulation in the design, and based on this, it is possible to determine the specification of the INC value and the timing generator 29 already defined.

The result can be read via the result bus 30 and this value can be used for statistics or to determine good / bad.

As described above, the arithmetic operation apparatus capable of detecting the speed of the present invention has the following effects.

In the case of high-speed, high-density circuits, the speed of the arithmetic unit can be measured without increasing the system clock, so the exact speed can be determined.

Claims (9)

In the arithmetic operation unit having an operation unit for calculating two input data of n bits, First and second registers for storing data input through a data bus and outputting the data by a load signal; N-bit first, second and third multiplexers for selecting the input of the operation unit, An operation unit configured to receive data output from the first and second multiplexers and perform an actual operation; A third register for storing the calculated result, A timing generator configured to supply a timing signal to the first, second, third multiplexer and a third register; And a logic gate formed between the timing generator and the third register to output a load signal to the third register. The first multiplexer of claim 1, wherein the first multiplexer uses an overrun window signal ORW output from the timing generator as a selection signal, one input is connected to an output of the first register, and the other input is an output of the operation unit. An arithmetic operation apparatus capable of speed detection, characterized in that connected to the. The method of claim 1, wherein the second multiplexer uses an overrun window signal output from the timing generator as a selection signal, wherein one input is connected to an output of the second register, and the other input receives an already determined INC value. An arithmetic operation apparatus capable of detecting speed. The speed detection method of claim 1, wherein the third multiplexer uses an overrun window signal output from the timing generator as a selection signal, and one input receives a logic "0" and the other input receives a carry-in. Possible arithmetic operations. The arithmetic operation apparatus of claim 1, wherein the logic gate is an OR gate. The timing generator of claim 1, wherein an output thereof is connected to an input of the first, second, third multiplexer and the logic gate, and one input receives a trigger and the other input receives a clock signal. Arithmetic device capable of speed detection. The arithmetic operation apparatus of claim 1, wherein an output of the third register which stores the operation result is connected to a result bus that transmits the result value to another block. 7. The speed detection method according to claim 6, wherein the signal output to the inputs of the first, second, and third multiplexers is an overrun window signal, and the signal output to the logic gate is a load signal. Arithmetic device. The method according to claim 2 or 3 or 4, And said overrun window signal is reset to " 0 " in normal operation and " 1 " in test mode.