KR100290737B1 - Circuit for operating data mean value - Google Patents

Abstract

PURPOSE: A data mean value operating circuit is provided to obtain a mean value of n data continuously input in time series without using n buffers, thereby simplifying the circuit arrangement for clock synchronization of a digital signal receiver. CONSTITUTION: A data mean value operating circuit includes a first operating element(201) for obtaining a sum of data input continuously in time series and deducting a previous mean value from a previous accumulation value, a second operation element(202) accumulating output values from the first operation element to input to the first operation element, a third operation element(203) for averaging output values of the second operation element, and an output element(204) for storing and outputting the mean values of the third operation element and providing the output to the first operation element as a data to be deducted from the previous accumulation value of the first operation element when a next data is input.

Description

Data Average Value Computation Circuit

According to the present invention, a data average value is obtained by continuously sequentially inputting n pieces of data for a predetermined time interval (Tref) and dividing by 1 / n to continuously calculate the average value of the data for a predetermined time interval (Tref) with respect to time progression. In particular, the present invention relates to a circuit for synchronizing clocks of a digital signal receiver, for example, a clock synchronizing circuit for synchronizing a clock on the image decoder side with a clock used in an image compression encoder using a system clock. It relates to the clock frequency averaging circuit of.

In the digital signal transmission system, the matching of the operating clock frequencies of the transmitting side and the receiving side is a very important problem.

For example, in the case of a digital TV system using MPEG video compression transmission technology, if the clock frequency for encoding a digital video signal on the transmitting side and the clock frequency for decoding the same on the receiving side do not match, an error occurs in the image reproduction. This, in turn, leads to deterioration in performance and reliability of the entire receiving system, including image quality.

In addition, digital signals transmitted through networks such as public networks or wired networks eliminate this effect because there is a certain amount of jitter (Variation of Time Interval) due to the transmission stage and characteristics of the transmission wired or wireless line. The technique must be considered in conjunction with the operating clock frequency matching technique.

An example of a system for transmitting and receiving digital signals in the related art is a technology for matching a clock of a transmitter and a receiver in a digital TV system such as digital satellite broadcasting. In the MPEG standard, the current clock of an encoder is set to a variable called PCR. The counters are loaded at regular time intervals to match the operating clock frequency of the receiving side (encoder) to the operating clock frequency of the receiving side (encoder).

That is, if the encoder transmits the STC (System Time Clock) information of the encoder at a predetermined time interval in the PCR (Program Clock Reference), the decoder collects the PCR values of the predetermined time interval and calculates the average value, and the average value is transmitted to the operating clock frequency information of the transmitting side. The difference between the present encoder current clock frequency is determined, and then its own operating clock frequency is increased or decreased according to the magnitude and the sign of the difference value to coincide with the operating clock frequency of the transmitting side.

If the average value of PCR is used for a certain time as described above, the influence of jitter included in the STC decreases, and the mean of PCR mean control is, after all, averaging the difference between the encoder STC and the decoder STC in the PCR for a predetermined time. The value is compared with the operating clock frequency of the decoder to control the decoder operating clock frequency by the difference.

Fig. 1 shows a configuration of an average value calculation circuit of clock data for clock synchronization in a conventional digital signal receiver as described above.

The configuration is as follows: n buffers 101 for n data inputs, an adder 102 and an adder output buffer 103 for accumulating the values of the n buffers, and the n data accumulation values as n. It consists of a divider 104 and a divider output buffer 105 for dividing the average value.

The n buffers 101 store STC data (item: itme = difference between STC encoder and STC_decoder) transmitted from the encoder at regular intervals. The oldest data is evicted when the next data arrives and the most recent data is evicted. The data is stored in place (window size = n).

The n pieces of data are added by the adder 102 and the adder output buffer 103, and when the addition of the n pieces of data is completed, the divider output buffer 105 is divided by the divider 104 by n values. 1 / n average value is output on

The clock and control signals for addition, division and buffer operation control are supplied by a suitable and known control logic circuit.

As a result, the conventional clock data averaging circuit for clock synchronization of a digital signal receiver calculates and averages n pieces of data continuously inputted in time series from the most recent one, and divides them by 1 / n.

The clock data average calculation circuit for clock synchronization of a conventional digital signal receiver requires n buffers.

As already mentioned in calculating the average value for clock synchronization, the larger the value of n, the better.

However, increasing the value of n imposes a constraint on the increase of the buffer. In view of this, the value of n is inevitably limited.

Furthermore, even if the n value is appropriately selected, n buffers are required, and thus the complexity of the circuit configuration must be taken, and the circuit for n buffer control must be added as well as the signal processing by the n buffers. Increasing the level can also affect the performance and reliability of system operation.

The present invention aims to provide a data averaging circuit, in which there is no theoretical limit on the n value selected for averaging in averaging time series consecutively input data for a predetermined time interval, and thus the use of n buffers is further excluded. .

In particular, the present invention continuously accumulates n data for a predetermined time interval Tref, and when n data accumulation is completed, divides the accumulated value by 1 / n to obtain an average value, and then, from the n + 1 th data up to the previous time. A data average value calculating circuit is provided which adds an n + 1 th value to a value obtained by subtracting the average value from an accumulated value and calculates a data average value that always considers a difference between a sum and an average accumulated over time series.

Particularly, in the present invention, the decoder side to which the video compression transmission technique is applied can average the n STC information carried in the PCR to match the operating clock frequency and the system operating clock frequency of the encoder side, and use the average value as the clock matching information. A data averaging circuit is provided for clock synchronization of a digital signal receiver.

1 is a circuit diagram of an average value calculation circuit of clock data for clock synchronization in a conventional digital broadcasting receiver.

2 is a circuit diagram of an average value calculation circuit of clock data for clock synchronization in a digital signal receiver according to the present invention.

FIG. 2 is an embodiment of the present invention, comprising: first calculating means 201 for adding data continuously inputted in series in time series and subtracting an average value from a previous accumulated value, and the first calculating means ( A second calculating means 202 for accumulating the output value of 201 and inputting it to the first calculating means 201, a third calculating means 203 for averaging the output value of the second calculating means 202, and the first value. And output means 204 for storing and outputting the average value of the three calculation means 203 and providing this value as data for subtracting the accumulated value from the first calculation means 201 to the previous one when inputting the next data. A data average calculation circuit characterized in that it is configured, and the control of addition, subtraction, accumulation and output timing is supplied by an appropriate and known control logic circuit.

The average value calculation operation by the data average value calculation circuit of the present invention configured as described above is performed as follows.

First, an example of a sequence of data that is continuously input in time series is given below.

Item Input: A1, A2, ..., An, B1, B2, ... Bn, C1, ....

Initially, data A1 is input to the first calculating means 201, and this value is stored in the second calculating means 202.

The next data A2 is input to the first calculating means 201, and this value is added to the value A1 stored in the second calculating means 202, and the value A1 + A2 is stored in the second calculating means 202.

This series of operations is performed up to the data An so that the second calculation means 202 stores the sum of the n data from the data A1 to the data An, and the third calculation means (at the timing at which the sum of the n data has been added). 203 is operated to divide the sum by n values so that an average value for the n pieces of data is stored in the output means 204.

The value stored in the output means 204 is the average value AV1 of the first n data A1 to An, which is input to the first calculation means 201, and the first calculation means 201 performs the second calculation. The average value [AV1 = SM1 / n] is subtracted from the output of the means 202 (sum of A1 to An = SM1) and stored in the second calculating means 202.

When the next data B1 is input, the first calculating means 201 adds the output values [SM1-AV1] and data B1 of the second calculating means 202, and adds the new value SM1-AV1. + B1 = SM2 is stored in the second calculating means 202, and the third calculating means 203 divides the output of the second calculating means 202 by n to output a new average value to the output means 204. do.

That is, the new average value AV2 considering the data B1 is;

(SM1-AV1 + B1) / n = [(sum of A1-An)-(average of A1-An) + B1] / n.

The new average value AV2 is again subtracted from the first SM2 201 to AV2 in the previous SM2 (SM2-AV2), and the next sequence of data B2 is added and stored in the second calculation unit 202.

Therefore, the new addition value SM3 stored in the second calculating means 202 at this time is;

SM3 = SM2-AV2 + B2 (SM2 = SM1-AV1 + B1)

= (Sum of A1 to An)-(average of A1 to An) + B2

to be.

The average value AV3 is calculated by the third calculating means 203 with respect to the new addition value SM3, and the average value AV3 is again calculated by the output means 204 in consideration of the next order data B3. Is subtracted from the sum SM3 before B3.

This series of operations continues, and the average value is computed and outputted at every data input.

As described above, in the present invention, when calculating an average value for n data, the average value is obtained by accumulating the first n data, and then subtracting the average value from the accumulated value from the previous data, and then adding new data. It simply repeats the operation of finding a new average for the accumulated value.

That is, without using a buffer, when the next data arrives and a new average needs to be obtained, the previous sum is subtracted from the previous sum, and then new data is added to obtain a new sum and average.

In this operation, data averaging is performed, so that the clock side of the digital signal receiver transmits the operating clock frequency at the receiving side (decoder) without limiting the n value without using a buffer in averaging PCR information of a predetermined time interval. (Encoder) Can be controlled to follow the clock frequency accurately.

The data average value calculating circuit of the present invention does not require n input buffers conventionally in order to obtain an average value for n data which are continuously input in time series.

Therefore, the circuit configuration for clock synchronization of the digital signal receiver can be simplified and the signal processing step can be reduced, which contributes to the performance and reliability of the decoder system.

Also, since there is no need to use a buffer, there is theoretically no limit on the value of n.

This means that when considering jitter due to the characteristics of the transmission line (network) in a digital transmit / receive system, the value of n is freely selected to minimize the influence of jitter and the value of n can be extended to the optimal value without considering the hardware complexity. Can be.

Claims (2)

A new sum of means for obtaining a sum of data consecutively input in a time-series sequence; a means for obtaining an average of the sum; and a means for obtaining the sum by adding next data to a value obtained by subtracting the mean from the sum. And calculating a new average of the means for calculating the average with respect to the new sum, and calculating the average value using data that always considers the difference between the sum and the average accumulated over time series. First calculation means 201 for adding up data continuously inputted in time series and subtracting the average value from the previous accumulated value, and the first calculating means by accumulating the output value of the first calculating means 201. Storing the average value of the second calculating means 202 input to the 201, the third calculating means 203 for averaging the output value of the second calculating means 202, and the third calculating means 203 And output means (204) for outputting and providing this value as data for subtracting the accumulated value from the first calculation means (201) to the previous data input at the next data input.