KR100285436B1 - Adaptive equalizer - Google Patents

Abstract

The present invention relates to an adaptive equalizer, and more particularly, a first slave delayer for outputting n-1 first delay signals by cascading an input signal to a basic delay time, an input signal and the n-1 first delay signals. A real signal generator for adding a multiplier of n multipliers and a multiplier of n filter coefficients, and a multiplication result of the n multipliers to delay the filtered real signal to a first delay time and output a delayed real signal; A first delayer for delaying the output signal that has determined the signal to a first delay time, and generating a difference between the delayed actual signal and the delayed output signal as an error signal, multiplying the generated error signal by a step coefficient, and delaying the multiplication result by a second delay; A correction signal generation unit for outputting a filter coefficient correction signal by delaying with time, a second delayer for delaying the input signal with a third delay time, and a delayed input signal. A second slave delayer for outputting n-1 second delayed signals with a dependent delay based on a delay time, a delayed input signal, n-1 second delayed signals, and the delayed filter coefficient correction signal, respectively, to filter filter weights And n filter coefficient generators generating the next filter coefficient which is delayed by a fourth delay time by adding the obtained filter coefficient weight and the current filter coefficient. Therefore, in the present invention, the computational process is divided by using a delay device to improve the computational speed and to reduce the cost of one chip.

Description

Adaptive equalizer

TECHNICAL FIELD The present invention relates to an adaptive equalizer, and in particular, a divided look-ahead (RLA) pipe for a digital video disc (DVD), which can improve computation speed and reduce cost by one-chip by dividing the computation process by delay division. A pipelined LMS adaptive equalizer.

In general, when reproducing data stored on magnetic recording or high density optical discs, various distortions occur as the recorded signal undergoes reproduction. Factors causing such distortion include damage to the recording medium, deterioration of the reproduction unit, frequency change, and jitter.

In this way, a technique for reducing bit detection error by compensating for distortion caused by the reproduction process is called channel equalization. The equalizer, which implements such a technique, reduces interference between codes by compensating for distortion of a reproduction signal, and reduces channel interference over time. An adaptive equalization technique is one of adaptive compensation for characteristic changes.

The adaptive equalization technique has been steadily studied since the Least Means Squares (LMS) adaptive filter technique was proposed. In general, the adaptive equalization technique has a low convergence rate, but the LMS algorithm, which is easy to implement hardware because of the simple algorithm itself, is widely used.

In order to improve the problem of the equalizer using the LMS algorithm, the modified LLA-LMS technique (NRShanbhag and KK Parhi) improves the computation speed while maintaining the performance similar to the existing algorithm by slightly modifying the delay characteristics of the LMS. , ″ Relaxed look-ahead pipelined LMS adaptive filters and their application to ADPCM, ″ IEEE Trans.circuit and systems, vol. 40, no. 12, DEC. 1993).

Look-Ahead Tec. (LAT) refers to a technology that converts an existing algorithm into a pipeline algorithm using input data previously calculated so that input and output values do not change compared to the existing algorithm. RLAT (Relaxed Look-Ahead Tec.) This method maintains the performance of the algorithm without maintaining accurate I / O mapping.

In the case of the LMS algorithm, the design of the LAT technique increases the complexity of the hardware. However, even if the input or output of the block that performs the multiplication or addition operation to carry out the LMS algorithm maintains a little delay characteristic with the rule, the convergence characteristic of the LMS algorithm has little effect. This reduces complexity, speeds up hardware operations, and maintains reasonable performance.

1 is a block diagram showing an adaptive equalizer structure using a conventional LMS algorithm.

The conventional LMS algorithm defines the filter coefficient W (n), the step size μ controlling the stability, the determination error e (n), and the input vector value U (n), as shown in Equation (1) below. Is expressed.

W (n) = W (n-1) + μe (n) U (n)

e (n) = d (n)-d ^ (n)

e (n) = d (n)-W ^T (n-1) U (n)

D (n) represents a determination value, and d ^ (n) means an actual output value.

In the LMS scheme, a signal output from the first slave delay unit 10 passes through a multiplier 12, an actual signal generator 14, an error signal generator 16, a correction signal generator 18, and a filter coefficient generator 22. All of these calculation processes ① must be made until the next filter coefficients are generated. Therefore, the processing speed is determined by these calculation times.

2 shows the structure of a conventional RLA adaptive equalizer. In the RLA method of FIG. 2, when a relaxation technique is applied to Equation (1) by applying a delay relaxation technique, Equation (2) is represented.

W (n) = W (n-1) + μe (n-D1) U (n-D1)

In Equation (1) and Equation (2), the output result is different, but in Equation (2), if the adaptive coefficient μ, which is the step size of the adaptive equalizer, has an appropriate value, the adaptive equalizer It does not significantly affect the convergence characteristic of updating the filter coefficient W (n).

If the sum relaxation technique is applied and the expression coefficient (μ), which is the step size of the adaptive equalizer of Equation (2), is subtracted and reexpressed, the following equation (3) and (4) can be arranged. have.

W (n) = W (n-1) + μe (n) U (n)

Second term of Equation (4) Equation (4) can be expressed as Equation (5) if the change of? Is slow. That is, when LA≤M (M: number of delays, LA: integer value), Equation (4) is expressed as Equation (5) by a relaxation technique.

The Relaxed Look-Ahead Technology (RLAT) using the least mean square (LMS) algorithm using the delayed relaxation technique and the sum relaxation technique described above is ) And the integer value LA can be changed from 1 to D ₂ .

e (n) = d (n)-W ^T (n-D2) U (n)

That is, in FIG. 2, an output signal from the first slave delayer 10 is generated by a multiplier 12, an actual signal generator 14, an error signal generator 16, and a correction signal generator 18. The first operation process ① and the second operation process ② through the filter coefficient generator 24 are divided by the delay unit 26. In order to match the delay time, the input signal is also delayed by the same time through the delay unit 28 and provided to the filter coefficient generator 24.

Therefore, since the total operation time is determined by the process having the most operation time among the first operation process and the second operation process, the operation time can be shortened as compared with the LMS method of FIG. 1.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide an adaptive equalizer that can improve the operation speed and reduce the cost in one chip by calculating by multi-stepping the operation process into a delay unit. have.

1 is a block diagram showing an adaptive equalizer structure using a conventional LMS algorithm.

Figure 2 is a block diagram showing the structure of a conventional RLA adaptive equalizer.

3 is a block diagram of a preferred embodiment of an RLA adaptive equalizer according to the present invention;

4 is a block diagram of another preferred embodiment of an RLA adaptive equalizer according to the present invention;

<Description of the code | symbol about the principal part of drawing>

10: first slave delay 12: multiplier

14, 30, 44: actual signal generator 16, 48: error signal generator

18, 34, 50: correction signal generator 20: second slave delay

22, 24: filter coefficient generator 26, 28, 32, 36, 46, 52: delay

40: delay multiplier 42: delay adder

In order to achieve the above object, the first equalizer of the present invention is a first slave delayer for outputting n-1 first delayed signals by cascading an input signal by a basic delay time, and an input signal and the n-1 th delayer. Generates a real signal that outputs a delayed real signal by delaying the filtered real signal to a first delay time by adding the multipliers of n multipliers and n multipliers, respectively, to multiply one delayed signal and n filter coefficients, respectively. A first delayer for delaying the output signal that has determined the actual signal to a first delay time, and generating a difference between the delayed real signal and the delayed output signal as an error signal and multiplying the generated error signal by a step coefficient and multiplying the result; A correction signal generator for outputting the filter coefficient correction signal by delaying the signal to the second delay time, a second delayer for delaying the input signal to the third delay time, and a delayed input. A second slave delayer for delaying the call with a basic delay time and outputting n-1 second delay signals, a delayed input signal and n-1 second delay signals and the delayed filter coefficient correction signal, respectively, And n filter coefficient generators for generating the filter coefficient after delaying the fourth delay time by obtaining the filter coefficient weight and adding the obtained filter coefficient weight and the current filter coefficient. The third delay time of the fourth delay is the sum of the first and second delay times.

The second equalizer of the present invention is a first slave delayer for outputting n-1 first delayed signals by cascading an input signal to a basic delay time, and an input signal and the n-1 first delayed signals and n filters. N first delay multipliers for multiplying the coefficients and delaying the result of the multiplication by the base delay time, and n / 2 for adding the respective outputs of the n delay multipliers in pairs and delaying each addition result as the base delay time. A real signal generator for generating a filtered real signal by adding all of the first delay adders and the outputs of the n / 2 delay adders and delaying the filtered real signal with a basic delay time to output a delayed real signal; The delay signal outputs the delayed output signal by delaying the output signal that determines the actual signal to the default delay time, and the difference between the delayed actual signal and the delayed output signal. A second delay adder for generating and delaying the generated error signal to the basic delay time, a second delay multiplier for multiplying the delayed error signal and the step coefficient and delaying the multiplication result to the basic delay time and outputting a filter coefficient correction signal; A second delay delaying the input signal with the first delay time, a second delay delay delaying the delayed input signal with the basic delay time and outputting n-1 second delay signals, a delayed input signal, and n-1 Filter coefficient weights are obtained by inputting the second second delay signals and the filter coefficient correction signal, respectively, and adding the obtained filter coefficient weights and the current filter coefficients to generate the next filter coefficients as the second delay time. It is characterized by including.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows one preferred embodiment of the adaptive equalizer according to the invention. In FIG. 3, the equalizer has a first slave delayer 10, a multiplier 12, a real signal generator 30, a delayer 32, a correction signal generator 34, a second slave delayer 20, and a filter coefficient. Generator 24, delay 36.

In the first slave delayer 10, the input and output of the n-1 delay units DL1 having the delay characteristic of the basic delay time D are dependently connected to each other so that the basic delay is applied to the input signal U (n). The sub-delayed time D outputs the n-1 first delay signals U (n-iD).

The multiplier 12 is composed of n multipliers MP1 and each of the input signal U (n) and the n-1 first delay signals U (n-iD) and n filter coefficients W (ni), respectively. Multiply.

The real signal generator 30 adds the multiplication results of the n multipliers and adds AD1 to output the filtered real signal, and delays the filtered real signal by the first delay time D3 to delay the real signal d '. and a delay unit DL2 for outputting (n-D3).

The first delay unit 32 outputs the delayed output signal d (n-D3) by delaying the output signal d (n) obtained by judging the actual signal by the determination means (not shown) by the first delay time D3. .

The correction signal generator 34 includes an adder AD2, a multiplier MP2, and a delay DL3, and the difference between the delayed real signal d '(n-D3) and the delayed output signal d (n-D3) is determined. Generate the error signal e (n-D3), multiply the generated error signal e (n-D3) by the step coefficient μ, and delay the multiplication result by the second delay time D1 to filter coefficient correction signal μe (n-D3). Outputs -D1).

The second delay unit 28 delays the input signal U (n) with a third delay time D1 + D3 and outputs it.

The second slave delay unit 20 includes n-1 delay units DL3, and dependently delays the delayed input signal U (n-D3-D1) with a basic delay time D so that n-1 delay units are delayed. 2 Outputs delay signals U (n--iD-D3-D1).

The filter coefficient generator 24 includes a multiplier MP3, delayers DL5, adders AD3, adder AD4, delayer DL6, a delayed input signal and n-1 second delays. Input the signals and the delayed filter coefficient correction signal, respectively, to obtain the filter coefficient weight shown in Equation (7), add the obtained filter coefficient weight and the current filter coefficient, and delay the result with the fourth delay time (D2). Generate a coefficient.

In one embodiment of the present invention, as shown in Figure 3, the entire operation process is divided into the first operation process ①, the second operation process ②, the third operation process ③ of the process that takes the most calculation time in each process The operation time is determined in the entire operation time. Therefore, the overall computation time can be reduced by dividing into three stages compared to the conventional two stage division.

4 shows another embodiment of an adaptive equalizer according to the invention. In FIG. 4, another embodiment includes a first slave delayer 10, a second slave delayer 20, a filter coefficient generator 24, a delay multiplier 40, a delay adder 42, and an actual signal generator 44. And a delay unit 46, an error signal generator 48, a correction signal generator 50, and a delay unit 52.

The first slave delay unit 10 includes n−1 delays DL1 and outputs n−1 first delay signals by slavely delaying an input signal with a basic delay time.

The n first delay multipliers 40 each include a multiplier MP1 and a delay DL7, and multiply the input signal and the n-1 first delay signals by n filter coefficients and multiply the multiplication result. The delay is output with the basic delay time (D).

Each of the n / 2 first delay adders 42 includes an adder AD5 and a delay DL8, and adds pairs of outputs of the n delay multipliers and adds each addition result as a basic delay time. Delay output.

The real signal generator 44 includes an adder AD1 and a delayer DL2, and adds each of the outputs of the n / 2 delay adders to generate a filtered real signal and bases the filtered real signal on a basic delay time. Delay to output the delayed actual signal.

The delay unit 46 outputs the delayed output signal by delaying the output signal which determines the actual signal by the basic delay time D.

The error signal generator, i.e., the second delay adder 48, includes an adder AD2 and a delay DL9, and generates a difference between the delayed real signal and the delayed output signal as an error signal and converts the generated error signal into a basic delay time. Delay to (D).

The correction signal generator, that is, the second delay multiplier 50 includes a multiplier MP2 and a delay DL3, multiplies the delayed error signal with the step coefficient and delays the multiplication result by the basic delay time D to filter coefficients. Output the correction signal.

The second delay unit 52 delays the input signal by the first delay time 5D.

The filter coefficient generator 24 includes a multiplier MP3, an adder AD3, a delayer DL5, an adder AD4, and a delayer DL6, and dependently delays the delayed input signal with a basic delay time. a second slave delayer for outputting n-1 second delayed signals, a delayed input signal, n-1 second delayed signals, and the filter coefficient correction signal, respectively, and the filter coefficients shown in Equation (8) below. The next filter coefficient is generated as the second delay time by obtaining the weight and adding the obtained filter coefficient weight and the current filter coefficient.

In another embodiment of the present invention, as shown in Figure 4, the entire operation process is the first operation process ①, the second operation process ②, the third operation process ③, the fourth operation process ④, the fifth operation process ⑤, the fifth 6 Operation process ⑥ It is divided into 6 steps and the operation time of ① and ⑤ process that takes the most computation time in each process is determined in the whole operation time. Therefore, the overall computation time can be reduced by dividing into six stages compared to the conventional two stage division.

In another embodiment, the second computational process consists of delays and adders in a tree structure that is reduced to exponential. In this case, the delay time DT of the second delay unit 52 is expressed by the following equation (9).

DT = 3D + CEIL (log ₂ n) D

Here, CEIL (X) is a function that is maintained as long as the value of X is an integer and is rounded up to X + 1 when the value is less than the decimal point. n represents the number of taps of the first slave delayer, that is, the number of delayers. 3 represents the number of delays DL2 of the actual signal generator, delays DL9 of the error signal generator, and delays DL3 of the correction signal generator.

If the number of retarders, n, is a power of two, the logarithmic value is an integer. For example, if n is 4, DT is determined as 3D + 2D = 5D. If n is not a power of 2, logarithm is a fractional value, so the value is rounded down. For example, if n is 3, the log value is 1.5828, so the decimal point is rounded up by CEIL and treated as 2. Thus, DT is determined to be 3D + 2D = 5D.

As described above, in the present invention, the calculation speed is determined by the maximum operation time of each division step by dividing the calculation process for correction of the filter coefficient by the delay division and calculating each division step. Therefore, the operation speed can be increased and the cost can be reduced in one chip.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit of the invention described in the claims below. You will understand.

Claims (4)

A first slave delayer for delaying an input signal with a basic delay time to output n−1 first delay signals; N multipliers for multiplying the input signal and the n-1 first delay signals with n filter coefficients, respectively; A real signal generator for adding the multiplication results of the n multipliers to delay the filtered real signal with a first delay time and output a delayed real signal; A first delayer for delaying the output signal determining the actual signal with a first delay time; A correction signal generator for generating a difference between the delayed real signal and the delayed output signal as an error signal, multiplying the generated error signal by a step coefficient, and delaying the multiplication result by a second delay time to output a filter coefficient correction signal; A second delayer for delaying the input signal with a third delay time; A second slave delayer for dependently delaying the delayed input signal with a basic delay time and outputting n-1 second delay signals; Filter delay weights are obtained by inputting the delayed input signal, n-1 second delay signals, and the delayed filter coefficient correction signal, respectively, and delayed by a fourth delay time by adding the obtained filter coefficient weight and the current filter coefficient. An adaptive equalizer comprising n filter coefficient generators for generating a coefficient. The adaptive equalizer of claim 1, wherein the third delay time of the fourth delay unit is a sum of the first and second delay times. A first slave delayer for delaying an input signal with a basic delay time to output n−1 first delay signals; N first delay multipliers for multiplying the input signal and the n-1 first delay signals with n filter coefficients and delaying the multiplication result with a basic delay time; N / 2 first delay adders for adding pairs of outputs of the n delay multipliers and delaying each addition result with a basic delay time; A real signal generator for adding the respective outputs of the n / 2 delay adders to generate a filtered real signal and delaying the filtered real signal with a basic delay time to output a delayed real signal; A delayer for delaying the output signal determining the actual signal with a basic delay time and outputting a delayed output signal; A second delay adder for generating a difference between the delayed real signal and the delayed output signal as an error signal and delaying the generated error signal with a basic delay time; A second delay multiplier for multiplying the delayed error signal by a step coefficient and delaying the multiplication result by a basic delay time to output a filter coefficient correction signal; A second delayer for delaying the input signal with a first delay time; A second slave delayer for dependently delaying the delayed input signal with a basic delay time and outputting n-1 second delay signals; The filter coefficient weight is obtained by inputting the delayed input signal, n-1 second delay signals, and the filter coefficient correction signal, respectively, and the next filter coefficient is calculated as the second delay time by adding the obtained filter coefficient weight and the current filter coefficient. Adaptive equalizer characterized in that it comprises n number of filter coefficient generators. The method of claim 1, wherein the first delay time DT is DT = 3D + CEIL (log ₂ n) D Where n is the number of taps of the first slave delayer, 3 is the sum of the basic delay time of the actual signal generator, the basic delay time of the second delay adder, and the basic delay time of the second delay multiplier, and D is the basic delay time. Adaptive equalizer, characterized in that determined by.