KR100284289B1 - Analog / Digital Converter - Google Patents

Abstract

The present invention relates to an analog-to-digital converter, and conventionally requires additional logic to correct the offset voltage in the comparator, the area is large when configured on-chip, thereby increasing the power consumption, and also to correct the offset The time required to generate the bias voltage is long, and additional clock for offset correction is required in addition to one clock period for determining one bit value, which increases the time required for converting N bits. There was a problem that the use of the system was restricted. Accordingly, the present invention sequentially compares the output signal of the esl part to determine and output the bit value by setting the most significant bit to '1' and all remaining bits to '0', and converting the output signal of the esl part to analog. A digital / analog converter for generating a voltage and an analog / digital converter for comparing a comparison voltage and an input analog signal to determine a most significant bit value as '1' or '0' and output the result to the SA unit. And an offset correction circuit positioned between the digital / analog converter and an SD unit to determine an offset value of the comparator initially and correct the offset accordingly, thereby reducing the size of the device and reducing power consumption. In addition, the conversion time can be shortened by reducing the number of clocks used for analog / digital conversion. There is an effect that can be removed as an offset.

Description

Analog / Digital Converter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter, and more particularly, to eliminates errors due to offset voltage generated from a comparator that determines digital data by comparing analog values and digital values in an analog type analog / digital converter. The present invention relates to an analog-to-digital converter that improves the speed and the conversion time.

Digital signals for voice or image information or physical variations can be processed and processed using many useful digital signal processing techniques. Therefore, in order to apply many useful digital technologies to the digital signal, the analog signal must be converted into a digital signal of a predetermined bit.

1 is a block diagram showing the configuration of a typical Successive Approximate Register type analog / digital converter. As shown therein, the most significant bit is set to '1' and all remaining bits are set to '0'. And the ES part 12 which outputs the determined most significant bit (MSB) value to the outside; A digital / analog converter 10 which receives the output signal of the SL unit 12 and converts it into an analog signal; The output signal of the digital-to-analog converter 10 is applied to the inverting terminal (-), the input analog signal Va is applied to the non-inverting terminal (+), and compared to compare the corresponding signal according to the It consists of the comparator 11 which outputs to the egg part 12. FIG.

FIG. 2 is a circuit diagram showing the configuration of the comparator 11. As shown therein, a pull-up signal CS1 is applied to a gate, a power supply voltage VDD is applied to a source, and a drain is connected to node A. Most transistors PM10 and PM11, an input analog signal VSUM is applied to a gate, node A is connected to a source, and node B is connected to a drain, and the PMOS transistor PM12. The NMOS transistor NM11 having a source applied to its gate, a common mode voltage VCM applied to its drain, a reset voltage PSMP applied to its gate, a drain connected to the node A, and a drain connected to the node C. Connected to the gate, the PMOS transistor PM13 to which the output signal VSUMR of the digital / analog converter is applied, the source to the gate of the PMOS transistor PM13, and the common mode voltage VCM to the drain are applied. The NMOS transistor N having the reset voltage PSMP applied to the gate M12), a drain is connected to the node B, a source is grounded, an NMOS transistor NM13 to which a first bias voltage BIASN is applied to the gate, a drain is connected to the node B, and a source is grounded. An NMOS transistor NM14 having a reference voltage VREF applied to its gate, a drain connected to the node C, a source grounded, and an NMOS transistor having a second bias voltage BIAS applied to the gate thereof. NM16 and an NMOS transistor NM15 having a drain connected to the node C, a source connected to ground, and a reference voltage VREF applied to a gate, and output signals Vout1 at nodes B and C, respectively. , (Vout2) is output.

FIG. 3 is a circuit diagram showing a conventional offset compensation circuit. An inverter INV1 for inverting an output signal of a comparator, an output signal of the comparator is applied to a drain, and a clock signal P2 is gated. An nMOS transistor NM20 applied to the drain and a source of the NMOS transistor NM20 are connected to a drain, a clock signal P3 is applied to the gate, and an NMOS22 NM22 source connected to the node D. A PMOS transistor (PM20) to which an output signal of the comparator is applied to a source, a PMOS transistor (PM22) having a source connected to a drain of the PMOS transistor (PM20), and having a drain connected to the node D; A capacitor C1 having one side connected to the node D, the other side of which is grounded, an output signal of the inverter INV1 being applied to a drain, and an NMOS21 transistor NM21 having a clock signal P2 applied to a gate; , The NMOS transistor (NM2) A drain is connected to the source of 1), a clock signal P3 is applied to the gate, an MOS transistor NM23 having a source connected to the node E, and an output signal of the inverter INV1 are applied to the source. A source is connected to the PMOS transistor PM21 whose gate is connected to the gate of the PMOS transistor PM20 and the drain of the PMOS transistor PM21, and the gate is connected to the gate of the PMOS transistor PM22. And a drain (PM23) having a drain connected to the node E, a capacitor C2 connected at one side to the node E, and grounded at the other side, and output signals BIASN at the nodes D and E. (BIAS) is outputted, and the operation | movement of such a conventional apparatus is demonstrated.

First, the SL unit 12 transmits an output signal in which the most significant bit MSB is set to '1' and the remaining bits are set to '0', to the digital / analog converter 10.

In this case, the most significant bit (MSB) has a value of VDD / 2, the remaining bits have a value multiplied by VDD / 2 sequentially, and finally the least significant bit (LSB) VDD / 2 ^N Has the value

Accordingly, the digital / analog converter 10 receives the output signal of the SL unit 12 and converts it into an analog signal and applies it to the inverting terminal (-) of the comparator 11.

Then, the comparator 11 compares the analog signal with the input analog signal VSUMR applied to the non-inverting terminal (+), and if the input analog signal VSUM is large, a value of '1' is input. If the log signal VSUM is small, a value of '0' is applied to the SL unit 12.

Accordingly, the RS part 12 determines the output value of the comparator 11 as the most significant bit (MSB) value, and repeats the above process with the next bit as the most significant bit (MSB), thereby resolving the value of each bit. Is set to '0' or '1'.

That is, the value determined by the SL unit 12 becomes a digital value with respect to the analog input signal VSUM.

In this case, an operation for correcting the offset generated in the comparator 11 will be described.

First, in FIG. 2, when the clock signal P1 is '1' in the first and second bias voltages BIASN and BIAS in the VDD / 2 state, the reset signal PSMP becomes '1' and thus the NMOS transistor NM11 and NM12 are turned on, and accordingly, a reset voltage PSMP is applied to the gates of the PMOS transistors PM12 and PM13.

Thereafter, after the reset signal PSMP becomes '0', an offset is generated by comparing the analog input signal VSUM with the output signal VSUMR of the digital / analog converter 10. Then, the voltage of the output signal Vout1 is generated. To change the final output stage (CMPN) to high or low depending on the offset.

Thereafter, as the final output signal CMPN is low or high, the first and second bias voltages are adjusted by the clock signals P2 and P3 to correct the offset.

At this time, the clock signals P1 to P3 are sequentially generated.

For example, if a positive offset is applied to the input analog signal VSUM, the voltage level applied to the gate of the PMOS transistor PM12 to which the input analog signal VSUM is applied increases, so that the PMOS transistor PM12 is accordingly increased. ), The voltage applied to the node C is lowered, so that the voltage applied to the node C becomes high, and thus the output signal Vout becomes high, and thus the final output terminal has a low voltage level.

Because the comparator is usually connected in two or three stages, the first and second output signals Vout1 and Vout2 are compared again in the comparator and the final output signal CMPN is compared to the compensating circuit. Will be entered.

As a result, when the voltage applied to the final output terminal CMPN is lowered, the bias signal BIASN is dropped and the bias signal BIAS is given in FIG. 3. Accordingly, the input analog signal VSUM including the offset becomes a voltage. The level will drop so it is corrected.

However, the conventional apparatus operating as described above requires additional logic to correct the offset voltage in the comparator, so that the area becomes large when configured on-chip, thereby increasing power consumption and generating a bias voltage for correcting the offset. In order to use the high speed system, the time required to convert the N bits is longer because the time required for the conversion is longer, and an additional clock for offset correction is required in addition to one clock cycle for determining one bit value. There was a problem that was limited.

Accordingly, the present invention devised in view of the above problems eliminates errors due to offset voltage generated from a comparator for determining digital data by comparing analog values and digital values in an analog-type analog / digital converter. The aim is to provide an analog-to-digital converter that improves precision and reduces conversion time.

1 is a block diagram showing the configuration of a conventional analog / digital converter.

2 is a circuit diagram showing the configuration of a comparator in FIG.

3 is a circuit diagram showing a configuration of a conventional offset correction circuit.

Figure 4 is a block diagram showing the configuration of the analog / digital converter of the present invention.

5 is a block diagram showing the configuration of an offset correction circuit in FIG.

***** Description of the symbols for the main parts of the drawings *****

40: Digital / Analog Converter 41: Comparator

42: SL 43: Offset correction circuit

In order to achieve the above object, the present invention sequentially sets the most significant bit to '1' and all remaining bits to '0' to determine and output a bit value, and the output signal of the ES part. A digital / analog converter for generating a comparison voltage by converting to analog, and comparing the comparison voltage with the input analog signal to determine the most significant bit value as '1' or '0' and outputting the result to the SA unit In the log / digital converter, characterized in that it further comprises an offset correction circuit located between the digital / analog converter and the SL unit, initially determines the offset value of the comparator and corrects the offset accordingly. do.

Hereinafter, the operation and effect of the analog / digital converter according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing the configuration of the analog / digital converter of the present invention. As shown in FIG. 4, the most significant bit is sequentially set to '1' and all remaining bits are set to '0' to determine and output a bit value. An analog part 42 and a digital / analog converter 40 which converts the output signal of the SL part 42 into an analog signal to generate a comparison voltage, and compares the comparison voltage with the input analog signal A comparator 41 for determining a most significant bit value as '1' or '0' and outputting the result to the SL unit 42; It is composed of an offset correction circuit 43 located between the digital / analog converter 40 and the SL unit 42 to initially determine the offset value of the comparator 41 and correct the offset accordingly.

5 is a block diagram showing the configuration of the offset correction circuit. As shown in FIG. 5, a star register 51 for outputting a comparison digital signal for offset measurement, and the comparison digital signal through a bus interface 50 are shown in FIG. A first data register 53 for storing digital data obtained through an interface; An adder (54) for obtaining a difference value between the digital data stored in the first data register (53) and the initial digital data of the star register (51); An offset register 52 for storing the addition value of the adder 54 as an offset value; A second data register 55 for storing final digital data from which the offset is removed; The controller 56 is configured to control each unit as well as to output an initial offset control signal. The operation of the present invention configured as described above will be described using an example of 2 bits.

If normal, that is, no offset, the star register 51 of the first offset correction circuit 43 inputs '10' to the digital / analog converter 40.

Then, the digital / analog converter 40 converts the '10' into an analog signal and outputs a normal VDD / 2.

At this time, the control unit 56 of the offset correction circuit 43 conducts the transmission gate G40 with an offset control signal to convert the VDD / 2, which is the first output signal of the digital / analog converter 40, into a comparator voltage. 41 is applied to the non-inverting terminal (+), and the transfer gate G40 is first turned off and then cut off.

Since there is no offset in the above, the comparator 41 applies a '1' to the ES 42, and then the SL 42 has the most significant bit value and the output value of the comparator 41 so that the most significant bit. After the value is determined to be '1', the next most significant bit is set to '1', that is, '11' is applied to the digital / analog converter 40.

Thereafter, the digital / analog converter 40 converts '11' to apply an analog signal of 3VDD / 4 to the inverting terminal (-) of the comparator 41, and then the comparator 41 has a non-inverting terminal. Since the voltage applied to the inverting terminal (-) is smaller than that of VDD / 2 of (+), '0' is applied to the RS part 42.

Accordingly, the RS 42 determines the value of the second bit as '0' so that the digital code of VDD / 2 is '10'.

At this time, the first data register 53 of the offset correction circuit 43 stores the '10' and obtains a difference from the value of the star register 51 by the adder 54 after storing the digital code value. The offset is '0' and this value is stored in the offset register 52, and then the process of converting the input analog signal into a digital signal is executed.

If an offset occurs, the start register 51 of the first offset correction circuit 43 inputs '10' to the digital / analog converter 40.

Then, the digital / analog converter 40 converts the '10' into an analog signal and outputs a normal VDD / 2.

At this time, the control unit 56 of the offset correction circuit 43 conducts the transfer gate G40 as an offset control signal to compare the offset voltage with VDD / 2, which is the first output signal of the digital / analog converter 40, to the offset voltage. In this case, the non-inverting terminal (+) of the comparator 41 is applied to sample the sample, and the transfer gate G40 is first turned on and then cut off.

Thereafter, the comparator 41 applies a '1' to the RS part 42 because the non-inverting terminal (+) is larger than the inverting terminal (-), and then the SL part 42 has the most significant bit value and the comparator. Since the output value of (41) coincides, the most significant bit value is determined to be '1', and then the most significant bit is set to '1', that is, '11' is applied to the digital / analog converter 40.

Thereafter, the digital / analog converter 40 converts '11' to apply an analog signal of 3VDD / 4 to the inverting terminal (−) of the comparator 41.

At this time, if it is assumed that the offset voltage is greater than VDD / 4, the comparator 41 outputs '1'. Accordingly, the SL 42 matches the most significant bit value and thus determines the second bit as '1'.

At this time, the first data register 53 of the offset correction circuit 43 stores the '11' and obtains the difference from the value '10' of the star register 51 by the adder 54 after storing the digital code value. At this time, the difference value '01' is an offset and this value is stored in the offset register 52.

Thereafter, when the input analog signal Va is converted into a digital signal, the offset is added to all the digital values by the adder 54 and stored in the second data register 54 as the final digital value.

As described in detail above, the present invention can reduce the power consumption by reducing the size of the device, and also shorten the conversion time by reducing the number of clocks used for analog / digital conversion, and also with a single conversion time. This has the effect of eliminating the offset.

Claims (4)

Sequentially converting the most significant bit to '1' and all remaining bits to '0' to determine the bit value and output the digital signal to convert the output signal of the ES part to analog to generate a comparison voltage The analog / digital converter, which compares the comparison voltage and the input analog signal, determines the most significant bit value as '1' or '0', and outputs the result to the SAL unit. And an offset correction circuit located between the log converter and the SL unit, which initially determines the offset value of the comparator and corrects the offset accordingly. The method of claim 1, further comprising a transmission gate that receives an offset control signal of the offset correction circuit to the inverting terminal and the control signal is applied to the non-inverting terminal through an inverter to pass the first generated comparison voltage. Analog-to-digital converter. 2. The analog / digital converter according to claim 1, wherein the comparator determines the offset value using the first output signal of the digital / analog converter as the analog input signal. 2. The apparatus of claim 1, wherein the offset correction circuit comprises: a star register for outputting a comparison digital signal for offset measurement, and a first data register for storing digital data obtained by interfacing the comparison voltage through a bus interface bus; An adder for obtaining a difference value between the digital data stored in the first data register and the initial digital data of the star register; An offset register for storing the addition value of the adder as an offset value; A second data register for storing final digital data from which the offset is removed; An analog / digital converter characterized in that the control unit for controlling the overall control and outputting the initial offset control signal.