KR100283693B1 - Efficient filter by using the structure of interpolated fir filter - Google Patents

Abstract

1. Fields to which the invention described in the claims belong

The present invention relates to an efficient filter using an interpolation technique.

2. The technical problem to be solved by the invention

An object of the present invention is to provide an efficient filter using an interpolation technique in which two or more filters are shared at the same time, thereby sharing the resources independently and the processing speed and performance of each independently implemented, while greatly reducing hardware complexity.

3. Summary of the Solution of the Invention

The present invention includes: first multiplexing means for receiving a first signal and a second signal from the outside and selectively outputting one of the first and second signals according to a multiplexing control signal from the outside; First filtering means for multiplying and outputting a signal output from said first multiplexing means by a tap coefficient selected according to an external tap coefficient control signal; At least one second filtering means for delaying the signal output from the first multiplexing means for a predetermined period and then multiplying the selected tap coefficient according to the tap coefficient control signal; Addition means for summing signals output from the first and second filtering means; And demultiplexing means for performing demultiplexing and ordering of signals output from the adding means in accordance with an output control signal from the outside, wherein the demultiplexing means differs from a portion where the required coefficient is zero by using an interpolation technique. Processing the coefficients of the filter to combine at least two filters into one, characterized in that to share resources.

4. Important uses of the invention

The present invention can be applied where more than two filters are required.

Description

Efficient Filter Using Interpolation Technique {EFFICIENT FILTER BY USING THE STRUCTURE OF INTERPOLATED FIR FILTER}

The present invention relates to an efficient filter using an interpolation technique, and more particularly, to an efficient filter using an interpolation technique in which hardware of two digital filters is shared to reduce hardware.

Conventionally, in case of a digital transmitter that requires two or more filters with M taps, the required number of filters are used as they are, or when the filters operate in a low speed mode, hardware resources between filters are shared by time sharing. It was.

As such, in the related art, when multiple digital filters are simultaneously required on one chip, as many independent filters are implemented as necessary. In addition, when the filter does not require high-speed signal processing speed, the complexity of hardware is improved by sharing resources among filters by time division, which requires twice as much hardware operation speed as each independent filter. There is this. Looking at this in more detail as follows.

In the IS-95 Code Division Multiple Access (CDMA) mobile communication system, data is modulated using quadrature phase shift keying (QPSK) spread spectrum in both forward and reverse transmission. Transmitted data is spread across the in-phase (I) and quadrature-phase (Q) channels and then passed through a band-limiting filter.

Filters greatly affect the complexity of hardware in digital transceivers. In the prior art, if multiple digital filters are needed at the same time, filters are independently implemented as many as necessary. In particular, it is important to optimize this when there are limited hardware resources available to the implementation.

One way to reduce hardware complexity is to share resources using time division. However, this method has a problem that it is almost impossible to apply when high-speed operation such as a CDMA transceiver is required because the system operation speed should be increased more than twice.

In order to solve the above problems, the present invention provides an interpolation technique in which two or more filters are shared at the same time, thereby sharing the resources, and having the same processing speed and performance as those independently implemented, while greatly reducing hardware complexity. The purpose is to provide an efficient filter.

1 is a conceptual diagram illustrating an N-fold interpolation process of a digital filter.

2 is a structural diagram of a digital filter having a general polyphase N structure.

3A to 3D are exemplary spectrum diagrams for explaining a low frequency filter design method using an IFIR design scheme.

4 is a structural diagram of an efficient filter using an interpolation technique according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21-1 to 21-N, 41, 42-1 to 42-N, 48, 49: multiplexer

23-1 to 23- (N-1), 44-1 to 44- (N-1), 47: delay element

22-1 to 22-N, 43-1 to 43-N: Multipliers

24, 45: adder

46: demultiplexer

In order to achieve the above object, the present invention comprises: first multiplexing means for receiving a first signal and a second signal from the outside and selectively outputting one of the first and second signals according to a multiplexing control signal from the outside; First filtering means for multiplying and outputting a signal output from said first multiplexing means by a tap coefficient selected according to an external tap coefficient control signal; At least one second filtering means for delaying the signal output from the first multiplexing means for a predetermined period and then multiplying the selected tap coefficient according to the tap coefficient control signal; Addition means for summing signals output from the first and second filtering means; And demultiplexing means for performing demultiplexing and ordering of the signals output from the adding means in accordance with an output control signal from the outside, wherein the demultiplexing means differs from the portion where the required coefficient is zero by using an interpolation technique. By processing the coefficients of the filter it is characterized in that at least two filters are combined to share resources.

In the present invention, the IFIR (Interpolated FIR) filter design scheme uses zero alternately. When the tap coefficient of one of the two filters is 0, the other one uses hardware resources. Two filters can be implemented using only hardware resources required for the two filters.

In the CDMA mobile communication system, the digital transmit filter occupies almost half of the digital transmitter chip. The present invention allows two digital transmit filters to share resources, thereby reducing the size of the chip hardware and reducing the chip size and cost. Can bring

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the application of the Interpolated Finite Impulse Response (IFIR) design scheme allows the independent filters of each of the I / Q channels to share resources, thereby reducing hardware complexity by almost half.

1 is a block diagram of a general digital transmission filter.

In general, as shown in FIG. 1, the digital transmission filter oversamples the digital data to be transmitted N times, and then processes the filter such as waveform shaping and band limitation.

An expander 11 oversamples N times the digital data to be transmitted.

The interpolation filter 12 receives an oversampled signal and performs processing such as waveform shaping or band limitation.

1 is implemented by the polyphase N method of the filter tap number M, as shown in FIG. 2.

FIG. 2 is a structural diagram of the filter of FIG. 1 implemented using the polyphase N method of the filter tap number M. Referring to FIG.

The multiplexer 21-1 selects and outputs one of the tap coefficients according to the tap coefficient control signal, and the tap coefficient control signal is changed at an N-times speed of the input signal. 2, … , N-1 cycles through the values.

The multiplier 22-1 multiplies the input signal by the filter coefficient selected by the multiplexer 21-1. In the multiplexer 21-1, since the filter coefficients change at an N-times speed of the input signal, the output of the multiplier is over-sampled and processed N times.

Delays 23-1 to 23- (N-1) are delay elements for shifting the input signal to the next stage and operate at the same speed as the input signal.

The second stage multiplier 22-2 multiplies the input signal delayed by the delayer 23-1 with the filter coefficient selected by the multiplexer 21-2. This operation is repeatedly performed up to N stages.

The delay element and the tap coefficient control signal operate at N times the speed of x (n). This polyphase implementation can reduce the number of adders and multipliers required to 1 / N, compared to a typical direct form filter with N = 1.

Another design approach to reduce filter hardware complexity is the IFIR design approach.

3A to 3D show frequency spectrum characteristic diagrams of a low frequency filter using an IFIR design scheme.

3A shows the spectrum of the filter to be designed.

FIG. 3b is doubling the passband and stopband frequencies in FIG. 3a. Since the transition band of FIG. 3B is twice that of FIG. 3A, the transition band of FIG.

FIG. 3C is obtained by inserting 0 between the tap coefficients obtained in FIG. 3B, and it can be seen that there is an image at π.

Figure 3d shows the frequency characteristics of the image suppression filter, the image can be removed by passing through the image suppression filter, which has a very wide transition band compared to the passband can be ignored compared to the frequency characteristics shown in Figure 3b You can do this with just enough tabs.

When the filter having the spectrum of FIG. 3C is implemented in the polyphase N = 2 scheme, the coefficients C ₁ , C ₃ , C ₅ ,..., Of the odd index in FIG. 2 become 0. Using this, two filters can be implemented to share one resource as shown in FIG. 4.

4 is a structural diagram of an efficient filter using an interpolation scheme according to an embodiment of the present invention, in which QPSK spreading is performed, the input signal is oversampled four times, and the I / Q two-channel filter is implemented in polyphase 4. The case is implemented as an example.

When the digital filter shown in this figure performs band limitation on in-phase and quadrature channel signals, the band for two signals is added by adding only a multiplexer instead of using respective digital filters for in-phase and quadrature channel signals. Restrictions can be performed.

In the figure, C _{I, n} and C _{Q, N} are generated by doubling the spectrum of the I / Q channel as shown in FIG. 3B, with the number of filter taps as M '.

To help understand, first, the overall operation of the efficient filter using the interpolation technique according to the present invention will be described.

In FIG. 4, the I / Q channel input signal is alternately applied to the filter by the multiplexer 41 control of the I / Q input control signal and multiplied by the corresponding channel filter coefficient by the tap coefficient control signal. The delay element 47 at the output stage reflects the delay of one sample of the Q channel signal when the I / Q inputs are combined.

Then, by controlling the multiplexers 48 and 49 so that the I / Q output control signal alternates with 0 at the output of the filtered signal, the spectrum of the filter becomes as shown in FIG. 3C. In this way, the desired spectrum can be obtained by passing the output signal of FIG. 4 through the image suppression filter.

Now, the function of each component will be described in more detail.

The first multiplexer 41 receives the I channel signal and the Q channel signal and performs expansion and multiplexing on the two signals according to the I / Q input control signal. The I / Q multiplexing control signal changes at four times the speed of the input signal, repeating 0 and 1. Here, the I channel signal and the Q channel signal have been described as an example of the case of Quadrature Phase Shift Keying (QPSK) modulation, but need not necessarily be the I channel and the Q channel.

The second multiplexer 42-1 is a 4-1 multiplexer for selecting filter coefficients. The tap coefficient control signal is shifted at the same speed as the I / Q input control signal. Cycle through values

The first multiplier 43-1 multiplies the signal extended and multiplexed in the first multiplexer 41 by the tap coefficient signal selected by the second multiplexer 42-1. Since the signals output from the first multiplexer 41 are input in the order of the I, Q, I, and Q channel signals, the 0 and 2nd input signals are the I channel filter coefficients. Multiplied by and the first and third input signals are Q channel filter coefficients Is multiplied.

Four delay elements are connected in series in the tap delay unit 44-1. Each delay element operates at four times the speed of the input signal, and sequentially outputs the signal output from the first multiplexer 41. To the side. The subsequent tap retarders 44-2 to 44-N also perform the same operation as the tap retarder 44-1.

The multiplexers 42-2 to 42-N perform the same operation as the second multiplexer 42-1. That is, the filter coefficient is selected and output.

The multipliers 43-2 to 43-N of each stage are connected to the multiplexers 42-2 to 42-N of each stage to the signal output from the tap delayers 44-1 to 44- (N-1). Multiply by the selected tap coefficient signal.

The adder 45 adds all the outputs of the multipliers 43-2 to 43-N in each stage.

The first demultiplexer 46 separates the output signal from the adder 45 into I and Q channels according to the I / Q demultiplexing control signal. The I / Q demultiplexing control signal repeats the values 0 and 1 at four times the speed of the filter input signal, and outputs the data of the I channel to the 0 terminal and the Q channel to the 1 terminal. At this time, output signal of terminal 0 is y (I, 0), x, y (I, 1), x, y (I, 2), x,. (Where x is a meaningless signal) and the output signal of terminal 1 is y (Q, 0), x, y (Q, 1), x, y (Q, 2), x,. Becomes

Since the delay signal 47 oversamples the input signal from the demultiplexer 46 in the order of I, Q, I, and Q, the delay of the I channel signal is delayed by one sample, thereby timing the I / Q channel signal. ) Again.

The multiplexer 48 is a two-to-one multiplexer. '0' is connected to terminal 0, and the filtered I channel signal is connected to terminal 1. If the output control signal is 0, 0 connected to terminal 0 is output control. Signal equals 1, the result of the I channel's filter Is output. The output control signal repeats the values of 0 and 1 at four times the speed of the filter input signal, replacing them with '0' when the input signal value of the multiplexer 48 is 'x', thereby filtering the IFIR of the I channel. Control to get the generated signal.

The multiplexer 49 operates in the same manner as the operation of the multiplexer 48 except that the Q channel signal is connected to the first terminal to output an IFIR filtered signal of the Q channel.

The I and Q channel filter result signals output from the multiplexers 48 and 49 can be passed through the image suppression filter to obtain the desired filter effect.

According to the present invention as described above, by using the IFIR filter design method to process the coefficients of the other filter in the portion where one filter coefficient is 0 to combine the two filters into one to share resources, thereby reducing the complexity of the filter hardware It can be reduced to 1/2.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

When the present invention as described above is applied to a communication system such as CDMA and IMT-2000, etc., where a plurality of band-limited filters are required, resources can be shared to greatly reduce the number and complexity of components of the digital filter. And it is possible to reduce the size of the hardware.

Claims (4)

First multiplexing means for receiving a first signal and a second signal from the outside and selectively outputting one of the first and second signals according to a multiplexing control signal from the outside; First filtering means for multiplying and outputting a signal output from said first multiplexing means by a tap coefficient selected according to an external tap coefficient control signal; At least one second filtering means for delaying the signal output from the first multiplexing means for a predetermined period and then multiplying the selected tap coefficient according to the tap coefficient control signal; Addition means for summing signals output from the first and second filtering means; And Demultiplexing means for performing demultiplexing and ordering of signals output from said adding means in accordance with an output control signal from the outside Efficient filter using an interpolation technique, including, but sharing the resources by combining at least two filters into one by processing the coefficients of the other filter in the portion where the required coefficient is zero by using the interpolation technique. The method of claim 1, The first filtering means, Second multiplexing means for selectively outputting one of a plurality of tap coefficients in accordance with the tap coefficient control signal; And First multiplication means for multiplying and outputting a signal output from said first multiplexing means by a tap coefficient output from said second multiplexing means Efficient filter using an interpolation technique comprising a. The method according to claim 1 or 2, The at least one second filtering means, respectively, Delay means for delaying a signal output from said first multiplexing means; Third multiplexing means for selectively outputting one of a plurality of tap coefficients in accordance with the tap coefficient control signal; And Second multiplication means for multiplying and outputting a signal output from said delay means by a tap coefficient output from said third multiplexing means; Efficient filter using an interpolation technique comprising a. The method according to claim 1 or 2, The demultiplexing means, A demultiplexer for separating the signal output from the adding means into a third signal and a fourth signal according to a demultiplexing control signal from the outside; A delay unit for delaying the third signal; A first multiplexer for selectively outputting the third signal delayed by the delay unit according to an interpolation control signal from the outside; And A second multiplexer for selectively outputting a fourth signal according to the interpolation control signal Efficient filter using an interpolation technique comprising a.