KR100281143B1 - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can improve the reliability of the device by compensating for the difference between the diffusion speed of the acenic and boron, the gate insulating film on a semiconductor substrate defined as NMOS region and PMOS region Forming a; Forming a first gate pattern and a second gate pattern made of a barrier material interposed between two layers of undoped polysilicon having a grain boundary perpendicular to the gate insulating layer, and a barrier material interposed between the two layers of undoped polysilicon ; Doping N-conductive impurities into the NMOS region including the first gate pattern and doping P-conductive impurities into the PMOS region including the second gate pattern; A process of diffusing doped impurities in the first and second gate patterns through heat treatment to form a gate electrode of an NMOS and a gate electrode of a PMOS, and simultaneously forming source / drain impurity diffusion regions in the substrate on both sides of the gate electrode; Characterized in that comprises a.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for providing a more reliable semiconductor device by compensating for the difference in diffusion rates of the boron as an N conductive impurity and the boron as a P conductive impurity. It is about.

In general, a single poly gate structure requires a buried PMOS to increase the short channel effect, making it impossible to produce a microdevice having a gate length of 0.25 μm or less.

Therefore, a technique of implementing the gate structure as a double gate, poly, that is, P-poly in PMOS and N-poly in NMOS, has been proposed.

Hereinafter, a method of manufacturing a dual gate of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device of a semiconductor device according to the prior art.

As shown in FIG. 1A, the device isolation region 12 is partially formed in the semiconductor substrate 11 using a trench isolation process or a local oxidation process (LOCOS).

Thereafter, a P well region 13 and an N well region 14 are selectively formed in the semiconductor substrate 11 through an impurity ion implantation process.

At this time, although not shown in the figure, the N well region 14 is masked when implanting the impurity ions to form the P well region 13, and conversely, when the N well region 14 is formed, the P well region 13 is formed. This is masked.

As shown in FIG. 1B, the gate insulating film 15 is formed on the semiconductor substrate 11 on which the device isolation region 12 is formed.

The first undoped polysilicon 16 in which impurities are not doped is sequentially deposited on the gate insulating layer 15.

Thereafter, a barrier material layer 17 is formed on the first undoped polysilicon layer 16, and a second undoped polysilicon layer 18 is formed on the barrier material layer 17.

As shown in FIG. 1C, the second undoped polysilicon layer 18, the barrier material layer 17, the first undoped polysilicon layer 16, and the gate insulating layer 15 may be subjected to a photolithography process. ) Is selectively removed to form the first gate pattern 20 and the second gate pattern 21.

In this case, the first gate pattern 20 is used as the gate electrode of the NMOS transistor during the subsequent process, and the second gate pattern 21 is used as the gate electrode of the PMOS transistor.

As described above, after the gate patterns 20 and 21 are formed, a portion in which the second gate pattern 21 is formed is masked with the first photoresist 22, as shown in FIG. 1D.

An n-conductive impurity, for example, an (As) ion, is implanted into the P well region 13 including the exposed first gate pattern 20, and then thermally treated to form an N-conductive source / drain impurity region 23. 23a).

Subsequently, after removing the first photoresist 22, the portion where the first gate pattern 20 is formed is masked with the second photoresist 24, as shown in FIG. 1E.

P-conductive impurities such as boron (B or BF ₂ ) ions are implanted into the exposed second gate pattern 21 and the N well regions 14 on both sides thereof, and then heat-treated to form P-conductive source / drain. Impurity regions 25 and 25a are formed.

At this time, the first gate pattern 20 is doped with ionic ions, and the second gate pattern 21 is doped with boron ions.

Thereafter, heat treatment is performed to activate the first and second gate patterns 20 and 21. The heat treatment is performed for several tens of seconds at 1000 ° C. or more.

As such, as illustrated in FIG. 1F, diffusion of the boron doped in the first gate pattern 20 and the boron doped in the second gate pattern 21 results in N-type first gate electrode 20a. And the second gate electrode 21a of the P conductivity type is implemented.

However, the conventional semiconductor device manufacturing method as described above has the following problems.

When polysilicon is used as the gate electrode, the reliability of the device is degraded due to the difference in diffusion rates of boron and acenic due to heat treatment.

That is, since the diffusion rate of boron is significantly faster than that of the acenic, the phenomenon that boron penetrates toward the gate insulating layer occurs as the heat treatment time increases, which eventually changes the threshold voltage.

In view of this, if the heat treatment time is set short, the diffusion of the acenic on the NMOS side is not properly performed, causing a depletion phenomenon.

In addition, since the heat treatment process for forming the source and drain impurity diffusion regions in the NMOS region and the PMOS region is performed separately, the process becomes complicated.

Disclosure of Invention The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for manufacturing a semiconductor device which can improve the reliability of the device by compensating for the difference in diffusion speed between the arsenic and boron. .

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

Figure 3 is a C-V characteristic diagram showing the dispersion characteristics of the present invention compared to the prior art

Figure 4 is a graph showing the result of comparing the ion implantation according to the present invention

Explanation of symbols for main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: P well area 34: N well area

35 gate insulating film 36 first undoped polysilicon

37: Barrier Material 38: Second undoped polysilicon

40: first gate pattern 41: second gate pattern

40a: first gate electrode 41a: second gate electrode

The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a gate insulating film on a semiconductor substrate defined by the NMOS region and the PMOS region, the two layers of the grain boundary perpendicular to the gate insulating film Forming a first gate pattern and a second gate pattern made of a barrier material interposed between the undoped polysilicon and the undoped polysilicon of the two layers, and an N conductive impurity in the NMOS region including the first gate pattern. Doping the P-conductive impurities into the PMOS region including the second gate pattern and diffusing the doped impurities to the first and second gate patterns through heat treatment to form an NMOS gate electrode and a PMOS gate. A hole for forming source / drain impurity diffusion regions in a substrate on both sides of each gate electrode while forming an electrode And characterized by comprising comprises a.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

First, the present invention used the diffusion rate difference between the N-type and P-type impurities.

In other words, the N-type impurity has a faster diffusion rate through the grain boundary than the diffusion rate through the grain boundary, and the P-type impurity utilizes almost the same diffusion rate through the grain boundary and the diffusion rate through the grain boundary. will be.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

As shown in FIG. 2A, the device isolation region 32 is partially formed in the semiconductor substrate 31 using a trench isolation process or a local oxidation process (LOCOS).

Thereafter, a P well region 33 and an N well region 34 are selectively formed in the semiconductor substrate 31 through an impurity ion implantation process.

At this time, although not shown in the drawing, the N well region 34 is masked when implanting impurity ions to form the P well region 33, and conversely, when the N well region 34 is formed, the P well region 33 is formed. This is masked.

As shown in FIG. 2B, a gate insulating film 35 is formed on the semiconductor substrate 31 on which the device isolation region 32 is formed.

A first undoped polysilicon 36 in which impurities are not doped is deposited on the gate insulating layer 35.

At this time, the deposition conditions of the first undoped polysilicon 36 are as follows.

That is, the first undoped polysilicon 36 is deposited under the condition that the temperature of the substrate is 580 ° C or higher while flowing a gas containing silicon (for example, SiH ₄ , Si ₂ H _6, etc.).

At this time, the grain boundary of the first undoped polysilicon 36 has a vertical shape.

For reference, general polysilicon deposition, including the prior art, is deposited at a temperature of 580 ° C. or less, that is, a temperature range of 550 ° C. to 570 ° C., but the present invention uses a gas such as SiH ₄ and Si ₂ H ₆ at a high temperature of 580 ° C. Since it deposits while flowing, the grain boundary of the polysilicon to be deposited has a vertical structure.

Subsequently, a gas such as SiH ₄ , Si ₂ H _6, and the like may be temporarily blocked, and the first undoped polysilicon may be flowed by flowing a gas reactive to silicon such as N ₂ , O ₂ , and NH ₃ at the same temperature. A barrier material 37, for example, a silicon oxide film or a silicon nitride film, is deposited on 36.

Thereafter, as in forming the first undoped polysilicon 36, a gas containing silicon is flowed to deposit the second undoped polysilicon 38.

In this case, the grain boundaries of the second undoped polysilicon 38 are also vertical, and the first undoped polysilicon 36 and the second undoped polysilicon 38 are mismatched by the barrier material 37. It has a mismatched structure.

Subsequently, as illustrated in FIG. 2C, the second undoped polysilicon 38, the barrier material 37, the first undoped polysilicon 36, and the gate insulating layer 35 are selectively formed through a photolithography process. The first gate pattern 40 and the second gate pattern 41 are formed to be removed.

As shown in FIG. 2D, the forming portion (PMOS region) of the second gate pattern 41 is masked with the first photoresist 42. An N conductive impurity, eg, an As, is implanted into the exposed first gate pattern 40 forming portion (NMOS region).

Here, phosphorus (P) can also be applied in addition to the acenic.

As shown in FIG. 2E, after removing the first photoresist 42, the portion (NMOS region) where the first gate pattern 40 is formed is masked with the second photoresist 43.

P-conductive impurities such as boron (B) are ion-implanted into the exposed second gate pattern 41 forming portion (PMOS region).

As such, after ion implantation of the acenic and boron, respectively, heat treatment is performed, the doped boron doped in the first gate pattern 40 and the boron doped in the second gate pattern 41 are diffused. The pattern 40 and the second gate pattern 41 are activated and used as the first gate electrode 40a and the second gate electrode 41a, respectively.

At the same time, source / drain impurity diffusion regions 43 and 43a for NMOS transistors are formed in the P well regions 33 at both sides of the first gate electrode 40a, and the N well regions (at both sides of the second gate electrode 41a) are formed. 34, source / drain impurity diffusion regions 45 and 45a for the PMOS transistor are formed.

Here, the heat treatment for forming the source / drain impurity diffusion region is performed in an O ₂ atmosphere at a temperature of 600 to 800 ° C., and then heat-treated in an N ₂ atmosphere for diffusion of acenic and boron.

As described above, the acenic has a fast diffusion rate through the grain boundary, whereas the boron has a diffusion rate through the grain boundary and the diffusion rate through the interior of the grain is almost the same as compared to the acenic spread through the grain boundary. It has almost the same diffusion rate.

That is, by compensating the diffusion speed of the acenic so that the diffusion speed of the acenic and boron are the same, depletion of the NMOS region can be prevented, and the phenomenon that boron penetrates toward the gate insulating film 35 in the PMOS region. Can be prevented.

On the other hand, Figure 3 is a C-V characteristics showing the dispersion characteristics when using three kinds of polysilicon having a vertical structure of the general polysilicon, amorphous silicon, and the grain boundary of the present invention as a gate electrode.

As shown in FIG. 3, it can be seen that when the polysilicon of the present invention is used as compared with the case of using amorphous silicon or general polysilicon, the deflation of the NMOS region is improved to 10% or less.

In other words, when comparing the capacitance on the positive bias side, it is shown that the polysilicon of the present invention has a high capacitance when the grain boundary is perpendicular to that of amorphous silicon or general polysilicon.

4 is a graph showing the result of ion implantation according to the present invention in comparison with the prior art.

As shown in Figure 4, when comparing the penetration amount of boron in the vicinity of the depth of 1500Å, it can be seen that the penetration amount of boron is smaller than in the case of using the present invention.

As described above, the semiconductor device manufacturing method of the present invention has the following effects.

First, by compensating the diffusion rate of N-conducting impurities to be the same as the diffusion rate of P-conducting impurities, it is possible to reduce the depletion of the NMOS region under limited heat treatment conditions and to prevent excessive penetration of boron in the PMOS region. have.

Preventing the excessive penetration of boron in the PMOS region, in turn, prevents the change of the threshold voltage, thereby improving the reliability of the device.

Second, the heat treatment for source / drain impurity diffusion in the NMOS region and the PMOS region is simultaneously performed, thereby simplifying the process.

Claims (8)

Forming a gate insulating film on a semiconductor substrate defined by an MNOS region and a PMOS region; Forming a first gate pattern and a second gate pattern made of a barrier material interposed between two layers of undoped polysilicon having a grain boundary vertically formed on the gate insulating layer and the undoped polysilicon of the two layers ; Doping N-conductive impurities into the NMOS region including the first gate pattern and doping P-conductive impurities into the PMOS region including the second gate pattern; A process of diffusing doped impurities in the first and second gate patterns through heat treatment to form a gate electrode of an NMOS and a gate electrode of a PMOS, and simultaneously forming source / drain impurity diffusion regions in the substrate on both sides of the gate electrode; A semiconductor device manufacturing method comprising a. The process of claim 1, wherein the forming of the first and second gate patterns is performed. Depositing first undoped polysilicon at a high temperature such that grain boundaries are vertical on the gate insulating film; Forming a barrier material on the first undoped polysilicon; Forming a second undoped polysilicon on the barrier material under the same deposition conditions as the first undoped polysilicon; And selectively removing the second undoped polysilicon, barrier material, first undoped polysilicon, and gate insulating film so as to remain selectively on the substrate of the NMOS region and the PMOS region. Device manufacturing method. The method of claim 2, wherein the first and second undoped polysilicon are deposited under conditions in which the temperature of the substrate is 580 ° C. or higher while flowing SiH ₄ or Si ₂ H ₆ gas. . The method of claim 1, wherein the barrier material is a silicon nitride film or a silicon oxide film. The semiconductor device according to claim 4, wherein the silicon nitride film is deposited while flowing NH ₃ gas at the first and second undoped polysilicon deposition temperatures, and the silicon oxide film is deposited while flowing O ₂ gas. Manufacturing method. 2. The method of claim 1, wherein the two layers of polysilicon having vertical grain boundaries are mismatched by the barrier material. The method of claim 1, wherein the N-type conductive impurity is used ascein (As), or phosphorus (P), and the P conductive type impurity is to use boron (B), or fluorine (BF ₂ ). A semiconductor device manufacturing method characterized by. The method of claim 1, wherein the heat treatment is performed at a temperature of 600 ° C. to 700 ° C. in an O ₂ atmosphere to form the source / drain impurity diffusion region, and then diffuse the doped impurities into the first and second gate patterns. The semiconductor device manufacturing method characterized in that to carry out continuously in N ₂ atmosphere.