KR100278017B1 - Shift register circuit by using memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit, and more particularly, to a shift register circuit using a memory in order to delay input data by N periods regardless of the number of delay elements.

The present invention provides a first latch unit for outputting input data in synchronization with a reference clock signal, a counter for counting the reference clock signal to generate an address signal, and a gating combination of the reference clock signal and the delayed reference clock signal. A read / write enable signal generator for generating a read / write enable signal and storing or outputting output data of the first latch unit in an address region designated by the address signal in response to the read / write enable signal; And a second latch unit configured to output an output data of the memory in synchronization with the reference clock signal.

Description

Shift register circuit using memory {SHIFT REGISTER CIRCUIT BY USING MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of a shift register circuit, and more particularly, a circuit capable of implementing a multi-stage shift register circuit using a small number of programmable logic cells (PLCs) in a field programmable gate array (FPGA). It is about.

FIG. 1 illustrates a 4-bit shift register circuit diagram, and FIG. 2 shows an operation timing diagram of the shift register circuit having the configuration of FIG. Referring to FIG. 1, the operation of the 4-bit shift register circuit will be briefly described. The input data Din input to the D terminal of the first D-flop flop 10 is latched at the rising edge of the reference clock signal CK. This delays the output by one clock cycle. The output signal Q0 of the D-flip flop 10 is output as a Q1 signal delayed by one clock cycle again at the next D-flip flop 20, and the Q1 signal is the next reference clock signal CK at D-flip flop 30. Is latched at the rising edge and output as a Q2 signal delayed by one cycle. The Q2 signal is delayed by one more period from the D-flip flop 40 to the output data Dout, and as a result, the input data Din is delayed by four clock cycles.

The shift register circuit of the above-described configuration is widely used in many areas. However, in the general shift register circuit as described above, 10 flip-flops are needed to delay the input data by 10 cycles, and 100 flip-flops are required to delay the 100 cycles. In other words, N delay elements are required to delay the input data by N periods. However, in a device having a limited number of delay elements, such as an FPGA, a problem in that a desired multi-stage shift register circuit cannot be implemented due to the limitation of the number of delay elements. there was.

Accordingly, an object of the present invention is to provide a shift register circuit using a memory that can delay input data by N periods without being limited by the number of delay elements.

It is still another object of the present invention to provide a shift register circuit capable of designing a multi-stage shift register circuit using only a few programmable logic cells in a field programmable gate array (FPGA).

The shift register circuit according to the present invention for achieving the above object,

A first latch unit for outputting input data in synchronization with a reference clock signal;

A counter for counting the reference clock signal to generate an address signal;

A read / write enable signal generator configured to generate a read / write enable signal by gating a combination of the reference clock signal and the delayed reference clock signal;

A memory for storing or outputting output data of the first latch unit in an address area designated by the address signal in response to the read / write enable signal;

And a second latch unit configured to output the output data of the memory in synchronization with the reference clock signal.

1 is a typical 4-bit shift register circuit diagram.

2 is an operation timing diagram of a shift register circuit having the configuration of FIG.

3 is a shift register circuit diagram according to an embodiment of the present invention.

FIG. 4 is an operation timing diagram when the enable signal EN in FIG. 3 is active at the "high" level.

FIG. 5 is an operation timing diagram when the enable signal EN in FIG. 3 is deactivated to the "low" level. FIG.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the preferred embodiment of the present invention. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention.

FIG. 3 illustrates a shift register circuit diagram according to an exemplary embodiment of the present invention, and FIG. 4 illustrates an operation timing diagram when the enable signal EN of FIG. 3 is active at a "high" level. 5 shows an operation timing diagram when the enable signal EN in FIG. 3 is de-active to the "low" level, respectively.

First, referring to FIG. 3, a configuration of a shift register circuit according to an exemplary embodiment of the present invention will be described. The D-flip-flop 50 sets the input data Din of the reference clock signal CK in a section in which an enable (EN) signal is activated. Latch at rising edge and output through Q terminal. As such, the signal DI output through the Q terminal is input to the data input terminal DI of the memory 70. The counter 60 counts the reference clock signal CK in the period in which the enable signal EN is activated and outputs the generated address signal to the address terminal AD of the memory 70.

The data to be shifted is stored in the memory 70. Therefore, the D-flip-flop 80 latches and outputs the data D0 output from the memory 70 at the falling edge of the reference clock CK. On the other hand, the D-flip flop 90 compensates for the half-cycle phase difference caused by the D-flip flop 80 by latching the output data Dn of the D-flip flop 80 at the rising edge of the reference clock signal CK and outputting the output data Dout. .

On the other hand, the reference clock signal CK is delayed by the delay 100 by a predetermined period and then input to the NAND gate 110, and the NAND gate 110 is the delayed reference clock signal CK and the inverted reference clock signal. (CK) is output by combining NAND gating. The output signal of the NAND gate 110 is input to the oragate 120 and combined with the enable signal EN to be input to the read / write terminal of the memory 70. That is, the delay 100, the NAND gate 110, and the oragate 120 generate and output a read / write enable signal for storing input data in the memory 70 within a half period of the reference clock signal. Accordingly, the delay 100, the NAND gate 110, and the oragate 120 are defined as a read / write enable signal generator.

Hereinafter, an operation when the enable signal EN is activated or deactivated will be described in detail with reference to FIGS. 3 to 5.

First, when the enable signal EN is active at the "high" level as illustrated in FIG. 4, the data Din input to the D-flip-flop 50 is latched at the rising edge of the reference clock signal CK. The output signal DI delayed by one cycle is input to the DI terminal of the memory 70 by being output, and the counter 60 counts the reference clock signal CK to increase the address of the memory 70 by one. In the shift register circuit according to the embodiment of the present invention, when the number of times that the input data is to be shifted is N, the counter 60 is designed as a (N-2) binary counter.

On the other hand, the NAND gate 110 combines the reference clock signal CK delayed by the delay 100 and the inverted reference clock signal CK by NAND gating to generate an inverted pulse signal having a period equal to the delay time caused by the delay 100. It is entered as 120. In the ORA gate 120, the inverted pulse signal and the inverted enable signal EN are combined together to generate a read / write enable signal R / W having a timing as illustrated in FIG. 4.

Therefore, the output signal DI of the D-flip-flop 50 is stored in the memory 70 within a half period in which the reference clock signal CK is "low". On the other hand, when the reference clock signal CK is "high", the memory 70 is in a data read state, in which the data before the N-2 clock is output through the DO terminal. That is, the data stored in the memory 70 is output after N-2 clock cycles. Accordingly, when the reference clock signal CK reaches the falling edge, the output signal DO of the memory 70 is latched at the D-flip flop 80, and the output signal Dn latched as described above is again at the D-flip flop 90. By latch output at the rising edge of (CK), data Dout having a phase difference of half period from Dn is outputted.

Hereinafter, the shift register circuit operation when the enable signal EN is deactivated to the "low" level as shown in FIG. 5 will be described. First, the D-flip-flop 50 is transferred regardless of the input of the reference clock signal CK. Outputs data and maintains the previous address value of 60 degrees. In addition, the NAND gate 110 generates an inverted pulse signal having a period equal to the delay time of the delay 100 by combining NAND gating between the reference clock signal CK delayed by the delay 100 and the inverted reference clock signal CK. It is entered as 120. In the ORA gate 120, the inverted pulse signal and the inverted enable signal EN are combined or combined, so that the write enable signal does not occur in the period in which the enable signal EN is deactivated. Therefore, the output signal DI of the D-flip-flop 50 is not stored in the memory 70 during the half period when the reference clock signal CK is "low".

On the other hand, when the reference clock signal CK is " high, " the memory 70 is in a read state, and the output signal DO of the memory 70 outputs previous data because its address does not change. Therefore, when the reference clock signal CK is at the falling edge, the D-flip-flop is output at 80 degrees, and when the reference clock signal CK is at the rising edge, the D-flip flop is 90 degrees. .

Accordingly, the present invention can operate as the N-shift shift register circuit by repeatedly performing the above-described operation every cycle of the reference clock signal.

As described above, since the desired shift register circuit can be designed using a counter, a memory, and a small number of delay elements, the present invention can be efficiently utilized for a circuit for optimizing an FPGA or other circuits. In particular, circuits that can utilize PLCs in FPGAs as small-capacity memory can benefit even more.

Claims (5)

In the shift register circuit, A first latch unit for outputting input data in synchronization with a reference clock signal; A counter for counting the reference clock signal to generate an address signal; A read / write enable signal generator configured to generate a read / write enable signal by gating a combination of the reference clock signal and the delayed reference clock signal; A memory for storing or outputting output data of the first latch unit in an address area designated by the address signal in response to the read / write enable signal; And a second latch unit configured to output the output data of the memory in synchronization with the reference clock signal. The shift register circuit according to claim 1, wherein the read / write enable signal generator generates a write enable signal that is output in synchronization with a falling edge of the reference clock signal. The method of claim 2, wherein the read / write enable signal generator, A delay for delaying the reference clock signal; And a NAND gate configured to generate a write enable signal during a half period of the reference clock signal by gating the delayed output reference clock signal and the inverted reference clock signal. The method of claim 1, wherein the second latch portion, A first flip-flop for latching output data of the memory at the falling edge of the reference clock signal; And a second flip flop for latching the output data of the first flip flop at the rising edge of the reference clock signal. The shift register according to any one of claims 1 to 4, wherein when the number of times to shift the input data is N, the counter is a (N-2) binary counter. Circuit.

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