KR100276603B1 - Cell drive circuit of field emission indicator - Google Patents

Abstract

The present invention divides the cathode into rows and columns, and installs a plurality of current sources for supplying a constant current to one pixel, and maximizes the gradation process by controlling each current source. It is for providing a driving circuit.

To this end, the present invention, in the field emission indicator having a plurality of gates and cathodes for one pixel, a gate driving element for selectively applying a constant voltage to the plurality of gates controlled by a control signal, and the plurality of cathodes On the side, a scan driver which scans the plurality of gates by a periodically applied scan signal and a data driver which adjusts the current of each cathode by a data voltage provided between the scan driver and ground are provided. The screen gradation process is selectively performed by using a plurality of current sources for the pixels, and the screen gradation process is not only easy, but a constant current is supplied to the cathode regardless of the voltage change applied to the cathode so that the voltage is changed in the floating state of the cathode. Current change can be eliminated.

Description

Cell drive circuit of field emission indicator

The present invention relates to a cell driving circuit of a field emission indicator. More particularly, the present invention relates to a cell driving circuit capable of maximizing screen gray scale processing by using a low voltage device instead of a high voltage device and using a plurality of current sources for one pixel. will be.

In general, a field emission display is an example of a display that converts various electrical information generated from various devices into visual information and transmits it to humans, and a field emission display is used. The basic structure of the device is typically an emitter 11 connected to the emitter electrode 10, as shown in FIG. 1, and a gate 12 provided with a constant distance on top of the emitter 11. ) And an anode 13 provided at a predetermined interval on the top of the gate 12 with the fluorescent film 14 coated on the rear surface (ie, the surface facing the gate 12).

Here, the emitter 11 is also called a tip, and the team is sharply shaped and has a radius of about 400 kW or less for emitting electrons by the driving power source.

A hole is formed in the gate 12, and the upper portion of the emitter 11 faces the hole.

In addition, the anode 13 plays a role of attracting electrons emitted from the emitter 11 and has transparency to transmit light by the fluorescent film 14.

Referring to the operation of the general field emission device configured as described above are as follows.

When the driving power is applied after the emitter 11 is grounded and the gate 12 adjacent thereto is positively biased, a strong electric field is generated at the tip of the cold cathode, whereby the electrons are quantum-mechanical. It is emitted from the emitter 11 by the phosphorous tunneling effect.

The emitted electrons are accelerated while passing through the gator 12 to move the vacuum state and collide with the high pixel energy on the screen of the positive electrode plate fluorescent film 14 coated on the transparent electrode to emit light. At this time, since almost no electrons are absorbed by the gate 12, high efficiency is achieved, and almost all electrons reach the screen coated with the fluorescent film 14.

When realizing color display in a field emission indicator employing such a field emission element. Colors are displayed because the pixels of RGB are emitted at the same time.

On the other hand, the color and brightness of light are adjusted by changing the density of emitted electrons reaching the fluorescent film 14 by the gate voltage.

On the other hand, there is a method of driving a sal in the conventional field emission indicator as described above is a method in which the overcurrent blocking circuit is configured by using a fusible link (that is, the method described in US Patent No. 5,210,472).

The cell driving circuit of the field emission indicator described in US Patent No. 5,210,472 is as follows.

FIG. 2 shows an embodiment of the cell driving circuit of the field emission indicator described in US Pat. No. 5,210,472, in which one pixel turns one or both of the FETs Q _C , Q _R connected in series. As it is turned off, it is turned off (i.e., non-emitted), and at least one of the plurality of FETs is non-conductive (i.e., gate voltage V _GS drops below the threshold level V _{T of the device} ). At the instant of the excursion, the voltage potential between the base and the grid is configured such that the electrons are emitted from the emitter 22A, 22B, 22C team corresponding to the pixel above the emission threshold voltage.

Here, the base electrode 23 is insulated from the grid 21, and in order to increase the field emission, the base electrode 23 applies a ground potential through a pair of series-connected field effect transistors Q _C and Q _R. It is connected to the pulldown node that it maintains.

The transistor Q _C is turned on / off by the column line signal S _C while the transistor Q _R is turned on / off by the low line signal S _R. Standard logic signal voltages for CMOS, NMOS, TTL, and other integrated circuits are approximately 5 [V] or less, and are used for column and row line signals.

When any one of the plurality of field effect transistors Q _C and Q _R is non-conductive, that is, when the gate voltage V _GS drops below the threshold voltage V _T of the device, the voltage potential between the base and the grid Above is the emission threshold voltage, electrons are emitted from the emitter tip of that pixel.

FIG. 3 is a view showing another embodiment of the cell driving circuit of the field emission indicator described in US Patent No. 5,210,472. The difference from the embodiment of FIG. 2 is that the base electrode 23 is thrashed. Connected to the grid 21 via a current limiting N-channel field effect transistor Q _L with a hold voltage V _T. Next, the drain and gate of the transistor Q _L are directly connected to the grid 21. Is connected.

2 and 3, a soluble link FL is provided in series in a loose current path from the base electrode 32 to ground via transistors Q _C and Q _R.

The fusible link FL is broken during testing if a short between any base and emitter in the emitter group occurs. Thus, the shorted group is separated from the rest of the array to improve yield to minimize array power loss.

2 and 3, the contrast (e.g., change in pixel illuminance) of the display being operated is obtained by varying the duty cycle. Here, the duty cycle refers to the period during which the emitters in the pixel, for example, emit substantially (ie% / frame).

In addition, luminance control is achieved by varying the emitter current by varying the gate voltage of any or all of the plurality of transistors Q _C , Q _R.

However, according to the cell driving circuit of the conventional field emission indicator as described above, the overall circuit configuration is very complicated because the overcurrent blocking circuit must be configured so that a value above a certain current does not flow using the fusible link. In addition, there is no method of maximizing screen gray scale processing and emitting electrons uniformly to the emitter.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and installs a plurality of current sources for supplying a constant current to one pixel while driving the cathode portion into rows and columns, and controlling the screen by controlling each current source. It is an object of the present invention to provide a cell driving circuit of a field emission indicator to maximize gradation processing.

According to a preferred embodiment of the present invention to achieve the above object, in a field emission indicator having a plurality of gates and cathodes for one pixel, a predetermined voltage is selectively applied to the plurality of gates controlled by a control signal. A gate driver for scanning the gate, a scan driver for scanning the plurality of gates by a scan signal periodically applied to the plurality of cathodes, and a data voltage provided between the scan driver and the ground, A cell drive circuit is provided with a data driver for adjusting current.

1 is a diagram for explaining the basic structure of a general field emission device.

2 shows an example of a cell driving circuit of a general field emission indicator.

3 shows another example of a cell driving circuit of a general field emission indicator.

4 illustrates a cell driving circuit of a field emission indicator according to an embodiment of the present invention.

FIG. 5 is a view showing in more detail the scan driver and data driver shown in FIG.

FIG. 6 is a diagram illustrating an example of a scan signal applied to the scan driver shown in FIG.

FIG. 7 is a signal waveform diagram used to explain a change state of a data voltage and a current applied to the data driver shown in FIG.

* Explanation of symbols for main parts of the drawings

10: emitter electrode 11, 22A, 22B, 22C: emitter

12, 30A, 30B, 30C: Gate 13: Anode

14 fluorescent film 23 base electrode

FL: Availability Links 32A, 32B, 32C: Cathode

34: scan driver 36: data driver

38: gate driving element

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The cell driving circuit of the field emission indicator according to the embodiment of the present invention is arranged so as to face the bottom surface of the anode 13 through the holes of the gates 30A, 30B, 30C, and 30D, as shown in FIG. A scan driver 34 which scans the gates 30A, 30B, 30C, and 30D by a scan signal Vscan periodically installed between the cathodes 32A, 32B, 32C, and 32D and ground, and the scan A data driver 36 is provided between the driver 34 and the ground to adjust the current of each of the cathodes 32A, 32B, 32C, and 32D based on the input data voltage Vdata. 13 and the plurality of gates 30A, 30B, 30C, and 30D formed on the lower portion at a predetermined interval are connected in parallel to each other so that a constant voltage Vgate is applied according to the turn-on / turn-off of the gate driving element 38. do.

Here, the scan driver 34 includes a plurality of low voltage devices 34a, 34b, 34c, 34d disposed between the cathodes 32A, 32B, 32C, 32D and ground; for example, 40 [V] or less. Preferably, the plurality of low voltage elements 34a, 34b, 34c, and 34d are formed of MOS transistors (e.g., NMOS transistors).

In addition, the gates of the respective NMOS transistors are all connected by one line to receive the periodic scan signal Vscan (see FIG. 5) provided from an external controller (not shown), and the drains of the respective cathodes 32A and 32B. , 32C, 32D).

The data driver 36 outputs an external controller (not shown) and sets a plurality of voltages according to data voltages Vdata1, Vdata2, Vdata3, and Vdata4 input through a data bus (not shown). Connected to the output elements 36a, 36b, 36c, 36d, output terminals of the plurality of voltage output elements 36a, 36b, 36c, 36d, and one side of the plurality of low voltage elements 34a, 34b, 34c, 34d, respectively. And a plurality of driving elements mb1, mb2, mb3 and mb4 driven by signals from corresponding voltage output elements and the plurality of driving elements mb1, mb2, mb3 and mb4, respectively, and the ground And a plurality of current limiters R1, R2, R3, and R4 having mutually different resistance values for limiting the amount of current flowing through the 32A, 32B, 32C, and 32C.

The plurality of voltage output devices 36a, 36b, 36c, and 36d may be formed of an OP amplifier having a negative feedback characteristic. Preferably, the non-inverting terminal (+) of the OP amplifier includes corresponding data voltages Vdata1, Vdata2, and Vdata3. , Vdata4) is input and the inverting terminal (-) is connected between the corresponding driving element (any one of mb1, mb2, mb3, mb4) and the resistors (any one of R1, R2, R3, R4).

In addition, the plurality of driving elements mb1, mb2, mb3, and mb4 are formed of MOS transistors (for example, NMOS transistors), and the gates of the MOS transistors are corresponding voltage output elements 36a, 36b, 36c, and 36d. Is connected to an output terminal of any one of the terminals, and the other sides are connected between the corresponding low voltage elements 34a, 34b, 34c, and 34d, respectively, and the resistors (any one of R1, R2, R3, and R4).

In addition, the gate driving element 38 includes a single MOS transistor (for example, an NMOS transistor), and generates a predetermined voltage Vgate according to biasing of a gate signal (Vgate signal) capable of turning on one frame. The gates 30A, 30B, 30C, and 30D.

In the embodiment of the present invention, the gate driving element 38 is configured as a single MOS transistor, but may be implemented by using a plurality of NMOS and PMOS transistors as necessary.

In addition, in the exemplary embodiment of the present invention, the number of current sources per pixel is limited to four, but the number of the current sources can be added or decreased as necessary. That is, the OP amplifiers 36a, 36b, constituting the MOS transistors 34a, 34b, 34c, 34d and the data driver 36 constituting the scan driver 34 at the rear end of the cathode while reducing the number of cathodes. It is sufficient to add or subtract 36c, 36d, the number of driving elements mb1, mb2, mb3, mb4 and resistors R1, R2, R3, R4.

That is, the scan driver 34 shown in FIG. 4 shows a part of any one of a plurality of gate lines provided on the panel 1, and the overall configuration thereof is as shown in FIG.

In addition, according to an exemplary embodiment of the present invention, the data driver 36 may be installed to be connected to the scan driver 34 outside the panel 1 as shown in FIG. 5.

Next, the operation of the cell driving circuit of the field emission indicator according to the embodiment of the present invention configured as described above is as follows.

First, as a gate signal (Vgate signal) is biased to the gate of the gate type device 38, a fixed voltage of a predetermined value is formed at each gate 30A, 30B, 30C, and 30D through the gate driving device 38. (Vgate) is applied.

Subsequently, each of the MOS transistors 34a, 34b, 34c, and 34d constituting the scan driver 34 on the cathode 32A, 32B, 32C, and 32D side is periodically scanned from an external control unit (not shown). It is turned on at Vscan to scan the gates 32A, 32B, 32C, and 32D, and the periodically input scan signal Vscan is Vscan1, Vscan2, Vscan3, as shown in FIG. It is developed in a sequential direction.

In addition, the data voltages Vdata1, Vdata2, Vdata3, and Vdata4 output from the controller (not shown) may correspond to the corresponding op amps 36a, 36b, 36c, and 36d of the data driver 36 through a data bus (not shown). Each of the op amps 36a, 36b, 36c, and 36d is provided with a non-inverting terminal (+), and the voltage value fed back to the inverting terminal (-) and the data voltage input to the current non-inverting terminal (+). Compared to each other, a constant voltage is set.

Accordingly, the corresponding driving elements mb1, mb2, mb3, and mb4 are turned on in accordance with the setting values of the respective op amps 36a, 36b, 36c, and 36d, and thus the turned-on driving elements mb1, mb2, A strong electric field is generated at the tip of the cathode connected to any one of mb3, mb4, and electrons are emitted from the cathode by the strong electric field, and the emitted electrons are applied to the gates 30A, 30B, 30C, and 30D. As it passes through, it accelerates further and strikes the pixel strongly and emits light.

Here, the amount of electrons input from the pixel depends on the data voltages Vdata1, Vdata2, Vdata3, and Vdata4 and the resistors R1, R2, R3, and R4 provided by the controller (not shown).

For example, the initially input data voltages Vdata1, Vdata2, Vdata3, and Vdata4 are set to signals as exemplarily shown in FIG. 7, and the resistances R1, R2, R3, and R4 are mutually different. When the resistance value is set as “R1> R2> R3> R4”, that is, when “Vdata1 = 0, Vdata2 = 0, Vdata3 = 0, Vdata4 = 0”, all the driving elements mb1, mb2, mb3, and mb4 are all present. When turned off, the current values applied to the cathodes 30A, 30B, 30C, and 30D are virtually eliminated, resulting in no electron emission.

In the case of “Vdata1 = 1, Vdata2 = 0, Vdata3 = 0, Vdata4 = 0”, only the driving element mb1 is turned on to form a current path between the cathode 32A and ground, which is caused by the cathode 32A. Since only electron emission occurs, it can be seen that the amount of current at this time is larger than the case of “Vdata1 = 0, Vdata2 = 0, Vdata3 = 0, Vdata4 = 0”.

On the other hand, in the case of “Vdata1 = 1, Vdata2 = 1, Vdata3 = 0, Vdata4 = 0”, only the driving elements mb1 and mb2 are turned on to form the current path between the cathodes 32A and 32B and ground, so that the cathode ( Since electron emission by 32A and 32B) occurs, it can be seen that the residual amount at this time is larger than the case of “Vdata1 = 1, Vdata2 = 0, Vdata3 = 0, Vdata4 = 0”.

In other cases, as described above, similarly, a current path between the cathode and the ground is formed, and electron emission by the cathode is performed.

According to the present invention as described above, by performing the screen gradation process selectively using a plurality of current sources for one pixel, not only the screen gradation process is easy, but also a constant current is applied to the cathode regardless of the voltage change applied to the cathode. By supplying it, it is possible to eliminate the current change caused by the voltage change in the floating state of the cathode.

In addition, this invention is not limited only to embodiment mentioned above, It can implement by modifying and modifying within the range which does not deviate from the summary of this invention.

Claims (13)

A field emission indicator having a plurality of gates and cathodes for one pixel, comprising: a gate driving element for selectively applying a predetermined voltage to the plurality of gates by a control signal, and periodically applied to the plurality of cathodes; And a scan driver for scanning the plurality of gates by a scan signal, and a data driver for adjusting the current of each cathode by a data voltage provided between the scan driver and ground. . The cell driving circuit of a field emission indicator according to claim 1, wherein said gate driving element is composed of a single MOS transistor. 3. The cell driving circuit of claim 2, wherein the single MOS transistor is an NMOS transistor. The cell driving circuit of claim 1, wherein the scan driver comprises a plurality of geovoltage devices simultaneously controlled by the scan signal. 5. The cell drive circuit according to claim 4, wherein the plurality of low voltage elements are each composed of MOS transistors. 6. The cell drive circuit according to claim 5, wherein the plurality of MOS transistors are NMOS transistors. The data driver of claim 1, wherein the data driver is connected to a plurality of voltage output elements for setting a constant voltage according to an external data voltage, an output terminal of the plurality of voltage output elements, and one side of the plurality of low voltage elements, respectively. An electric field comprising a plurality of drive elements driven by signals from a voltage output element, and a plurality of current limiters respectively provided between the plurality of drive elements and ground to limit the amount of current flowing through the plurality of cathodes Cell drive circuit of the emission indicator. 8. The cell drive circuit according to claim 7, wherein each of the plurality of voltage output elements is constituted by an OP amplifier. The cell driving circuit of claim 8, wherein the plurality of OP amplifiers have negative feedback characteristics. 8. The cell driving circuit of claim 7, wherein the plurality of driving elements are each composed of MOS transistors. 12. The cell driving circuit of claim 10, wherein the plurality of MOS transistors are NMOS transistors. 8. The cell driving circuit of claim 7, wherein the plurality of current limiters are each composed of a resistor. 13. The cell driving circuit of claim 12, wherein the resistance values of the plurality of resistors are differential from each other.

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