KR100275103B1 - Static memory cell - Google Patents

Abstract

PURPOSE: A memory cell improved is provided to reduce the size of a chip and the power consumption by permanently storing a large quantity of data in a readable and erasable cell. CONSTITUTION: A switching transistor(M20) performs a switching in a memory cell. A data recording bit line(26) records data to a cell using a readable and erasable sensing circuit(46). A data reading bit line(28) reads the data stored in the memory cell. A data erasing bit line(32) erases the data stored in the memory cell. An electronic element(36) stores data in the form of electromagnetism. A data reading element(34) reads the data stored in the electronic element(36). An output current voltage bit line(35) connects an output value to the readable and erasable sensing circuit(46).

Description

Improved write, read and erasable static memory cells

Figure 1a is a cross-sectional view illustrating a memory cell structure used in a conventional erasable static read-write memory,

Figure 1b is a circuit diagram of Figure 1,

Figure 2a shows a static record according to the prior art based on NMOS technology, a perspective view of the read memory cell,

Figure 2b shows a static write in accordance with the prior art based on CMOS technology, a perspective view of the read memory cell,

Figure 3a is a perspective view of one transistor static write, read and erase (SRAM) memory according to the first and second embodiments of the present invention,

3b is a perspective view of one transistor read only memory cell (ROM) based on BJT technology according to a third embodiment of the present invention,

3bb is a perspective view of one transistor read only memory cell based on MOS technology according to the present invention,

4a and 4b are perspective views for explaining voltage and current changes in the terminal according to the present invention,

FIG. 5 shows voltage transfer characteristics of transistor M20 operating in an active mode in a data read cycle according to the first embodiment of the present invention; FIG.

Figure 6 is a perspective view of one transistor static write, read and erase memory cell designed to store more than one bit of data at the same time in accordance with the present invention;

7 is a perspective view showing an input of an emitter of a memory cell according to the present invention,

FIG. 8 is a perspective view showing a 256 × 8 memory cell according to the present invention,

FIG. 9 is a perspective view showing a 256 × 8 memory cell and program 1 and program 2 according to a second embodiment of the present invention;

FIG. 10 is a truth table showing the state of the emitter according to the present invention,

FIG. 11 is a perspective view illustrating a circuit based on MOS technology according to a third embodiment of the present invention; FIG.

DESCRIPTION OF REFERENCE NUMERALS

26: data write line 28: data read line

32: Data erase line 34: Data read element

35: data line 36: electromagnetic element

46: write, read, and erase detection circuit

The present invention relates to an improved apparatus and method for storing data in a computer and other digital systems, and more particularly to a system and method for storing one bit of data in the first embodiment and storing one or more bits of data in the second and third embodiments. Read and erase memory cells for performing the same. In the third embodiment, the present invention can maintain data stored in a memory cell even when power to a computer or a digital system is turned off.

In the prior art, there are several types of static write and read (SRAM) data storage memory cells. In the prior art used in a NOR cell array, a circuit including two gates and capacitors shown in Figs. 1a and 1b is used. For several years, the data was stored in the first gate by isolating the gate with silicon dioxide so that the data could be stored in the isolated capacitor. Since ultraviolet light slightly conducts the silicon dioxide insulator, data is removed by exposing the cell to strong ultraviolet (UV) light to erase the data stored in the cell. This ultraviolet exposure removes the charge stored in the transistor.

Another type of prior art is a static write and read memory cell using both NMOS and CMOS technologies as shown in Figs. 2a and 2b.

Various implementations of the prior art exist for SRAM memory cells that store data in digital systems. However, in all of these prior art embodiments, there is a need to reduce the number of components with one memory cell rather than to easily form many memory cells per unit area of the integrated circuit memory chip. Moreover, it is necessary to increase the amount of data that each memory cell can simultaneously hold. Every existing memory cell, whether static or dynamic, stores one bit of data per memory cell at a time.

It is a first object of the present invention to provide an improved method for storing one bit of data in a memory cell device with reduced number of components or elements and one transistor static write, read and erase memory cells.

It is another object of the present invention to provide an improved memory cell device and method for storing more than one bit of data used for computers and other digital systems.

It is another object of the present invention to provide an improved memory cell and method for storing a large amount of binary data used as a RAM for a built-in main memory of a computer and other digital systems.

It is another object of the present invention to provide an improved memory cell device and method for storing a large amount of data, which is also used as a ROM for a built-in main memory of a computer and other digital systems.

It is a further object of the present invention to provide a method and apparatus which is inherent in an array of the same memory cells in a memory cartridge for recording video, audio and computer data so that the recording and playback of the data can be carried out without a driving component, And to provide an improved apparatus and method for a static memory cell made by a device.

It is yet another object of the present invention to provide an improved apparatus and method for a memory cell that can be embedded in an array of identical memory cells on a memory card for recording video, audio and computer data.

It is another object of the present invention to permanently store large amounts of data in a form of write, read and erase, such as on an internal main memory for a computer and other digital systems, to provide data storage capacity such as magnetic disks, magnetic tape, and CD- And to provide an improved apparatus and method that can significantly reduce the power used to operate relative to a peripheral memory system.

Hereinafter, the present invention will be described in detail with reference to the accompanying FIGS. 3 to 11.

Referring to FIG. 3a, a first embodiment of the present invention for a single static write, read and erase memory cell is described. The multi-emitter transistor M20 is switched by a row address select line 24 that is controlled and activated by the decoder circuitry 44. [ The transistor M20 is set to 1 + 0 + 0 = 1, 0 + 1 + 0, and 1 + 0 + 1 under the condition that only one emitter has a high input at a time during each functional cycle such as a write cycle, a data read cycle, 54, and 56 as an input having an OR function of 1 (= 1) and 0 + 0 + 1 = 1, where all other emitter inputs that are not included in the functional cycle are low 1 ow) input, or the signal input lines are disconnected from the signal supply in the write, read and erase detection circuitry 46 of FIG. 3a. Assuming that the emitter 52 is used for data writing and the emitter 54 is used for data reading and the emitter 56 is used for data erasing, the truth table shown in FIG. Shows the emitter input for each data function cycle.

[Table 1] Emitter input of the memory cell according to the present invention

At any one time, only one of the three functions is allowed at a time, and two or three functions can not be simultaneously implemented by the write, read and erase circuitry 46.

The data read line 28 and the data erase line 32 are inactivated or disconnected in the write, read and erase sense circuit 46 during the data write cycle while the data write line 26 is in the write, And is activated by the sensing circuit 46. A predetermined amount of data write voltage is applied to the data write line 26 and a corresponding data write current is caused to flow through the data write line 26 and is applied to the data write line 26 in a given direction shown in Figs. 3a, 4a and 4b Passes through the electromagnetic element 36 and derives an amount of electromagnetic that provides the corresponding electromagnetic field 38 representing one bit of data.

A data write current flows through the data write line 26 connected to the data write-input emitter terminal 52 and is applied to the data write line 52 by the write, The voltage V ₁ acts as the input of the data write input emitter terminal 52 which provides the output voltage V01. Thus, a corresponding output current for the data write current I ₁ provided at the data write input emitter terminal 52 is generated at the collector terminal. The voltage VO2 at the output and the collector current through the data line 35 are measured by the write, read and erase sense circuit 46 to examine the appropriate connections and functions of the data write circuit loop and the data write cycle, respectively .

As will be described in detail, when the voltage (V ₂₎ across the data reading element 34 to form a transistor (M20) to the conductor, an electromagnetic for generating an electromagnetic field (38) has to be suitable for a predetermined amount. The predetermined amount of electromagnetic is represented by a high (1) bit, and the other quantities are represented by a low (0) bit.

To read the data stored in the memory cell, the data read line 28 has a predetermined read voltage applied by the write, read and erase sense circuit 46 of FIG. 3a. The read voltage generates the corresponding read current flowing along the data read line and the terminal of the data read element 34 shown in Figures 4a and 4b. When the data read current I ₂ or I ₃ flows through its terminal, the data read element 34 is electrically connected to the semiconductor element 38 which changes the voltage V ₂ across its terminal proportional to the field 38 Hx or Hy. It is formed of Indium Antimonide.

The most general equation used to express the relationship between the voltage (V ₂ ) across the data read element 34 and the field Hx 38 is to be. here,

V ₂ = voltage across data read element 34 shown in Figure 4a

K = indium antimony material, constant

Hx = the electromagnetic field 38 from the electrostatic element 36 shown in Figure 3a)

I ₂ = data read current passing through element 34 shown in FIG.

S = width of data read element 34 shown in Figure 4a

Since S, K, and I ₂ are constants, the voltage (V ₂ ) across data read element 34 is directly proportional to field Hx 38. On the other hand, the voltage (V ₂ ) applied to the data reading element 34 is proportional to the magnetic field corresponding to the field Hx. In turn, the amount of magnetization is proportional to the bit being one of the high (1) or low (1) (0) stored in the memory cell.

Voltage (V ₂₎ applied to the data reading device 34 operates as a dependent input voltage to be input to a data read input emitter terminal 54. Referring to FIG. 5, an emitter terminal 54 dependent voltage (V ₂ = V _in) to a low (1ow) or only when sufficient to conduct a transistor (M20), V _cc, and substantially the same VO2 = VOL in The output voltage, the supply voltage at the collector terminal, is implemented in the output stage, providing a low (0) bit. As V ₂ = V increases, the input emitter current (IE) increases while increasing the collector current (IC). In turn, the output voltage VO2 increases to a saturation current VO2 = VOH = VCE (saturation). This represents a high (1) bit. However, depending on the type of the transistor used in the present invention, the VCE (saturation) becomes negative (-), and as shown in FIG. 5, the logarithmic law in which the negative limit gradually appears as the minimum value, Direction.

VOH and VOL are measured by the column write, read and erase sense circuitry 46 to determine the stored bits. On the other hand, where VOH = VCE (saturation) is a high (1) bit because the high output voltage = VOH, the low 1OW output voltage = VOL, VOH = VCE (saturation), and VOL = , And VOL = VCC represents a low (1) (0) bit. The output voltages for the high (1) and low (0) bits may be reversed.

Alternatively, when the current I ₂ flows to its terminal as shown in FIG. 4b, the data reading element 34 is connected to the ferroelectric element 31, which changes the resistance to its own terminal, Nickel alloy. The general formula used to express the relationship between the resistance and the field Hy (38) is , Where the response of DELTA R to Hy can be linearized by an external bias field. According to Ohm's law, V ₃ = I ₃ R ₃ and I ₃ is a constant in a given design and situation, so the voltage V ₃ across the data reading elements shown in FIGS. 3a and 4b is It is proportional to the resistance (R ₃ ). The resistance R ₃ is proportional to the electromagnetic field Hy 38 as shown in Figs. 3a and 4b. The electromagnetic field Hy 38 is proportional to the type of data bits stored in the electromagnetic in the magnetic or electronic device 36 in Figure 3a or 1 (high) or 0 (low).

On the other hand, a data read input emitter on the emitter terminal 54 for a given dependent input voltage (V ₃ = V _in), and a corresponding output voltage (V02), see FIG. 5 recording as described in the previous paragraph, the read and And is implemented at the output stage of the erase memory cell.

When a data read current (I ₃₎ flows through his terminal the resistance change (ΔR) and the electromagnetic field 38, another design, the data reading device 34, such as using a combined magnetic line type that a linear relationship between the It is also used for. Moreover, since a slightly different configuration and size are applied to the used indium antimony element 34 and the iron-nickel alloy element 34, other equations representing the relationship between the voltages V ₂ and V ₃ and the electromagnetic system 38 Is used.

To erase the data stored in the memory cell, all other data lines are deactivated using the write, read and erase sense circuitry 46, while the data erase line 32 is in the write, And is activated by applying a suitable voltage using the erase detection circuit 46. [ The corresponding current flows to the data erase line 32 and passes along the electromagnetic element 36 in a direction opposite to that followed by the data read current in the data read line 26. [ The element demagnetization processing of the electromagnetic element 36 is performed so that data stored in the electromagnetic or magnetic element 36 by electronization or magnetization is removed. Before erasing the data stored in the memory cell, the data read cycle is initialized to determine the type of bit stored in the cell.

Voltage V ₂ = V _in is the with respect to the ground reference voltage applied to the collector voltage (Vcc) and the base terminal 37 is at the collector terminal 35 of the transistor (M20) transistor (M20) to conduction in the active region It should be sufficient to do. Furthermore, the emitter, collector, and base resistors required for transistor M20 to merge into the memory cell circuit to produce the desired result for a particular 1-bit storage memory cell are shown in Figures 3 and 8, Circuit 46 and decoder circuit 44, respectively. Since the emitter, collector, and base resistors are not part of one memory cell and are shared by all memory cells in the selected low for all memory cells and base resistors in the column for the emitter and collector resistors, Arrangement is necessary and convenient. On the other hand, the size and area of each memory cell occupied by the integrated circuit chip is greatly reduced by this shared design.

Eighth degree decoder circuit 44 prior to each cell transistor (M20), the selected memory cell row every row line that connects to the base of the ground voltage and by another preferably maintained below the ground reference voltage (V ₂ = V _in ) is applied to the emitter terminal 54 shown in FIG. 3a, the transistor base terminal 37 is activated by having the amount of ground reference voltage required for transistor M20 to conduct. The description of the base terminal 37 of the switching transistor M20 is for clarifying the form of the transistor used in the present invention. Other transistor configurations are used in other operating steps to provide the same switching stage result.

The voltage at the data input emitter terminal 54 according to the first embodiment of the present invention (V _in) is the two voltages, that is, the data read bit line voltage (V _R) applied to 28 shown in the 3a Fig. And the voltage (V ₂ or V ₃ ) across the data read element 34 shown in Figure 3a, the voltage V _R being applied to the bit line 28 by the column sense circuit 46 . On the other hand, V _in can be expressed as V _in = V _R + V ₂ or V _in = V _R + V ₃ . 1 at the output terminal, for a given value of V ₂ or V ₃ (Hi (high)) provides a corresponding VOH = VCE (sat) for the bit, or the output terminal for another given value of V ₂ or V ₃ 0 ( It is the choice of the static memory cell designer to use V _in = V ₂ or to use V _in = V _R + V ₃ = V _R + V ₂ to provide the corresponding VOL = VCC for the low low bit.

When the second embodiment of the present invention is shown and described in the following paragraphs, we turn to the fifth and sixth road attention.

In the second embodiment of the present invention, the write, read, and erase memory cells of FIG. 6 are designated for storing one or more bit of binary data of a particular type at a time, and all bits Or all bits stored in a given memory cell that are all 0 (low), but not all bit combinations at once.

A given memory cell is selected by applying a suitable signal to the base end 37 of the transistor M20 in order to write data to the memory cell of FIG. The column write, read and erase detection circuit 46 of FIG. 6 applies a predetermined voltage to the data write line 26, and the current is applied to the data lines 26 corresponding to the amount of electromagnetic or magnetic in the electromagnetic or magnetic element 36 of FIG. A predetermined write circuit flows through the magnetic or magnetic element 36 to the data write line 26 to induce an amount.

Once the data has been written to the cell, the data is supplied to the sense circuit 46 and the data write current and voltage is applied to the data write input emitter stage 52 at a predetermined output current at the collector stage output stage of transistor M20 and And becomes an input signal for generating an output voltage. The column write, read and erase sense circuit 46 measures the output data write output voltage and output current to determine the inherent connectivity and inherent functionality of the data write circuit loop.

The row select line 24 is activated by the decoder circuit 44 for each additional binary bit of the same specific data type to be written to and stored in the memory cell. The column write, read and erase sense circuitry 46 is a data storage magnetics that flows through the data write line 26 and represents the total number of additional binary bits of the particular data type that contain additional binary bits and are currently stored in the memory cell, A predetermined voltage is applied to the data write line 26, which in turn sends a corresponding predetermined data write current to the electro-magnetic element 36 to induce a corresponding amount of electromagnetic or magnetic. Read and erase detection circuit 46 of FIG. 6 to generate the corresponding data write output voltage and output current at the collector stage 55 of FIG. 6 and determine the unique data write circuit loop connection and function. The data write voltage and the write current become the input signals of the data write input emitter stage 52. [

To read the data stored in the one-transistor static write, read and erase memory cells of FIG. 6, the decoder circuit 44 of FIG. 8 applies a predetermined suitable voltage to the row select line 24, (24). The column write, read and erase detection circuitry 46 of FIG. 6 applies a predetermined data read voltage to the data read line 28 to provide a corresponding predetermined data read current flowing through the data read line 28 to the data And sends it to the reading element 34.

As already described in the first embodiment of the present invention, the data reading element 34 is connected to the terminal when current flows through its terminal in the presence of an electromagnetic field or a magnetic field, When an electric current flows through the inside of the device, such as a material that changes the voltage, that is, a semiconductor material such as indium antimonide, or where an electromagnetic or magnetic field exists, as shown in FIG. 4b, It is composed of elements such as iron-nickel alloy which changes resistance.

When the data read current now flows through the data read element 34, the voltage across the data read element 34 is proportional to the magnetic field 38 or magnetic field 38 in the same direction as H _x for 4a or Hy for 4b .

The intensity of the magnetic field or the electromagnetic field (H _x or Hy) is in turn dependent on the amount of electromagnetic or magnetic field induced by the data write current in the magnetic storage element 36 induced by the data read current.

In turn, the total amount of electromagnetic or magnetic in the magnetic storage element 36 is directly proportional to the number of binary bits of a particular type recorded in the memory cell 46 by the column write, read and erase detection circuitry 46 of FIG. 6 .

Thus, the voltage V _z across the data reading element 34 is directly proportional to the amount of data in the particular type of binary bit stored in the memory cell.

The voltage _Vz is itself either the dependent input voltage V _in of the data read input emitter terminal of Figure 6 or the data read voltage applied to the data read line 28 by the write, To become the dependent input voltage V _in .

A voltage V _z must be a sufficient voltage itgekkeum to create a transistor (M20) to the value of itself as soon as the saturation mode, or a voltage V _z As already described in the second embodiment, the data write cycle of the present invention, specific Readout and erase detection circuitry 46 that indicates whether the data in the form of one or more bits is combined with the data read voltage applied to the data read line 28 of Figure 6, Should be enough voltage to make it.

Therefore, V _in becomes the input voltage of the data read input emitter terminal 54, and the transistor M20 is set to a saturation state in which the voltage VCE between the input emitter terminal 54 and the collector terminal 55 is fixed or fixed Mode.

That is, in the second embodiment of the present invention, VCE becomes VCE (sat), and VCE is fixed or fixed regardless of the voltage of V _in as long as data is stored in the memory cell.

Referring to FIG. 6, the column write, read and erase sense circuit 46 measures the voltage V _x across the data read circuit loop. From Sixth Avenue,

V _x = V _in + V CE (Sat),

V _in = V _in (Sat) + V (data)

There is a relationship

V _x = V _in (sat) + V (data) + V CE (sat).

here,

V _x = total voltage read by the write, read and erase sense circuitry 46 that is in the data read circuit loop,

V _in (Sat) = the input voltage required to operate the transistor in saturation mode,

V (data) = the voltage across the data reading element 34, representing the amount of actual data of the binary bit stored in the memory cell either electronically or magnetically,

VCE (sat) = voltage between the data read input emitter terminal 54 and the monitor output collector terminal 55.

V _in (Sat) is constant, and a given switching transistor M20 is known to be used. It is also known that VCE (sat) is constant and a given switching transistor design (M20) is used. V _x is directly proportional to V (data). After measuring the V _x, by subtracting V _in (sat) and VCE (sat) from the value of V _x, it can be determined for V (data) that represents the actual amount of data in binary bits stored in the memory cell at any moment .

In particular, each bit of binary data in a particular form such as 1 (high) or 0 (low) is assigned a constant representative voltage. For example, binary bit 1 (high) is assigned a representative voltage of 1 mV. The amount of uniform representative voltage representing a unit bit of a particular data type is determined by the actual size of the electromagnetic or magnetic element 36, the amount of electromagnetic and corresponding electromagnetic or magnetic fields 38, the selected size and magnitude of the electromagnetic element 36 Or the magnitude and sensitivity of the data read element 34 associated with the amount of electromagnetic field that may affect the amount of data read current used and the magnitude of the voltage applied to the element and the amount of data read current used, When the circuit 46 measures the voltage of the small increment applied to the data read circuit loop which is between the point 200 and the point 220 as shown in Fig. 6, both ends of the data read element 34 It depends on whether you are sensitive enough.

The switching transistor M20 used, the column write, read and erase sense circuit 46, the data read element 34 and the electrostatic or magnetic data storage element 36 are connected to a voltage across the data read element 34, (I.e., a bit of a particular type of data) in order to fully exploit the advantages of the memory cell data storage capacity (V (data)), i.e. the memory cell data storage capacity, (Data) having a representative voltage with V (data).

However, the preferred range of the proposed unit bit representative voltage is not limited. The range may vary depending on the parameters of the design elements used, particularly the magnetic elements 34,36.

If V If _x is 5 volts to the transistor (M20) in the saturation mode,

VCE (sat) = - 0.1 volts,

V _in (Sat) = + 0.1 volts,

V _x = V _in (sat) + V (data) + V CE (sat)

V (data) = V _x - V _in (sat) - VCE (sat)

V (data) = 5 - 0.1 - (- 0.1) = 5 volts. V _x = V _c where V _c is the collector terminal voltage. Thus, V (data) can be measured by simply measuring the collector terminal voltage V _c using the write, read and erase sense circuit 46 and subtracting V _in (sat) and V CE (sat) from the value of V _c have.

In order to obtain the total number of binary bits stored in a specific form in a memory cell, the total representative voltage V (data) applied to the data read circuit loop is multiplied by a predetermined unit bit representing one bit unit predetermined in this case to 1 milli-bit Divided by the representative voltage. Therefore, 5 volts divided by 1 millivolt represents a specific type of data of the entire 5000 bits, that is, a bit having a value of 1 (high) or a bit having a value of 0 (low) It is not a bit with a combination of two forms of 0 or 1.

Once the number and type of bits stored in a given memory cell are measured and determined as described above, a copy of the bit-rich bits in the memory cell is sent to the buffer register or microprocessor register for computation via the data bus Loses.

A voltage representing a unit bit corresponding to 1 (high) may be used to indicate a unit bit corresponding to 0 (low). In contrast, the unit bits corresponding to 1 (high) and 0 (low) may be represented by voltages of different magnitudes.

The column write, read and erase sense circuit 46 of FIG. 3a, FIG. 6 and FIG. 8 has control lines R / W / E and CS, where R / W / While the write, read and erase input signals are applied on the control lines R / W / E, CS (Chip Select) is needed to select a given chip in a multi-chip system.

Furthermore, the column write, read and erase sense circuit 46 of FIGS. 3a, 6 and 8 increases all the required data output resistance and current so that the required memory S cycle is executed, And includes current and voltage measurement circuitry and amplification circuitry as well as the collector and emitter terminal resistances needed to provide the unique functions of the memory cell circuitry. As already described in the first embodiment of the present invention, since the resistors are not part of each memory cell and are shared by all the memory cells in one column, they are provided by the column write, read and erase sense circuit 46 This design with the necessary collector and emitter terminal resistors is a necessary and easy way, which reduces the area occupied by a single memory cell on the integrated circuit chip.

A decoder circuit 44 is used to apply a suitable voltage to the row select line 24 in order to erase the data written to the static write, read and erase memory cells with one transistor as in FIG. 6 Thereby selecting the memory cell. The data erase voltage is applied to the data erase line 32 by the column write, read and erase sense circuitry 46. A corresponding predetermined amount of current flows through the data erase line 32 and flows to the data storage or electronic device 36 but is in the opposite direction to the current flow of the data write current described in the data storage cycle. At this time, a demagnetization phenomenon occurs, so that data recorded and stored as magnetization in the electromagnetic or magnetic element 36 is erased.

The aforementioned data erase current flows through the data storage element 36 in a predetermined state by an amount corresponding to the total number of given binary data bits and is equal to the data write current used to magnetize the electromagnetic storage element 36 . Thus, by increasing the magnetization in the element 36 by the amount of magnetization representing the total number of binary bits of the particular data type currently stored in the memory cell containing the additional binary bits, the magnetic data storage element 36 is provided with data It is possible to erase data by a given number of bits at a time by reducing the magnetization of the electromagnetic storage element 36, as can be recorded or stored. In some designs it may be necessary to selectively read the data stored in the cell before erasing the data because the erase circuit in the column write, read and erase detection circuitry 46 is stored in the memory cell before the erase cycle proceeds It is to know exactly how many data bits are. This design is readily used in memory design applications where data write cycle time, data read cycle time and data erase cycle time are not critical.

A third embodiment of the present invention will now be described with reference to Figures 3b and 3bb. A ROM composed of one transistor is read or repeatedly read by a digital system which is an important part of the memory cell of the third embodiment, the data being recorded or stored in the memory cell fabrication.

The ROM cell may use the bipolar switching transistor technique shown in FIG. 3a or the MOS switching transistor technology shown in FIG. 3bb.

A ROM cell designed to store one bit of data per memory cell, regardless of the switching transistor technology used, except that the data is written or stored at the time of the ROM cell fabrication, as described in the data read cycle of the first embodiment of the present invention. . Furthermore, the switching transistor M21 of the third circuit is different from the switching transistor M20 of the third circuit diagram in that one emitter is provided. The switching transistor M21 of the third circuit has a collector terminal 55 which operates as an input terminal and an emitter terminal 54 which operates as an output terminal irrespective of the result. An external data write circuit is used to write data to the cell during cell fabrication. The data is read from the ROM cell as described in the first embodiment of the present invention.

In a ROM cell designed to temporarily store a particular type of data bit in excess of one bit, the data may be stored in a magnetic or electrostatic device 36 of the third degree when fabricating the ROM cell as described in the second embodiment of the present invention. Recorded or stored. In the data write cycle in cell fabrication, an external data read circuit is used instead of the column write, read and erase detection circuit 46 as described in the second embodiment.

The data is read from the ROM cell of the third degree as described in the second embodiment of the present invention, and the readout circuit of the third degree comprises a voltage measurement circuit for measuring the voltage V _x across the data read circuit loop. Where V _x = V _in + VEC (sat) and V _in = V _in (sat) + V (data). Therefore, V _x = V _in (sat) + VEC (sat) + V (data) and V _x is the capacitance between two points 200 and 220 defining the data read circuit loop of the memory cell shown in FIG. Voltage.

As previously described in the function of the data read cycle of the second embodiment, in order to obtain the total number of data bits of a particular type stored in the ROM cell, V (data) is a predetermined voltage .

In conjunction with the third embodiment of the present invention using MOS (Metal-Oxide Semiconductor) technology, when the ROM cell of Figure 3bb is designed to store one bit or more than one bit at a time, the data read sense circuit 74 ) is a point (400) (x) and points (600) (y) is the voltage V _z there is measured the V _z = V _t + V (data) between, V _t is a voltage drop across the transistor (M21), V (data) is a voltage applied to the data reading element 34. [

V _t is the gate voltage applied to turn on the transistor, and V (data) can be obtained by measuring V _z , which is the voltage across the data read circuit loop.

Once the V (data) is determined by the data readout detection circuit 74 of FIG. 3bb, V (data) is divided by a predetermined amount of voltage assigned to indicate a bit of a particular binary type, The total number of bits of a particular type of binary data is obtained. A copy of a bit (COPY) is sent to the data bus to be moved by another circuit, such as a microprocessor, for a particular function.

When designing to retain a particular type of data for more than one bit as described in the second embodiment of the present invention, the write, read and erase sense circuitry 46 of FIG. It is necessary to create data in a way that is easier and faster to access.

Turning to FIG. 8, a 256 x 8 transistor static write, read and erase memory cell array is shown. In general, in order to store data of one word length in a memory cell array, it is necessary to precisely define the number of binary bits (standard word length) (8 bits in the case of FIG. 8).

If the standard word length is n bits, then there is a single address space (1 to 2 ⁿ ) designed to store a single word of 2 ⁿ single addresses (address space), and specific data that can be stored by each memory cell in a single address space at a given time Is defined as a single address space capable of storing a single word of one or more bits up to a predetermined maximum number depending on the maximum number of binary bits of the form.

If n is 8, as shown in FIG. 8, the standard word length is 8 bits per word and 2 ⁿ is a single address of 256 as the total address space capacity of the memory cell array. Since each address space is allocated to store in an 8-bit word, each memory cell having a specific address space can be formed of only one type of binary bit, that is, 1 (high) Bit or < RTI ID = 0.0 > 0 < / RTI >

If the memory cells in the address space are designed to store 5000 bits of data, then the 256 address spaces in the memory cell array, as described in the second embodiment of the present invention, will have a standard word length of 8 It is possible to store 5000 words, which is a bit.

Thus, the address space W ₁ can store up to 5000 words with a single bit array 00000000 of 8 bits each. In FIG. 8, the address space W ₂ can store up to 5000 words in a single bit array 00000001 of 8 bits each.

In FIG. 8, the address space W ₃ can store up to 5000 words with a bit array 00000010 of 8 bits each. In FIG. 8, the address space W ₄ can store up to 5000 words with a bit array 00000011 of 8 bits each have. Finally, in FIG. 8, the address space W ₂₅₆ may store up to 5000 words in a bit array 11111111 of 8 bits each. The address between W ₄ and W ₂₅₆ is omitted from the paper and the data word is stored in the above form. For example, the address space W ₂₅₄ stores the word of a single word 11111101, and W ₂₅₅ stores the word of a single word 11111110.

A second embodiment of the present invention will be described in detail with reference to FIG.

A memory cell array with 256 rows and 8 columns capable of storing one or more binary data is shown in FIG. Also, two simple programs, Program 1 and Program 2, are shown in Figure 9 in the form of machine language, each program having eight instructions and each instruction having a standard word length of 8 bits. Eight memory cells corresponding to address space 0 are designed to store the word 00000000. The eight memory cells corresponding to address space 1 are designed to store the word 00000001, and the address space 2 is designed to store the word 00000010. The address space 3 is designed to store the word 00000011, and finally the address space 7 stores 00000111. Address spaces 8 through 255 may be empty or may be allocated for other data. Therefore, the instructions of program 1 and program 2 will be stored in the memory cell array as follows.

Address space B will store Instruction A of Program 1 and Instruction N of Program 2. Address space 1 will store instruction B of program 1 and instruction K of program 2. Address space 2 will store Instruction C of Program 1 and Instruction I of Program 2. Address space 3 will store instruction D of program 1 and instruction L of program 2. The address space 4 stores the instruction E of the program 1 and the instruction O of the program 2. [ The address space 5 will store Instruction I of Program 1 and Instruction M of Program 2. Address space 6 will store instruction G of program 1 and instruction P of program 2, and address space I will store instruction 1 of program 1 and instruction J of program 2.

Referring to the data read of one word stored in the memory cell array as in FIG. 8, the number of all bits stored in each memory cell of the selected address space is read as described in the second embodiment of the present invention, Taking a copy of the same bit as the bits read from all the memory cells in the space and sending it to the data bus of the digital system having the memory cell as a component and using the column write, read and erase detection circuit 46 of FIG. 6 One bit of data copied from each memory cell is sent to another part of the digital system, such as a microprocessor, that needs word-shaped data.

If each memory cell in FIG. 9 is designed to store only one bit per memory cell, then the address space between address space 0 and address space 7 has the ability to store only one program from program 1 to program 2 Programs 1 and 2 can not be stored at the same time.

However, since these memory cells from address space 0 to address space 7 can simultaneously store one or more bits of a particular type of data, both program 1 and program 2 can be easily stored in the available address space and can store more data There is a margin for the number of binary bits that each memory cell can simultaneously store.

The present invention is fully described in the third embodiment, and slight modifications are possible in the third embodiment. For example, a switching transistor structure, which is described in the first embodiment and gives a voltage input / output characteristic different from that shown in FIG. 5, may be used instead of the transistor M20.

Furthermore, the data reading element 34 of FIGS. 3a and 6 may be a magnetic field which crosses a given direction or another element which changes the voltage or resistance applied to the element terminal when it flows in proportion to the strength of the electromagnetic field. The element 34 in FIG. 3a can be replaced with an indium antimonide semiconductor, an iron-nickel alloy, or a bonded magnetic stripe.

The data read element 34 also requires two or more terminals to form a data read circuit loop in the memory cells of Figs. 3a, 3b, 3bb and 6d. The additional signal line means preferably connecting the additional terminals of each data read element 34 to the write, read and erase sense circuit 46 is shown in Figures 3a, 3b, 3bb and 6 Lt; RTI ID = 0.0 > memory cell. ≪ / RTI >

Furthermore, the number of binary bits that each memory cell can store in accordance with the second embodiment of the present invention depends on how the design is implemented and also depends on the size and sensitivity of the elements used in the data read element 34 of FIG. 6, The level and size of the write, read and erase signals that are acceptable in the design, the range of voltages, currents, and resistances that the circuit components can accommodate, and the nature of the data storage magnetic or electronic elements 36, Such as the sensitivity and voltage range of the write, read and erase sense circuitry 46.

However, as will be understood by those skilled in the art, the present invention provides a memory cell of a first and second embodiment, also known as an EPROM, and a memory cell of FIG. 1b, and of NMOS and PMOS SRAM technology is used as an excellent alternative to the memory cell associated with SRAM technology, where the memory cell has at least six transistors compared to one transistor. Therefore, the area of the chip can be reduced by the present invention.

Since the data storage element of the present invention has a magnetic material, the data storage element can be coupled to all of the memory cells as if metal wiring carrying the signal was easily etched on the chip.

Compared to 16M, 64M and 256M bit DRAM memory chips, the first and second embodiments of the present invention can be an excellent alternative to the DRAM memory chip in many respects.

First, DRAM is dynamic as it is by name, but its onset is permanent static write, read and erase memory. Thus, in the first embodiment of the present invention, it is possible to operate as SRAM, RAM, ROM and EPROM for all digital systems, so that data stored in main memory of such a digital system can be stored in peripheral storage such as magnetic disks and magnetic tape You do not need to download it to your device.

Second, the second embodiment of the present invention has the advantage of having a data storage capacity much larger than the data storage capacity per memory cell of current DRAM memory in addition to the above-mentioned advantages.

A 16M DRAM has exactly 16,777,216 memory cells and can store exactly 16,777,216 bits or 2,097,152 bytes of data per chip. Comparing the 16M memory cell according to the second embodiment of the present invention, as described above, each memory cell is given a maximum number of 5000 (5000, for example) in a specific form and depends on the parameters related to the design of the used memory cell Bit data, it has 16,777,216 memory cells but stores 16,777,216 × 5,000 bits, or 8.388608 × 10 ¹⁰ bits, 1.048576 × 10 ¹⁰ bytes, or 10.48576 gigabytes of data.

Third, in the first to third embodiments, the present invention can be formed in a memory cartridge format or a memory card format, and is also used as follows.

(a) In the first and second embodiments, data is recorded in a digital system that needs to conserve the electric energy consumed in blank memory cartridges and blank memory cards and magnetic and magnetic tape drives And can be used as a removable memory cartridge and a memory card. Such digital systems include portable laptop computers and personal digital assistants (PDAs). In contrast, current DRAM memory requires a certain amount of power to store stored data and is therefore not used in memory cartridges and memory cards.

(b) The second embodiment according to the present invention can be incorporated in a memory cartridge and a memory card, which are pre-recorded in sound and video equipment, and such recording data can be recorded in sound and video equipment And also conserves the energy used in current acoustic and imaging devices that use magnetic tape, magnetic, and laser disk drives.

(c) In the third embodiment, since the present invention can be embedded in a ROM cartridge and a ROM memory card widely used in a digital system, the ROM cartridge and the ROM memory card include a prepared software package . This structure is convenient when long software that requires very large storage space needs to be used repeatedly and thus needs to be accommodated in the permanent main memory of such a digital system. Unlike current static RAM (SRAM), ROM and RAM, this structure is feasible because the present invention has a very large data storage capacity.

Fourth, in the second and third embodiments according to the present invention, electric energy is saved when compared with an optical disk drive, a peripheral data storage device such as a magnetic tape and a magnetic disk drive, and an SRAM having six transistors do. For example, an integrated circuit chip of a 16M cell may have a capacity of about 10.48576, which is close to the capacity of a recent two-sided CD-ROM technology when one cell is designated to store 5000 bits of data, as previously described in the Detailed Description of the Invention. Store G bytes. What's even better is that while the present invention is a main memory on a substrate, the memory drive is a time consuming and energy-consuming peripheral device for operating the motor device that drives it when accessing and storing data from them .

Fifth, since the memory cell of the present invention is smaller than the memory cell of the SRAM including six transistors, the movement distance of the data signal required for reading and writing each bit is short, so that the SRAM of six transistors writes and reads data It has a cycle several times shorter than the cycle required.

Sixth, according to the present invention, in a six-transistor SRAM, the DC voltage must be constantly supplied in order to store data on the flip-flop, whereas the present invention supplies a constant power to the data stored in the memory cell There is no need to save energy when compared to a six transistor SRAM.

In the present invention, even if the power supply of the memory cell is shut off, the data can be stored in the state of being stored in the memory cell with electromagnetic energy.

Therefore, the present invention is not limited to the above-described embodiments, and the scope should be determined by the claims and legal equivalents.

Claims (20)

In one transistor static write, read and erase memory cell for storing data until erasure, a) switching transistor means for switching said one transistor static write, read and erase memory cell; b) a row in which a first terminal is connected to decoding means and a second terminal is connected to said switching transistor means for applying a predetermined amount of voltage to select said one transistor static write, read and erase memory cell, Selection line means; c) electromagnetic or magnetic element means for storing binary data in electromagnetic or magnetic form; d) connected to said electromagnetic or magnetic element means in such a way as to induce a predetermined electromagnetic or magnetic quantity indicative of a specific number of bits of a particular binary form of said "1" binary character or "0" binary data in said electromagnetic or magnetic element; Data write bit line means for applying a predetermined data write voltage causing a predetermined corresponding data write current to flow to said electronic or magnetic element means; and e) a control unit connected to the electromagnetic or magnetic element means to cause a corresponding predetermined amount of erase current to flow to the electromagnetic or magnetic element means, Data erase bit line means for applying the data erase voltage flowing through the electromagnetic or magnetic element means in a direction opposite to the flow direction of the data write current to affect demagnetization of electromagnetic or magnetic fields; f) data read bit line means to which a data read current is sent; g) through said two terminals of said data reading element means in the presence of an electromagnetic or magnetic field generated by said predetermined electromagnetic or magnetic quantity induced in said electromagnetic or magnetic element means by said data write current and exhibiting a particular direction Data reading element means of a suitable material having the characteristics of changing the voltage across said two terminals when said two terminals are connected to said data read bit line means; And and h) a transistor coupled to the collector terminal of the switching transistor means for channeling the collector current during the write, read and erase cycles of the one transistor static write, read and erase memory cells and for outputting the output voltage and the collector An output voltage and output current bit line means for providing a current connection. ≪ RTI ID = 0.0 > 1 < / RTI > The method according to claim 1, And a first input emitter terminal is coupled to the first end of the data write bit line. The method according to claim 1, And a second input emitter terminal is coupled to the first end of the data read bit line means. The method according to claim 1, And a third input emitter terminal is coupled to the first end of the data erase bit line means. The method according to claim 1, And a second end of the data write bit line is connected to the column write, read and erase sense circuit means. The method according to claim 1, And the second end of the data read bit line means is connected to the column write, read and erase sense circuit means. The method according to claim 1, And the second stage of the data erase bit line means is connected to the column write, read and erase sense circuit means. The method according to claim 1, The switching transistor means having only one of the input emitter terminals of the switching transistor means during the data cycle function has the high input voltage carrying an input voltage signal and an input current signal of a particular data cycle function under a given item, The remaining emitter terminals having a low input voltage or performing an OR operation in sense with an input supply voltage separated from within the column write, read and erase sense circuit. . The method according to claim 1, Further comprising a data read sub circuit for measuring one of a voltage applied to the data read element and a resistance applied to the data read element, wherein the column write, read and erase sense circuit The predetermined data write current, the predetermined data read voltage, the corresponding predetermined data read current, the predetermined data erase voltage, and the corresponding predetermined data erase current. Transistor static write, read and erase memory cells. The method according to claim 1, When said data read current is configured to flow through a terminal of said data read element means, said data read element means is arranged to be arranged in such a way that the data read element means, in proportion to said electromagnetic or magnetic field across said data read element means, Wherein the memory cell is comprised of an indium antimonide semiconductor material having characteristics that change the voltage across the two terminals. The method according to claim 1, When said data read current is configured to flow through a terminal of said data read element means, said data read element means is arranged to be arranged in such a way that the data read element means, in proportion to said electromagnetic or magnetic field across said data read element means, Wherein the first and second terminals are made of iron and a nickel alloy having characteristics that change the electrical resistance between the two terminals. The method according to claim 1, Wherein said data reading element means is arranged in such a way that when said data reading current is configured to flow through said data reading element means, And a material having a characteristic of changing the electrical resistance between the terminals. The method according to claim 1, The electromagnetic or magnetic element means for storing data may comprise means for providing a first electromagnetic or magnetic quantity representative of a particular first binary logic bit and a second electromagnetic or magnetic quantity representative of a particular second binary logic bit, Wherein the memory cell is a memory cell. The method according to claim 1, Characterized in that said electromagnetic or magnetic element means is capable of being electromagnetized or magnetized into a plurality of electromagnetic or magnetic quantities such that each of said plurality of electromagnetic or magnetic quantities represents a specific number of binary bits which are all of the same binary logic level Transistor static write, read and erase memory cells. The method according to claim 1, Characterized in that said electromagnetic or magnetic element means is capable of erasing a particular first electromagnetic or magnetic quantity representing a particular first binary logic bit and a particular second electromagnetic or magnetic quantity representing a particular second binary logic bit. Static write, read and erase memory cells. The method according to claim 1, Wherein said electromagnetic or magnetic element means is capable of erasing a given electromagnetic or magnetic quantity representative of the number of specific binary bits of the same binary logic level. A method for reading data stored in a one-bit transistor static write, read and erase memory cell, a) applying a voltage suitable for a row select line to select said one transistor static write, read and erase memory cell for data reading; and b) a data storage cell for storing data by a data write current when the data read current is configured to flow through both terminals of the data read element means, And the data readout bit line means having a characteristic to change the voltage or resistance applied to both ends of the data read element means in proportion to the current magnetic field or magnetic field of the corresponding direction Applying a predetermined amount of data read voltage to the data read bit line to cause the data read bit line to flow; c) when said data read voltage applied to said data read bit line means is added either independently or to a data read input emitter terminal of a switching transistor of said one transistor static write, read and erase memory cell, The voltage across the terminal being coupled to an output of the switching transistor to indicate a different form of a low input voltage or a binary bit that causes a particular first output voltage amount at an output of the switching transistor to indicate a form of binary bits Setting a subsidiary input voltage that is one of a high input voltage causing a specific second output voltage amount; read and erase sense circuit means connected to said output of said switching transistor for determining the type of binary bit stored in said one transistor static write, read and erase memory cell, Measuring a second output voltage amount; e) at the output of the switching transistor, by measuring the output voltage at the output of the switching transistor that is not equal to either the particular first output voltage or the particular second output voltage, Reading and erasing memory cells, wherein the sensing circuit is configured to determine an empty of data stored in the one transistor static write, read and erase memory cell. / RTI > CLAIMS What is claimed is: 1. A method for reading data stored in a transistor static write, read and erase memory cell for processing one or more bits, a) applying a predetermined voltage to a row select line to select said one transistor static write, read and erase memory cell during a data read cycle; b) two terminals of the data reading element means having a characteristic of changing either voltage or resistance in a current electromagnetic field or a magnetic field provided by a given electromagnetic or magnetic quantity induced by the data writing current to the electromagnetic or magnetic element means Which is proportional to the electromagnetic field or the magnetic field, so that a corresponding predetermined data read current flows through the two terminals of the data read bit line means and the data read element means when the data read current flows in a specific direction, Applying a predetermined amount of voltage to the data read bit line to generate a voltage across the means; c) the voltage drop across the data read input emitter terminal of the switching transistor and the collector terminal of the switching transistor is set to a constant value so that the switching transistor of the one transistor static write, read and erase memory cell immediately operates in the saturation mode, And when the data read voltage is inputted to the data read input emitter terminal of the one transistor static write, read and erase memory cell, the data read voltage applied to the data read bit line means is judged to be sufficiently small ; d) measuring the total voltage across the data read circuit loops of said one transistor static write, read and erase memory cells using column write, read and erase sense circuit means connected to said data read circuit loop; e) applying a constant voltage between said data read input emitter terminal and said collector terminal to said data read voltage applied to said data read bit line means to obtain a voltage metric using said column write, read and erase sense circuit means; Adding a descent; f) the one transistor static write, the one transistor static write, and the one transistor write operation to conserve the amount of voltage across the data read element means directly proportional to the total number of binary bits of data of the allotment type stored in the one transistor static write, Subtracting the voltage subtract from the total voltage across the data read circuit loop of the read and erase memory cells; g) subtracting said amount of voltage applied to said data reading element means from said assigned type of data to obtain the total number of binary bits of data of said allocation type stored in said one transistor static write, read and erase memory cell at a particular time Using column write, read and erase sense circuit means to divide by a certain predetermined amount of voltage representing one binary bit; And h) taking a copy of one binary bit of the assigned type of data measured by said column write, read and erase sense circuit means and taking said one transistor static write, read and erase memory cell on a digital system data bus channel And controlling the binary bit to be transferred to another part of the digital system, such as a microprocessor with the component. The one-transistor static write processing one or more bits, the data stored in the read and erase memory cells / RTI > 19. The method of claim 18, During the data read cycle using the column write, read and erase sense circuit means connected to the collector terminal, the total voltage across the data read circuit loop is realized by measuring the output voltage at the collector terminal of the switching transistor Wherein the one or more bits of data are read from the memory cell. A method for arranging data in a transistor static write, read and erase memory cell array, a) determining a reference length of a word of the data to be stored in the one transistor static write, read and erase memory cell array by specifying a maximum number of binary bits that a data word may contain; b) the maximum number of the binary bits having the reference length of the word of data that can be arranged causes the formation of a unique reference length word of data, and the only reference length corresponding to one transistor static write, read and erase memory cell array Assigning an address space within the one transistor static write, read and erase memory cell array as a method for allocating the unique reference length word of data to an address space; c) storing said unique reference length word of data in a corresponding assigned reference length address space corresponding to said one transistor static write, read and erase memory cell array; and d) storing all additional said unique reference length words of data in a correspondingly assigned reference length address space corresponding to said one transistor static write, read and erase memory cell arrays. Write, read and erase memory cell arrays.