KR100272914B1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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KR100272914B1
KR100272914B1 KR1019970060395A KR19970060395A KR100272914B1 KR 100272914 B1 KR100272914 B1 KR 100272914B1 KR 1019970060395 A KR1019970060395 A KR 1019970060395A KR 19970060395 A KR19970060395 A KR 19970060395A KR 100272914 B1 KR100272914 B1 KR 100272914B1
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chip
option
alignment
circuit
connection
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KR19980042497A (en
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가주히사 다지마
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가네꼬 히사시
닛본 덴키 가부시키가이샤
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Abstract

제조 기간의 단축, 집적도의 향상, 소형화, 및 적응 범위의 확대를 도모한다.It aims to shorten the manufacturing period, improve the integration degree, reduce the size, and expand the adaptation range.

다수 종류의 커스텀 회로에 대하여 범용성이 있는 기본기능, 공통 기능을 구비한 공통 기본 회로(11) 및 다수의 범프 전극(14)으로 구성된 옵션 접속부(15)가 형성된 머더 칩(1)에, 공통 기본 회로(11)에 대한 각종 변경을 담아 넣은 옵션 회로 및 다수의 범프 전극(21)으로 이루어지는 접속부가 형성된 옵션 칩(2)을, 다수의 범프 전극(14) 및 다수의 범프 전극(21)을 서로 대응 접속하여 탑재한다. 머더칩(1) 및 옵션 칩(2)은 별도로 제작할 수 있고, 또한, 옵션 탑재부(15)의 영역에도 공통 기본 회로(11)가 형성될 수 있다.The common basic to the mother chip 1 in which the basic connection which is universal with respect to many types of custom circuits, the common basic circuit 11 with common functions, and the option connection part 15 comprised from the several bump electrodes 14 were formed. The option chip 2 containing the various changes to the circuit 11 and the option chip 2 including the connection part formed of the plurality of bump electrodes 21 are formed, and the plurality of bump electrodes 14 and the plurality of bump electrodes 21 are connected to each other. Correspond to the connection and mount. The mother chip 1 and the option chip 2 can be manufactured separately, and a common basic circuit 11 can also be formed in the region of the option mounting part 15.

Description

반도체 집적회로Semiconductor integrated circuit

본 발명은 반도체 집적 회로에 관한 것으로, 특히 사용자의 요구를 담은 커스텀 회로 부분을 포함하는 반도체 집적 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits that include custom circuit portions that accommodate user needs.

사용자의 요구를 담은 커스텀 회로 부분을 포함하는 반도체 집적 회로는 1장의 칩상에, 많은 커스텀 회로 부분에 대하여 공통인 기본적인 회로 부분과, 개개의 사용자를 향한 커스텀회로 부분을 형성하는 경우가 많다.BACKGROUND OF THE INVENTION [0002] A semiconductor integrated circuit including a custom circuit portion that meets the needs of a user often forms, on one chip, a basic circuit portion common to many custom circuit portions and a custom circuit portion for an individual user.

이러한 반도체 집적 회로의 종래의 제 1 예의 칩의 레이아웃도를 제5도에 도시한다.5 is a layout diagram of a chip of the first conventional example of such a semiconductor integrated circuit.

상기 반도체 집적 회로는 1장의 반도체 기판의 소정의 영역에, 다수 종류의 커스텀 회로에 대하여 범용성이 있는 소정의 기본 기능, 공통 기능을 구비한 공통 기본 회로(11a)와, 이 공통 기본 회로(11a)의 영역외 PD 소정의 영역에 공통 기본회로(11a)의 소정의 부분에 대한 규정 변경 기능 변경, 기능 추가 등을 포함하는 각종 변경을 담아 넣은 커스텀 회로(20)와, 반도체 기판의 주변부에, 공통 기본 회로(111a) 및 커스텀 회로(20)와 외부 회로를 접속하는 다수의 전극 패드(12)가 형성된 집적 회로 칩(10)을 갖는 구성으로 되어 있다.The semiconductor integrated circuit includes a common basic circuit 11a having a predetermined basic function and a common function that are versatile for a plurality of types of custom circuits in a predetermined region of one semiconductor substrate, and the common basic circuit 11a. The custom circuit 20 in which various modifications including a change of a prescribed function for a predetermined portion of the common basic circuit 11a, addition of a function, etc. are stored in a predetermined region of the PD outside the region of the PD, and the peripheral portion of the semiconductor substrate is common. The integrated circuit chip 10 is provided with a plurality of electrode pads 12 connecting the basic circuit 111a and the custom circuit 20 to an external circuit.

이러한 반도체 집적 회로를 제조하는 경우, 제조 기간(TAT)을 단축하기 위해서, 커스텀 회로(20)를 제외한 부분은 미리 제작해 두고, 커스텀 회로(20) 부분은 수주에 따라서, 사용자의 요구를 담아 후속 공정에서 제조해 넣는 방법을 취하고 있다. 이렇게 함에 따라, 후속 공정으로 제조해 넣는 커스텀 회로(20) 부분은 집적 회로 칩(10) 전체와 비교하면 작기 때문에, 수주로부터 납품까지의 제조 기간, 집적 회로 칩(10) 전체의 제조기간을 단축할 수 있다.In the case of manufacturing such a semiconductor integrated circuit, in order to shorten the manufacturing period (TAT), parts except for the custom circuit 20 are manufactured in advance, and the custom circuit 20 part is made according to the user's request according to the order. It takes the method to manufacture in a process. As a result, since the portion of the custom circuit 20 manufactured in the subsequent process is smaller than the integrated circuit chip 10 as a whole, the manufacturing period from order to delivery and the manufacturing period of the integrated circuit chip 10 are shortened. can do.

또한, 개발 기간이 짧고, 또한 다품종 소량 생산에 대응할 수 있는 커스텀형 반도체 집적 회로로서, 일본특허공개 평4-199742호 공보 기재의 예가 있다. 이 공보를 참조하여 작성한 종래의 반도체 집적 회로의 제 2 예의 레이아웃도 및 부분확대측면도를 제6(a),(b)도에 도시한다.In addition, there is an example of Japanese Patent Laid-Open No. 4-199742 as a custom semiconductor integrated circuit that has a short development period and can cope with a small quantity production of a large variety of products. The layout diagram and partial enlarged side view of a second example of a conventional semiconductor integrated circuit created with reference to this publication are shown in FIGS. 6 (a) and (b).

이 반도체 집적 회로는 기판의 주변 부분 및 그 안쪽의 소정의 위치에 설치된 다수의 전극 패드(31) 및 이들 다수의 전극 패드와 접속하여 사용자의 요구에 따라서 배선 경로나 배선, 전극 패드간의 접속 등이 결정되는 커스텀화된 배선을 구비한 모듈 기판(30)과, 이 모듈 기판의 안쪽의 전극 패드(81)와 접속하여 모듈 기판(30)에 탑재되어 집적 회로 전체를 구성하는 다수의 칩(40)을 갖는 구성으로 되어 있다.The semiconductor integrated circuit is connected to a plurality of electrode pads 31 provided at the periphery of the substrate and a predetermined position therein, and to the plurality of electrode pads so that wiring paths, wiring, connection between the electrode pads, etc. can be made according to a user's request. A plurality of chips 40 mounted on the module substrate 30 by connecting to the module substrate 30 having the determined customized wirings and the electrode pads 81 inside the module substrate and constituting the entire integrated circuit. It is configured as having.

이 반도체 집적 회로의 모듈 기판(30)은 다수의 배선이 평행하게 달리는 배선층을 복치층, 각 층간의 배선이 상호 교차하도록 형성하여, 이들 각 중간의 배선 및 배선·전극 패드간의 접속을, 기록 회로에 의해 사용자의 요구에 따라서 완성하도록 되어 있고, 탑재되는 칩(40)의 내용에 따라서, 배선 경로, 배선과 주변의 전극 패드(31) 사이의 접속, 배선과 안쪽(칩(40)을 탑재 접속한다)의 전극 패드(31)의 접속을 결정할 수 있다. 또한, 다수의 칩(40) 각각은 평행하여 설계, 제작할 수 있다. 따라서, 다품종 소량 생산이라도, 개발 기간, 제조 기간을 짧게 할 수 있다.The module substrate 30 of this semiconductor integrated circuit forms a wiring layer in which a plurality of wirings run in parallel so that the interconnection layer and the wirings between the layers cross each other, and the connection between these intermediate wirings and the wiring and electrode pads is connected to the recording circuit. By the user's request, and according to the contents of the chip 40 to be mounted, the wiring path, the connection between the wiring and the peripheral electrode pad 31, the wiring and the inside (mounting the chip 40 and connecting Connection of the electrode pad 31 can be determined. In addition, each of the plurality of chips 40 can be designed and manufactured in parallel. Therefore, even in a small quantity production of many kinds, a development period and a manufacturing period can be shortened.

상술한 종래의 반도체 집적 회로는 제 1 예에서는 커스텀 회로(20) 부분 이외를 미리 제작해 두고, 커스텀 회로(20)부분은 수주 후, 후속 공정으로 제조해 넣는 구조로 되어 있기 때문에, 후속 공정에서 제조해 넣은 부분이 적고, 수주로부터 납품까지의 제조 기간, 집적 회로 칩(10) 전체의 제조 기간을 단축할 수 있지만, 커스텀 회로(20) 부분 이외의 부분의 제작과, 커스텀 회로(20) 부분의 제작이 시간적으로 완전히 시리얼(serial)로 되기 때문에, 제조 기간의 단축에는 한계가 있고, 또한, 제조 기간의 단축이 곤란한 문제점과, 커스텀 회로(20)의 형성 영역이 한정되기 때문에, 커스텀화에 대한 적응 범위가 좁은 문제점이 있다.In the above-described conventional semiconductor integrated circuit, in the first example, a part other than the custom circuit 20 part is manufactured in advance, and the custom circuit 20 part is manufactured in a subsequent step after several weeks. Although there are few parts manufactured, the manufacturing period from an order to delivery and the manufacturing period of the whole integrated circuit chip 10 can be shortened, but manufacture of parts other than the custom circuit 20 part and the custom circuit 20 part Since the fabrication of the product becomes completely serial in time, there is a limitation in shortening the manufacturing period, and it is difficult to shorten the manufacturing period, and the formation area of the custom circuit 20 is limited. There is a problem of a narrow adaptation range.

또한, 제 2 예에서는 모듈 기판(30)은 그 제조 후에도 배선 및 전극 패드(81)를 칩(40)의 내용에 맞추어 결정할 수 있기 때문에, 개발기간이 짧고, 또한 다품종 소량 생산에 대응할 수 있지만, 모듈 기판(30)은 범용성을 높이기 위해서 실제로 사용하지 않는 배선이 많아 그 면적이 커진다고 하는 문제점과, 모듈 기판(30)에는 배선 및 전극 패드(31) 및 이들의 접속제어를 위한, 기록회로만이 설치되어 있어 집적 회로 본래의 회로는 칩(40)에만 형성되어 있는 배선과 집적 회로가 별개의 기판으로 되기 때문에, 전체가 대형화하여, 집적도가 낮다고 하는 결점과, 미세화가 진행하여 인접하는 전극 패드(31)간의 간격이 좁게 되면, 모듈 기판(30)의 전극 패드(31)와 칩(40)의 전극 패드(41)의 위치를 정확히 맞추어 접속할 필요가 있지만, 그 위치 맞춤(얼라인먼트)을 위한 수단이 없기 때문에, 전극 패드(31, 41)사이의 오류 접속이나 인접하는 전극 패드끼리가 단락하는 좋지 않은 상황이 발생하기 쉽다고 하는 문제점과, 칩(40)이 전극 패드(31, 41)의 접속만으로 모듈 기판(30)에 탑재되어 있기 때문에, 칩(40)에 힘(스트레스)이 가해졌을 때 파손되기 쉬운 문제점이 있다.In addition, in the second example, since the module substrate 30 can determine the wiring and the electrode pad 81 according to the contents of the chip 40 even after its manufacture, the development period is short and it is possible to cope with the production of small quantities of various kinds. In order to increase the versatility, the module substrate 30 has a problem that a large number of wirings are not actually used, and the area thereof becomes large. In addition, only the recording circuits for the wiring and the electrode pad 31 and their connection control are provided in the module substrate 30. Since the circuits provided in the integrated circuit and the integrated circuit formed only on the chip 40 are formed as separate substrates, the entire circuit is enlarged, the defect of low integration degree, and miniaturization proceed to the adjacent electrode pad ( If the interval between the 31 is narrow, it is necessary to connect the electrode pad 31 of the module substrate 30 and the electrode pad 41 of the chip 40 to be exactly matched, but for the alignment (alignment) Since there is no stage, there is a problem that an error connection between the electrode pads 31 and 41 and an unfavorable situation in which adjacent electrode pads are shorted easily occur, and the chip 40 is connected to the electrode pads 31 and 41. Since it is mounted on the module substrate 30 only, there is a problem that breakage occurs when a force (stress) is applied to the chip 40.

본 발명의 목적은, 첫째, 집적도의 향상 및 소형화를 꾀함과 동시에 제조 기간을 단축하고 또한 커스텀화에 대응하는 적응 범위를 확대할 수 있고, 제 2에, 미세화 진전시의 오류접속이나 단락 사고의 발생을 방지함과 동시에 칩에 대한 스트레스 인가시의 파손을 방지할 수 있는 반도체 집적 회로를 제공하는데 있다.The object of the present invention is firstly to improve the density and to reduce the size, to shorten the manufacturing period and to expand the adaptation range corresponding to the customization, and secondly, to prevent the error connection and the short circuit accident at the time of miniaturization. The present invention provides a semiconductor integrated circuit capable of preventing occurrence and at the same time preventing breakage upon application of stress to a chip.

본 발명의 반도체 집적 회로는 다수 종류의 커스텀 회로에 대하여 범용성이 있는 소정의 기본 기능, 공통 기능을 구비한 공통 기본 회로 및 이 공통 기본 회로와 접속하여 소정의 위치에 설치된 다수의 제 1 접속 단자를 포함한 옵션 접속부가 형성된 머더 칩부에, 상기 공통 기본 회로의 소정의 부분에 대응하는 규정 변경, 기능 변경, 기능 부가를 포함한 각종 변경을 담은 커스텀 회로 부분의 옵션 회로 및 상기 옵션 접속부의 다수의 제 1 접속 단자 각각과 대응하는 다수의 제 2 접속단자를 포함한 접속부가 형성된 옵션 칩을, 상기 다수의 제 1 접속 단자 및 다수의 제 2 접속 단자를 대응 접속하여 탑재하여 이루어진 구성을 갖고 있다. 또한, 다수의 제 1 및 제 2 접속 단자를 범프 전극으로서 구성한다.The semiconductor integrated circuit of the present invention includes a predetermined basic function that is universal for a plurality of types of custom circuits, a common basic circuit having a common function, and a plurality of first connection terminals provided at predetermined positions in connection with the common basic circuit. An option circuit of a custom circuit portion containing various changes including a prescribed change, a function change, and a function corresponding to a predetermined portion of the common basic circuit, and a plurality of first connections of the option connection portion, on a mother chip portion having an optional connection portion included therein. The option chip in which the connection part containing the several 2nd connection terminal corresponding to each terminal was formed has the structure comprised by mounting the said 1st many connection terminal and many 2nd connection terminal correspondingly. Moreover, many 1st and 2nd connection terminals are comprised as bump electrode.

또한, 머더 칩과 옵션 사이에, 다수의 제 1 및 제 2 접속 단자의 인접하는 접속 단자 사이의 간극 확보용 머더 칩 및 옵션 칩에 가해지는 충격에 대한 강도 강화용 보호·완충층을 설치하여 구성되고, 또한, 머더 칩 및 옵션의 제 1, 제 2접속 단자 사이의 위치에 대응하는 얼라인먼트 수단을 설치하여 구성된다.In addition, between the mother chip and the option, a mother chip for securing the gap between adjacent connection terminals of the plurality of first and second connection terminals and a protective layer for strengthening strength against impacts applied to the option chip are provided. Moreover, it is comprised by providing the alignment means corresponding to the position between a mother chip and an optional 1st, 2nd connection terminal.

또한, 얼라인먼트 수단은 옵션 칩의 소정의 위치에 소정 간격으로 일렬로 배치된 소정 굵기의 다수의 제 1 얼라인먼트용 단자와, 이들 다수의 제 1 얼라인먼트용 단자 각각과 대응하는 머더 칩의 위치에 상기 다수의 제 1 얼라인먼트용 단자는 다른 굵기, 다른 간격으로 일렬로 배치된 다수의 제 2 얼라인먼트용 단자를 구비하여, 상기 다수의 제 1 및 제 2 얼라인먼트용 단자 각각의 대응하는 것끼리의 통전상태를 확인하여 얼라인먼트를 행하는 쇼트노기스 얼라인먼트 시스템으로 구성되고, 또한, 얼라인먼트 수단은, 머더 칩 및 옵션 칩 중의 한쪽에 설치된 선단이 끝이 가늘게 되도록 경사를 갖는 제 1 얼라인먼트용 단자와, 상기 머더 칩 및 옵션 칩 중의 다른쪽에 설치되고 상기 제 1 얼라인먼트용 단자를 삽입하는 삽입 구멍을 갖고 이 삽입 구멍이 개구부에서 넓게 되도록 한 경사를 갖는 제 2 얼라인먼트용 단자를 포함하는 셀프 얼라인먼트 구조로서 구성된다.Further, the alignment means includes a plurality of first alignment terminals having a predetermined thickness arranged in a line at predetermined intervals on the option chip, and the plurality of first alignment terminals at the mother chips corresponding to each of the plurality of first alignment terminals. The first alignment terminals of the plurality of terminals have a plurality of second alignment terminals arranged in a row at different thicknesses and at different intervals to check the energization state of the corresponding ones of the plurality of first and second alignment terminals. And a shortening alignment system configured to perform alignment, and the alignment means includes a first alignment terminal having an inclination such that a tip provided on one of the mother chip and the option chip is tapered, and the mother chip and the option chip. It is installed on the other side and has an insertion hole for inserting the first alignment terminal, and this insertion hole is an opening. Wide so that is configured as a self-alignment structure including a terminal for the second alignment that has a gradient in the.

또한, 머더 칩의 옵션 탑재부 부근에, 상기 옵션 탑재부에 옵션 칩이 탑재되지 않을 때에는 상기 머더 칩 개체로 이 머더 칩내의 공통 기본 회로가 갖는 기능을 달성하는 접속 상태로 하고, 상기 옵션 탑재부에 상기 옵션 칩이 탑재되어 있을때에는, 상기 공통 기본 회로 및 옵션 칩의 옵션 회로를 결합한 상태의 기능을 달성하는 접속 상태로 하는 접속 전환 회로를 설치하여 구성된다.When the option chip is not mounted on the option mounting unit near the option mounting unit of the mother chip, the mother chip unit is connected to achieve the function of the common basic circuit in the mother chip. When the chip is mounted, a connection switching circuit for providing a connection state that achieves the function of combining the common basic circuit and the option circuit of the option chip is provided.

제1도는 본 발명의 제 1 실시 형태를 나타내는 평면도 및 부분 확대 측면도.1 is a plan view and a partially enlarged side view showing a first embodiment of the present invention.

제2도는 본 발명의 제 2 실시 형태를 나타내는 옵션 칩을 탑재한 부분의 평면도 및 측면도.2 is a plan view and a side view of a portion on which an option chip according to a second embodiment of the present invention is mounted.

제3도는 본 발명의 제 3 실시 형태를 나타내는 쇼트노기스 얼라인먼트 부분의 원리 설명용 모식도 및 쇼트노기스부의 배치도.FIG. 3 is a schematic diagram for explaining the principle of a short noggin alignment portion showing a third embodiment of the present invention, and a layout view of the short noggins section.

제4도는 본 발명의 제 4 실시 형태를 나타내는 셀프 얼라인먼트 구조의 측면도 및 얼라인먼트 단자 부분의 확대 측면도.4 is a side view of a self-alignment structure and a magnified side view of the alignment terminal portion according to the fourth embodiment of the present invention.

제5도는 종래의 반도체 집적 회로의 제 1 예를 나타내는 평면도.5 is a plan view showing a first example of a conventional semiconductor integrated circuit.

제6도는 종래의 반도체 집적 회로의 제 2 예를 나타내는 평면도 및 부분 확대측면도.6 is a plan view and a partially enlarged side view showing a second example of a conventional semiconductor integrated circuit.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 머더 칩 2 : 옵션 칩1: Mother chip 2: Option chip

3 : 보호 완충층 10 : 집적 회로 칩3: protective buffer layer 10: integrated circuit chip

11, 11a : 공통 기본 회로 12 : 전극 패드11, 11a: common basic circuit 12: electrode pad

13 : 접속 전환 회로 14 : 범프 전극13 connection switching circuit 14 bump electrode

15 : 옵션 탑재부 16,17 : 얼라인먼트용 단자15: Option mounting part 16, 17: alignment terminal

20 : 커스텀 회로 21 : 범프 전극20: custom circuit 21: bump electrode

22 : 얼라인먼트용 단자 23x,23y : 쇼트노기스부22: alignment terminal 23x, 23y: short-nosed part

24 : 얼라인먼트용 단자 80 : 모듈 기판24: terminal for alignment 80: module board

31 : 전극 패드 32 : 배선31 electrode pad 32 wiring

33 : 전도성 접착제 40 : 칩33: conductive adhesive 40: chip

41 : 전극 패드 42 : 범프41: electrode pad 42: bump

다음에 본 발명의 실시의 형태에 대하여 도면을 참조하여 설명한다.EMBODIMENT OF THE INVENTION Next, embodiment of this invention is described with reference to drawings.

제1(a),(b)도는 본 발명의 제 1 실시의 형태를 예시하는 평면도 및 부분 확대 측면도이다.1 (a) and (b) are a plan view and a partially enlarged side view illustrating the first embodiment of the present invention.

이 제 1 실시 형태는 반도체 기판의 소정 영역에 다수 종류의 커스텀 회로에 대하여 범용성이 있는 소정의 기본 조작, 공통 기능을 구비한 공통 기본 회로(11), 이 공통 기본 회로(11)와 접속하여 상기 반도체 기판의 주변 부분에 설치된 다수의 전극 패드(12) 및 공통 기본 회로(11)와 접속하여 상기 반도체 기판의 소정 위치에 설치된 다수의 범프 전극(14)을 포함하는 옵션접속부(15)가 형성된 머더 칩(1)에, 공통 기본 회로(11)의 소정의 부분에 대응하는 규정 변경, 기능 변형, 기능 추가 등을 포함한 각종 변경을 담은 커스텀 회로 부분의 옵션 회로(도시 생략) 및 옵션 접속부(15)의 다수의 범프 전극(14) 각각과 대응하는 다수의 범프 전극(21)을 포함하는 접속부가 형성된 옵션 칩(2)을, 다수의 범프 전극(14)과 다수의 범프 전극(21)을 상호 대응 접속하여 탑재한 구성으로 되어 있다.This first embodiment is connected to a common basic circuit 11 having a predetermined basic operation and a common function that is versatile for a plurality of custom circuits in a predetermined region of a semiconductor substrate, and the common basic circuit 11 described above. Mother formed with the option connecting portion 15 including a plurality of electrode pads 12 provided on the periphery of the semiconductor substrate and the common basic circuit 11 and a plurality of bump electrodes 14 provided at a predetermined position of the semiconductor substrate. The option circuit (not shown) and the option connection part 15 of the custom circuit part in which the chip 1 contains various changes including regulation changes, function modifications, function additions, etc. corresponding to predetermined parts of the common basic circuit 11. A plurality of bump electrodes 14 and a plurality of bump electrodes 21 correspond to the option chip 2 having a connection portion including a plurality of bump electrodes 21 corresponding to each of the plurality of bump electrodes 14 of the plurality of bump electrodes 14. Sphere connected and mounted It is a.

또, 머더 칩(1)의 접속 전환 회로(13)는 옵션 칩(2)이 탑재되어 있지 않는 상태에서는 머더 칩(1) 개체로 소정의 기능을 달성하는 접속 상태가 되어 있고, 옵션 칩(2)이 탑재되어 있는 상태에서는, 옵션 칩(2)의 기능과 머더 칩(1)의 기능이 결합한 상태를 만들어낼 수 있는 접속 상태가 되도록, 접속 상태를 전환하는 기능을 가지고 있다. 또, 이 접속 상태의 전환은, 퓨즈 소자의 절단, 비절단에 의해 행할 수 있다.In addition, in the state in which the option chip 2 is not mounted, the connection switching circuit 13 of the mother chip 1 is in the connection state which achieves a predetermined function by the mother chip 1 individual, and the option chip 2 ) Has a function of switching the connection state such that the connection state can be created to form a state in which the function of the option chip 2 and the function of the mother chip 1 are combined. The connection state can be switched by cutting or not cutting the fuse element.

또한, 커스텀화는 공통 기본 회로(11)의 한정된 소정의 부분, 소정의 신호등에 대한 규정 변경, 기능 변경, 기능 추가 등이 많기 때문에, 이들 각종 변경에 대한 공통 기본 회로(11)와 옵션 칩(2)의 커스텀 회로 부분과의 사이에서 주고 받는 신호의 종류는 어느 정도 한정된다. 따라서, 옵션 탑재부(15) 및 옵션 칩(2)에 형성되는 범프 전극(14,21)의 수라든지 배치는 여러 종류의 커스텀 회로 부분(따라서 옵션 칩(2))에 대하여 공통으로 할 수 있다.Further, since the customization is often limited to a predetermined part of the common basic circuit 11, a change in regulations for a predetermined signal lamp, a function change, a function addition, and the like, the common basic circuit 11 and the option chip (for example) The types of signals exchanged with the custom circuit part of 2) are somewhat limited. Therefore, the number and arrangement of the bump electrodes 14 and 21 formed on the option mounting portion 15 and the option chip 2 can be common to various types of custom circuit portions (thus, the option chip 2).

머더 칩(1)은 여러 종류의 옵션 칩(2)에 대하여 공통이고, 더우기 접속 절단회로(13)에 의해서 단독으로 기능 확인, 검사 등이 가능하므로, 수주전에 미리 제작 및 검사를 해 둘 수 있다. 또한, 옵션 칩(2)의 종류도 한정되기 때문에, 이러한 종류의 옵션 칩(2)을 머더 칩(1)과는 다른 공정에서 미리 제작해 둘 수 있으며, 사용자의 요구에 따라서 제작이 끝난 옵션 칩(2)을 선택하여 머더 칩(1)에 탑재하고, 접속 전환 회로(13)에 의해 머더 칩(1)및 옵션 칩(2)간의 신호의 주고 받음을 가능하게 하며, 커스텀화된 반도체 집적 회로로 할 수 있다. 또한, 새로운 커스텀화라도, 옵션 칩(2)의 제작으로 대응할 수 있다. 따라서 수주에서 납품까지의 제조 기간을 종래의 제 1 예보다 대폭 단축할 수 있다. 또한, 옵션 칩(2)의 면적에 대한 제약이 작으므로, 커스텀화에 대한 적응 범위를 넓게 할 수 있다.The mother chip 1 is common to various types of option chips 2, and furthermore, since the function can be independently checked and inspected by the connection cutting circuit 13, the mother chip 1 can be manufactured and inspected in advance several weeks ago. . In addition, since the type of the option chip 2 is also limited, this kind of option chip 2 can be produced in advance in a process different from that of the mother chip 1, and the option chip which has been manufactured according to the user's request (2) is selected and mounted on the mother chip 1, and the connection switching circuit 13 enables the exchange of signals between the mother chip 1 and the option chip 2, and the customized semiconductor integrated circuit. You can do In addition, even new customization can be made by manufacturing the option chip 2. Therefore, the manufacturing period from order to delivery can be significantly shortened than the conventional first example. In addition, since the constraint on the area of the option chip 2 is small, it is possible to widen the adaptation range for customization.

또한, 머더 칩(1)의 옵션 탑재부(15)의 영역에도 공통 기본 회로(11)를 형성할 수 있으므로, 종래의 제 1 및 제 2의 예보다 집적도를 향상시킬 수 있고, 또한 소형화할 수 있다.In addition, since the common basic circuit 11 can be formed in the area of the option mounting unit 15 of the mother chip 1, the degree of integration can be improved and further downsized compared with the conventional first and second examples. .

제2(a),(b)도는 본 발명의 제 2 실시 형태를 나타내는 옵션 칩을 탑재한 부분의 평면도 및 측면도이다.2 (a) and 2 (b) are a plan view and a side view of a portion on which an option chip according to a second embodiment of the present invention is mounted.

이 제 2 실시 형태는 머더 칩(1)과 옵션 칩(2)의 사이에, 상호 접속하는 범프 전극(14,21)이, 인접하는 것끼리로 접촉하여 단락 사고를 일어나지 않도록 그 간극을 확보하기 위함과, 옵션 칩(2)이나 머더 칩(1)에 외부로부터 충격(힘)이 가해졌을 때에 이 옵션 칩(2) 및 머더 칩(1)이 파손되지 않도록 하기 위해서, 보호완충층(3)을 설치한 것이다.In this second embodiment, the gap between the mother chip 1 and the option chip 2 is secured so that the bump electrodes 14 and 21 to be interconnected are in contact with each other so as not to cause a short circuit accident. In order to prevent damage to the option chip 2 and the mother chip 1 when an impact (force) is applied to the option chip 2 or the mother chip 1 from the outside, the protective buffer layer 3 is provided. It is installed.

보호 완충층(3)은 옵션 칩(2) 및 머더 칩(1)의 적어도 한쪽에, (폴리)이미드·저 유전율 저 레지스트의 PGMA/PMMA 수지를 사용하여, 범프 전극을 노출하기 위해서 리소그래피 기술을 사용하여 형성한다.The protective buffer layer 3 uses a lithography technique to expose the bump electrodes on at least one of the option chip 2 and the mother chip 1 using PGMA / PMMA resin of (poly) imide low dielectric constant low resist. To form.

제3(a),(b)도는 본 발명의 제 3 실시 형태를 나타내는 쇼트노기스 얼라인먼트 부분의 원리 설명용 모식도 및 쇼트노기스부의 배치도이다.3 (a) and 3 (b) are schematic diagrams for explaining the principle of the short nozzle alignment part and the layout diagram of the short nozzle part of the third embodiment of the present invention.

미세화가 진전하여 인접하는 범프 전극(14,21)사이가 좁게 되면, 머더 칩(1)에 탑재하는 옵션 칩(2)의 탑재 위치 정밀도를 높게 할 필요가 있다. 또한, 머더 칩(1)과 옵션 칩(2)의 사이의 간격은 좁기 때문에, 서로 대응하는 범프 전극(14,21)이 정확한 위치에서 접속되어 있는지의 여부를 확인할 수 없다.When miniaturization advances and the adjacent bump electrodes 14 and 21 become narrow, it is necessary to make the mounting position precision of the option chip 2 mounted in the mother chip 1 high. In addition, since the distance between the mother chip 1 and the option chip 2 is small, it is not possible to confirm whether the bump electrodes 14 and 21 corresponding to each other are connected at the correct position.

그리하여, 노기스의 원리를 응용하여, 예를 들면 제3(a)도와 같은 사이즈로 다수의 얼라인먼트용 단자(16,22)를 머더 칩(1) 및 옵션 칩(2)에 배치한 다수의 쇼트노기스부(23x,23y)를 설치하여, 상호 대응하는 얼라인먼트용 단자(16,22)간의 통전이 있는지의 여부를 센서(4) 및 전원(E)에 의해 확인함으로써, 옵션 칩(2)의 정확한 탑재 위치를 결정한다. 대응하는 얼라인먼트용 단자간에서 전부에 통전이 있을 때, 정확한 위치가 된다.Thus, by applying the principle of Noggins, for example, a plurality of short-nose devices in which a plurality of alignment terminals 16 and 22 are arranged on the mother chip 1 and the option chip 2 in the same size as in FIG. 3 (a). Accurate mounting of the option chip 2 by providing sections 23x and 23y and confirming with the sensor 4 and the power supply E whether or not there is energization between the corresponding alignment terminals 16 and 22. Determine your location. When there is energization between all of the corresponding alignment terminals, the correct position is obtained.

얼라인먼트용 단자(16,22)는 그 높이를 범프 전극(14,21)에 의해 약간 높게하여, 대응하는 얼라인먼트용 단자(16,22)가 가볍게 접촉하는 상태에서는 범프 전극(14,21)은 접촉하지 않도록 해 두고 이들 사이의 통전을 확인하여, 정확한 위치가 결정되었을 때, 대응하는 얼라인먼트용 단자(16,22)를 강하게 접촉시킴으로써(다소의 변형은 문제 없다), 대응하는 범프 전극(14, 21)끼리를 접촉시킨다. 이렇게 함으로써, 정확한 위치에서 대응하는 범프 전극(14,21)끼리를 접속할 수 있다.The alignment terminals 16 and 22 are slightly raised in height by the bump electrodes 14 and 21, and the bump electrodes 14 and 21 are in contact with each other when the corresponding alignment terminals 16 and 22 are in light contact. The electric current between them is checked, and when the correct position is determined, the corresponding alignment terminals 16 and 22 are strongly contacted (some deformation is not a problem), so that the corresponding bump electrodes 14, 21 ) Touch each other. In this way, the corresponding bump electrodes 14 and 21 can be connected at the correct position.

제4(a),(b)도는 본 발명의 제 4 실시 형태를 나타내는 셀프 얼라인먼트 구조의 측면도 및 얼라인먼트용 단자 부분의 확대측면도이다.4 (a) and 4 (b) are side views of the self-alignment structure showing the fourth embodiment of the present invention and enlarged side views of the alignment terminal portion.

이 셀프얼라인먼트 구조는 옵션 칩(2)측에, 그 높이가 범프 전극(21)보다 높고, 선단이 끝이 가늘게 되도록 경사를 가지는 얼라인먼트용 단자(24)가 설치되고, 머더 칩(1)측에, 그 높이가 범프 전극(14)보다 높고, 얼라인먼트용 단자(24)를 삽입하는 삽입 구멍을 가지고 이 삽입 구멍이 개구부에서 넓어지도록 경사를 가지는 얼라인먼트용 단자(17)가 설치된 구성으로 되어 있다. 이러한 구조, 구성으로 함으로써 얼라인먼트용 단자(24)를 얼라인먼트용 단자(17)의 삽입 구멍에 삽입하기만 해도, 머더 칩(1) 및 옵션 칩(2)의 대응하는 위치를 정확히, 또한 용이하게 결정할 수 있다. 따라서, 이러한 얼라인먼트용 단자(17,24)를 다수 장소에 설치함으로써, 머더 칩(1)에 대한 옵션 칩(2)의 탑재 위치를 정확히, 또한 용이하게 결정할 수 있다.This self-alignment structure is provided on the option chip 2 side with an alignment terminal 24 having an inclination such that its height is higher than the bump electrode 21 and the tip is tapered, and on the mother chip 1 side. The alignment terminal 17 has a height higher than that of the bump electrode 14 and has an insertion hole for inserting the alignment terminal 24, and an alignment terminal 17 having an inclination such that the insertion hole widens in the opening portion is provided. With this structure and configuration, it is possible to accurately and easily determine the corresponding positions of the mother chip 1 and the option chip 2 only by inserting the alignment terminal 24 into the insertion hole of the alignment terminal 17. Can be. Therefore, by providing these alignment terminals 17 and 24 in many places, the mounting position of the option chip 2 with respect to the mother chip 1 can be determined correctly and easily.

또, 제 2 내지 제 4 실시 형태는 이들을 조합하여 적용할 수 있다. 또한, 옵션 칩(2) 및 대응하는 옵션 탑재부(15)는 하나에 한정되지 않고, 다수 설치하는 것도 가능하다.Moreover, 2nd-4th embodiment can be applied combining these. In addition, the option chip 2 and the corresponding option mounting part 15 are not limited to one, and many can be provided.

이상 설명한 바와 같이 본 발명은, 다수 종류의 커스텀회로에 대하여 범용성이 있는 기본 기능, 공통 기능을 구비한 공통 기본 회로, 및 옵션 접속부가 형성된 머더 칩과, 공통 기본 회로에 대한 각종 변경을 담아 넣은 옵션 회로 및 접속부가 형성된 옵션 칩을 따로 따로 제작하여, 옵션 칩을 머더 칩에 탑재하는 구성으로 함에 따라, 머더 칩 및 옵션 칩을 동시에 미리 제작해 둘 수 있고, 또한 새로운 옵션화라도 옵션 칩의 제작으로 대응할 수 있기 때문에, 수주로부터 납품까지의 제조기간을 단축할 수 있으며, 또한, 종래의 제 2 예와 같은 사용하지 않는 배선, 패드등은 없고, 옵션 탑재부에도 공통 기본 회로를 형성하여 2층 구조로 할 수 있으므로, 집적도가 향상되어 소형화할 수 있으며, 또한, 옵션 칩의 면적에 대한 제약이 작기 때문에, 커스텀화에 대한 적응 범위를 확대할 수 있는 효과가 있다.As described above, the present invention provides a multi-purpose basic function for a plurality of custom circuits, a common basic circuit having a common function, and a mother chip on which an optional connection part is formed, and an option containing various modifications to the common basic circuit. By making an option chip with a circuit and a connection part separately and mounting the option chip on the mother chip, the mother chip and the option chip can be manufactured at the same time in advance, and a new option can be produced by the option chip. In this way, the manufacturing period from order to delivery can be shortened, and there is no unused wiring and pads as in the conventional second example. As a result, the degree of integration can be improved and downsized, and since the constraint on the area of the option chip is small, it is possible to customize it. There is an effect that can extend the range of adaptation.

또한, 머더 칩과 옵션 칩의 사이에는 보호 완충층을 설치한 구성으로 함에 의해, 미세화가 진전하더라도 오류 접속이나 인접 단자간의 단락 사고의 발생 및 칩에 대한 충격, 스트레스 인가시의 칩의 파손을 방지할 수 있는 효과가 있어, 얼라인먼트 수단을 설치한 구성으로 하는 것에 의해, 미세화가 진전하더라도 옵션 칩을 머더 칩의 정확한 위치에 정확히 탑재할 수 있고 오류 접속, 단락 사고 등의 발생을 방지할 수 있는 효과가 있다.In addition, by providing a protective buffer layer between the mother chip and the option chip, even if miniaturization progresses, occurrence of a fault connection or a short circuit between adjacent terminals, damage to the chip during impact or stress application, can be prevented. It is possible to effectively mount the option chip at the exact position of the mother chip even if the miniaturization progresses, and to prevent the occurrence of an error connection or a short circuit accident. have.

Claims (6)

다수 종류의 커스텀 회로에 대하여 범용성이 있는 소정의 기본 기능, 공통 기능을 구비한 공통 기본 회로 및 이 공통 기본 회로와 접속하여 소정의 위치에 설치된 다수의 제 1 접속단자를 포함하는 옵션 접속부가 형성된 머더 칩과, 상기 공통 기본 회로의 소정 부분에 대한 규정 변경, 기능 변경, 기능 부가를 포함하는 각종 변경을 담아 넣은 커스텀 회로 부분의 옵션 회로 및 상기 옵션 접속부의 다수의 제 1 접속 단자 각각과 대응하는 다수의 제 2 접속 단자를 포함하는 접속부가 형성된 옵션 칩과, 상기 옵션 칩의 소정의 위치에 소정의 간격으로 일렬로 배치된 소정 굵기의 다수의 제 1 얼라인먼트용 단자와, 이들 다수의 제 1 얼라인먼트용 단자 각각과 대응하는 머더 칩의 위치에 상기 다수의 제 1 얼라인먼트용 단자와는 다른 굵기와 간격으로 일렬로 배치된 다수의 제 2 얼라인먼트용 단자를 포함한 얼라인먼트 수단을 구비하며, 상기 다수의 제 1 접속 단자 및 다수의 제 2 접속 단자를 대응 접속하여 상기 머더 칩에 상기 옵션 칩을 탑재하고, 상기 얼라이먼트 수단은 상기 다수의 제 1 및 제 2 얼라인먼트용 단자 각각의 대응하는 것끼리의 통전 상태를 확인하여 얼라인먼트를 행하는 쇼트노기스 얼라인먼트 시스템으로 구성한 반도체 집적 회로.A mother formed with an optional connection part including a predetermined basic function that is versatile for a large number of custom circuits, a common basic circuit having a common function, and a plurality of first connection terminals provided at a predetermined position in connection with the common basic circuit. A number corresponding to each of the plurality of first connection terminals of the option circuit of the custom circuit portion containing a chip, various changes including a regulation change, a function change, and a function addition to a predetermined portion of the common basic circuit; An option chip including a connection portion including a second connection terminal of the plurality of first alignment terminals, the plurality of first alignment terminals having a predetermined thickness arranged in a line at a predetermined interval on the option chip, and the plurality of first alignment portions Lines of mother chips corresponding to the terminals are arranged in a line with a thickness and an interval different from that of the plurality of first alignment terminals. And a plurality of alignment means including a plurality of second alignment terminals, wherein the option chip is mounted on the mother chip by correspondingly connecting the plurality of first connection terminals and the plurality of second connection terminals. A semiconductor integrated circuit comprising a short-noise alignment system for performing alignment by checking energization states of corresponding ones of a plurality of first and second alignment terminals. 제1항에 있어서, 상기 다수의 제 1 및 제 2 접속 단자를 범프 전극으로 하는 반도체 집적 회로.The semiconductor integrated circuit according to claim 1, wherein the plurality of first and second connection terminals are used as bump electrodes. 제1항에 있어서, 상기 머더 칩과 옵션 사이에, 다수의 제 1 및 제 2 접속 단자가 접속하는 접속 단자 사이의 간극 확보용 및 머더 칩 및 옵션 칩에 가해지는 충격에 대한 강도 강화용 보호·완충층을 설치한 반도체 집적 회로.The method according to claim 1, wherein the gap between the mother chip and the option is secured for securing a gap between the connection terminals to which the first and second connection terminals are connected, and the strength strengthening protection against impact applied to the mother chip and the option chip. Semiconductor integrated circuit provided with a buffer layer. 제1항에 있어서, 상기 머더 칩 및 옵션의 제 1, 제 2 접속 단자 사이의 위치에 대한 얼라인먼트 수단을 설치한 반도체 집적 회로.The semiconductor integrated circuit according to claim 1, wherein an alignment means for a position between said mother chip and optional first and second connection terminals is provided. 제4항에 있어서, 상기 얼라인먼트 수단은 머더 칩 및 옵션 칩 중의 한쪽에 설치된 선단이 앞이 가늘어지도록 경사를 갖는 제 1 얼라인먼트용 단자와, 상기 머더 칩 및 옵션 칩 중의 다른쪽에 설치되어 상기 제 1 얼라인먼트용 단자를 삽입하는 삽입 구멍을 갖고 이 삽입 구멍이 개구부에서 넓게 되도록 경사를 갖는 제 2 얼라인먼트용 단자를 포함하는 셀프 얼라인먼트 구조로 된 반도체 집적 회로.The said alignment means is a 1st alignment terminal which inclines so that the front end provided in one of a mother chip and an option chip may taper, and it is provided in the other of the said mother chip and an option chip, and the said 1st alignment A semiconductor integrated circuit having a self-alignment structure having an insertion hole for inserting a terminal for insertion and having a second alignment terminal inclined such that the insertion hole is wider in the opening portion. 제1항에 있어서, 상기 머더 칩의 옵션 탑재부 부근에, 상기 옵션 탑재부에 옵션 칩이 탑재되지 않을 때에는 상기 머더 칩 개체로 이 머더 칩내의 공통기본 회로가 갖는 기능을 달성하는 접속상태로 하여, 상기 옵션 탑재부에 상기 옵션 칩이 탑재되어 있을 때에는, 상기 공통 기본 회로 및 옵션 칩의 옵션 회로를 결합한 상태의 기능을 달성하는 접속 상태로 하는 접속 전환 회로를 설치한 반도체 집적 회로.The method according to claim 1, wherein when the option chip is not mounted near the option mounting portion of the mother chip, the mother chip object is connected to achieve the function of the common basic circuit in the mother chip. The semiconductor integrated circuit provided with the connection switching circuit which makes it the connection state which achieves the function of the state which combined the said common basic circuit and the option circuit of an option chip, when the said option chip is mounted in the option mounting part.
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