KR100271649B1 - Erase apparatus for flash memory cell - Google Patents

Abstract

PURPOSE: An eraser device of a flash memory cell is provided to maintain constantly an erasing efficiency by increasing an erasing voltage with the lapse of time. CONSTITUTION: The first power supply portion(20) erases data programmed in a floating gate of a flash memory cell by applying an eraser signal to an eraser gate during a predetermined time. The second power supply portion(21) provides electric power for verifying an erasing state of the floating gate of the flash memory cell. A sense amplifier(22) verifies the erasing state for the floating gate of the flash memory cell by using the electric power supplied from the second power supply(21).

Description

Eraser Device of Flash Memory Cell

The present invention relates to an ERASE device of a flash memory cell. In particular, the ERASE signal is applied by increasing the voltage level over time without fixing the ERASE signal level to a constant value. The present invention relates to an ERASE device of a flash memory cell that maintains a constant ERASE efficiency during the process.

FIG. 1 is a circuit diagram showing a configuration of an ERASE device of a conventional flash memory. As shown in FIG. 1, a predetermined level of power VEG10 is supplied to an erasure gate EG, thereby providing a flash memory cell. A first power supply unit 10 for erasing data programmed into the floating gate FG of FIG. 13; A second power supply unit (11) for applying a power supply (VCG10) for verifying an erasure (ERASE) state of the floating gate (FG) of the flash memory cell (13) to the control gate (CG); And a sense amplifier 12 for verifying an ERASE state of the floating gate FG of the cell by the verification power supply VCG10 of the second power supply 11. Will be described with reference to the waveform diagram of FIG.

First, the second power supply unit 11 supplies the power supply VCG10 to the control gate CG of the flash memory cell 13 to control the charge state of the floating gate FG to program data and erase the data. The first power supply unit ERASEs the data programmed in the floating gate FG, that is, the first power supply unit 10 flashes the flash memory cell 13. As shown in (a) of FIG. 2, an eraser signal VEG10 having a predetermined level is applied to the eraser gate EG of FIG. 2 to transfer data programmed to the floating gate FG of the flash memory cell 13. Erase.

At this time, the data programmed in the floating gate FG of the flash memory cell 13 is erased by the first pulse signal VEG10 in FIG. 2A of the first power supply 10. If not, the predefined voltage ▵ The erase pulse ERASE is performed by the second pulse signal VEG10 of FIG. 2A increased by V), and the sense amplifier 12 performs the floating gate FG of the flash memory cell 13. If the ERASE is not detected and the result of the sensing does not become the ERASE, the above process is repeated until the flash memory cell 13 is erased.

However, in the conventional apparatus operating as described above, since the amount of charge in the floating gate changes as the ERASE progresses, the electric field strength between the erasure gate and the floating gate becomes smaller, and thus the erasure is performed over time. (ERASE) There was a problem that the efficiency can get worse.

Therefore, the present invention devised in view of the above problems does not fix the ERASE voltage to a constant value and increases the voltage over time to maintain the constant ERASE efficiency while the voltage is applied. Its purpose is to provide an array storage value of a flash memory cell that can be used.

1 is a circuit diagram showing a configuration of an erasure device of a conventional flash memory cell.

2 is a timing diagram in FIG. 1;

Figure 3 is a circuit diagram showing the configuration of the erasure device of the flash memory cell of the present invention.

4 is a timing diagram in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a first power supply unit in FIG. 4; FIG.

Fig. 6 is an output waveform diagram of an erasing signal in Fig. 5;

FIG. 7 is a circuit diagram showing a configuration of a second power supply unit in FIG. 4; FIG.

FIG. 8 is a circuit diagram showing the configuration of a sense amplifier in FIG.

Fig. 9 is an output waveform diagram of an erasure signal with increased signal width in Fig. 4;

** Explanation of symbols for main parts of drawings **

20: first power supply 21: second power supply

22: sense amplifier 23: flash memory cell

The present invention for achieving the above object is a first power supply for erasing the data programmed in the floating gate of the flash memory cell by applying an eraser signal of which the level of the power is raised for a predetermined time to the eraser gate; ; A second power supply unit supplying power for verifying an erasure state of a floating gate of the flash memory cell; And a sense amplifier for verifying an erasure state of the floating gate of the cell by the verify power of the second power supply unit.

Hereinafter, the operation and effect of an embodiment of an ERASE device of a flash memory according to the present invention will be described with reference to the accompanying drawings.

Fig. 3 is a circuit diagram showing the structure of an ERASE device of the flash memory according to the present invention. As shown in this figure, an eraser signal VEG20 whose power level is increased for a predetermined time is provided to the eraser gate EG. A first power supply 20 for applying and erasing data programmed into the floating gate FG of the flash memory cell 23; A second power supply unit 21 for supplying a power supply VCC20 for verifying an ERASE state of the floating gate FG of the flash memory cell 23; And a sense amplifier 22 for verifying an eraser ERASE state of the floating gate FG of the flash memory cell 23 by the verification power supply VCG20 of the second power supply 21.

FIG. 5 is a circuit diagram showing the configuration of the first power supply unit 20. As shown in FIG. 5, a first NMOS transistor having a power supply voltage VOSER applied to a drain and an erasure command signal ERASECMD applied to a gate thereof. The source of N1) is connected to one side of the first resistor R, the other side of the first resistor R is connected to the other side of the capacitor C having one side grounded, and the connection point is connected to the gate. signal( ) Is connected to the drain of the applied second NMOS transistor N2, and the source of the second NMOS transistor N2 is grounded and an eraser command signal Is connected to the drain of the third NMOS transistor N3 applied to the gate to generate the signal VEG20 at the connection point.

FIG. 7 is a circuit diagram showing the configuration of the second power supply unit 21. As shown therein, a first NMOS transistor N4 to which a DC power source VDC is applied to a drain and a verification command signal VR is applied to a gate thereof. The source of the ) Is connected to the drain of the second n-MOS transistor N5 to which the signal is applied to generate the signal VCC.

FIG. 8 is a circuit diagram showing the configuration of the sense amplifier 22. As shown in FIG. 8, the drain and gate of the first PMOS transistor P1 to which the power supply voltage VDD is applied to the source are connected, and are generated at the connection point. The signal is applied to the drain of the flash memory cell 23, and the signal is inverted through the inverter IN1 to output the corresponding sensing signal SENCE OUT. The operation of the present invention configured as described above will be described. .

First, the general operation is the same as in the prior art. That is, the second power supply unit 21 supplies the power supply VCC20 to the control gate CG of the flash memory cell 23 to control the charge state of the floating gate FG to program data, and the first power supply. The supply unit 20 erases the data programmed in the floating gate FG, that is, the first power supply unit 20 is connected to the erasure gate EG of the flash memory cell 23 of FIG. 4. As shown in (a), the eraser signal VEG20 that increases with time is applied for a predetermined time to erase the programmed data in the floating gate FG of the flash memory cell 23.

In this case, in order to verify the erasure ERASE of the flash memory cell 23, when the second power supply 21 applies the verification voltage VCG20 as shown in FIG. 4B to the control gate CG, The sense amplifier 22 senses the verification result, and if the flash memory cell 23 is not erased, the erase pulse EG is reset to the second pulse signal VEG20 in FIG. By applying a voltage VEG20 that changes with time and is higher than the first pulse signal VEG20 as shown in FIG. 2, the operation is repeatedly performed until the flash memory cell 23 is erased. do.

Here, the internal operation of the first power supply unit 20 will be described.

The DC voltage VOSER is a DC voltage having the maximum voltage that can be supplied to the erasing gate EG, and the erasing command signal ERASECMD is higher than the DC voltage VOSER while the first and second enMOS transistors. The first resistor R and the capacitor C are very large and have a waveform that continuously rises during the operation time as shown in FIG. 6.

When the erasure command signal ERASECMD becomes a high potential when the ERASE operation is performed for the first time, the first and second NMOS transistors N1 and N2 are turned on and the voltage applied to the first node ( VC increases as shown in FIG. 6, and accordingly, the voltage VEG20 applied to the erasure gate EG of the flash memory cell 23 increases.

At this time, the voltage VEG20 applied to the erasure gate EG increases with time as shown in FIG. 6. If the erasure operation ERASE is terminated, the erasure command signal ERASECMD becomes low. When the first and second NMOS transistors N1 and N2 are turned off, the capacitor C maintains a current potential, while the third NMOS transistor N3 has a high potential erasure command bar. signal( Since it is turned on by (), low potential is applied to the erasure gate (EG).

That is, when the erasing operation ERASE ends and the erasing command signal ERASECMD becomes low potential, the capacitor C stores the current voltage level and the erasing gate EG is discharged to the ground voltage. Repeat this operation.

In addition, when verifying that the ERASE operation is completed, when the verification command signal VR is applied to the second power supply 21 at high potential, the fourth enMOS transistor N4 is turned on and the fifth enMOS transistor. Since N5 is turned off, a high potential is applied to the flash memory cell 23. At this time, if the floating gate FG is not erased, there is no potential difference so that no current flows in the flash memory cell 23. Accordingly, the first PMOS transistor P1 of the sense amplifier 22 is turned on by the low potential signal generated at the drain side of the flash memory cell 23 so that a high potential is applied to the inverter IN1. As a result, since the inverter IN1 inverts the high potential and outputs the low potential, the user may determine that the flash memory cell 23 is not an eraser.

In contrast, when the floating gate FG of the flash memory cell 23 is erased, the floating gate FG of the flash memory cell 23 is charged by the high potential verification signal VCC. Accordingly, since the high potential flowing through the first PMOS transistor P1 of the sense amplifier 22 is grounded through the flash memory cell 23, the inverter IN1 of the sense amplifier 22 receives a low potential signal. The input signal is inverted to output a high potential signal. Accordingly, when the output signal SENSE OUT of the sense amplifier 22 has a high potential, the user can know that the flash memory cell 23 is erased. .

As shown in Figs. 9A and 9B, the supply power VEG20 of the first power supply 20 is supplied by increasing the time by an integer multiple of the erase signal VEG for every erase operation. You can reduce the number of repetitions of the (ERASE) operation.

As described in detail above, the present invention provides a method for erasing the magnetic field strength between the erasing gate and the floating gate, in which electrons of the floating gate are released while the erasure operation is performed by the erasure signal. Compensation is made by increasing the voltage so that the ERASE efficiency can be kept constant while the voltage is applied.

Claims (6)

A first power supply unit applying an eraser signal having a raised power level to the eraser gate for a predetermined time to erase the data programmed in the floating gate of the flash memory cell; A second power supply for supplying power for verifying an eraser state for the floating gate of the flash memory cell; And a sense amplifier for verifying an erasing state of the floating gate of the flash memory cell by the verification power supply of the second power supply unit. The method of claim 1, wherein the first power supply unit is connected to one side of the first resistor and the other side of the first resistor connected to the source of the first NMOS transistor to which the power supply voltage is applied to the drain and the erase command signal is applied to the gate. Is connected to the other side of the grounded capacitor, the connection point is connected to the drain of the second NMOS transistor to which the Eraser Bar command signal is applied to the gate, and the source of the second NMOS transistor is grounded and the gate is And a drain of the third NMOS transistor, to which the erasure bar signal is applied to the gate, to generate a signal at the connection point thereof. The method according to claim 1 or 2, wherein the first power supply unit repeatedly applies the eraser signal to the eraser gate sequentially higher than the previously applied eraser signal until the flash memory cell is erased. Eraser device of flash memory cell. The method according to claim 1 or 2, wherein the first power supply unit applies an eraser signal of which the signal width is increased by a predetermined integer multiple times until the flash memory cell is erased to reduce the number of times of erasing operation of the eraser. Eraser device of a flash memory cell. 2. The second power supply of claim 1, wherein the second power supply unit receives the DC power to the drain and the source of the first NMOS transistor to which the verification command signal is applied to the gate, the source of which is grounded, and the verification command bar signal is applied to the gate. An erasing device for a flash memory cell, wherein the drain of the MOS transistor is connected to generate a signal at the connection point. 2. The sense amplifier of claim 1, wherein the sense amplifier is connected to a drain and a gate of a first PMOS transistor to which a power supply voltage is applied to a source, and applies a signal generated at the connection point to a drain of a flash memory cell. Eraser device of a flash memory cell, characterized in that configured to invert through to output the corresponding sensing signal.