KR100271624B1 - Peak current preventing circuit for memory cell - Google Patents

Peak current preventing circuit for memory cell Download PDF

Info

Publication number
KR100271624B1
KR100271624B1 KR1019970013798A KR19970013798A KR100271624B1 KR 100271624 B1 KR100271624 B1 KR 100271624B1 KR 1019970013798 A KR1019970013798 A KR 1019970013798A KR 19970013798 A KR19970013798 A KR 19970013798A KR 100271624 B1 KR100271624 B1 KR 100271624B1
Authority
KR
South Korea
Prior art keywords
address
sense amplifier
output
refresh
peak current
Prior art date
Application number
KR1019970013798A
Other languages
Korean (ko)
Other versions
KR19980076896A (en
Inventor
이일호
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970013798A priority Critical patent/KR100271624B1/en
Publication of KR19980076896A publication Critical patent/KR19980076896A/en
Application granted granted Critical
Publication of KR100271624B1 publication Critical patent/KR100271624B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A peak current prevention circuit is provided to prevent generation of a peak current by sequentially driving word lines within a given time period upon a refresh mode and by driving a sense amplifier to the same shape of a corresponding word line with some time difference with the word line. CONSTITUTION: A peak current prevention circuit includes an address latch(65) for coding/outputting an internal output address at a normal mode, coding an external output address and grouping/outputting them in a given time unit. Transfer gates(66A-66N) pass the output address of the address latch(65) in a normal mode, and transfer the output address of the address latch(65) to delays(67A-67N) in a refresh mode, based on a refresh signal(RF). Delays(67A-67N) delay the output address of the transfer gates(66A-66N) for a given time period in a refresh mode to output them to a row decoder for driving word lines and a controller for driving a sense amplifier.

Description

메모리셀의 피크 커런트 방지회로{PEAK CURRENT PREVENTING CIRCUIT FOR MEMORY CELL}Peak Current Prevention Circuit of Memory Cells {PEAK CURRENT PREVENTING CIRCUIT FOR MEMORY CELL}

본 발명은 메모리셀 어레이의 리플레쉬 기술에 관한 것으로, 특히 비트라인 센스앰프의 인에이블 시점에서 피크 커런트(peak current)가 발생되는 것을 방지하기 위하여, 워드라인을 소정의 단위 시간내에서 순차적으로 액티브시키도록한 메모리셀의 피크 커런트 방지회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refreshing technology of a memory cell array. In particular, in order to prevent peak current from occurring at an enable point of a bit line sense amplifier, the word lines are sequentially activated within a predetermined unit time. The present invention relates to a peak current prevention circuit of a memory cell.

도 1은 종래기술에 의한 메모리셀의 블록도로서 이에 도시한 바와 같이, 로우디코더(12A) 및 칼럼디코더(도면에 미표시)의 워드라인구동신호에 의해 구동되어 기 저장된 셀데이터를 센스앰프(13A)측으로 출력하거나 그 센스앰프(13A)를 통해 입력되는 데이터를 저장하는 메모리셀(11A)과; 비트라인을 통해 상기 메모리셀(11A)에 입출력되는 데이터를 소정 레벨로 증폭하는 비트라인 센스앰프(13A)와; 상기 비트라인 센스앰프(13A)의 구동을 제어하는 센스앰프 구동부(14A)로 하나의 메모리셀부(10A)가 구성되고, 이와 같은 메모리셀부(10B-10C)가 매트릭스형태로 다수개 구비되어 구성되었다.FIG. 1 is a block diagram of a memory cell according to the prior art. As shown in FIG. 1, the cell data driven by the word line driving signals of the row decoder 12A and the column decoder (not shown in the drawing) is stored in the sense amplifier 13A. A memory cell 11A for outputting data to or storing data inputted through the sense amplifier 13A; A bit line sense amplifier 13A for amplifying data input / output to the memory cell 11A through a bit line to a predetermined level; A memory cell unit 10A is configured as a sense amplifier driver 14A for controlling the driving of the bit line sense amplifier 13A, and a plurality of such memory cell units 10B-10C are provided in a matrix form. .

도 2는 도 1에서 센스앰프 구동부의 상세 블록도로서 이에 도시한 바와 같이, 외부로 부터 공급되는 어드레스(A0~An)를 완충증폭하는 어드레스버퍼(21)와; 리플레쉬신호(RF)의 제어를 받아 상기 어드레스버퍼(21)의 출력어드레스를 선택적으로 통과시키는 전송게이트(22A-22N)와; 카운트동작에 의해 어드레스를 발생하는 어드레스 카운터(23)와; 상기 어드레스 카운터(23)에서 출력되는 어드레스를 선택적으로 통과시키는 전송게이트(24A~24N)와; 상기 전송게이트(22A-22N)의 출력어드레스나 전송게이트(24A~24N)의 출력어드레스를 래치하여 코딩된 형태의 어드레스(AX0~ AXn),(AXb0~AXbn)를 발생하는 어드레스 래치부(25)와; 상기 어드레스(AX0~AXn), (AXb0~AXbn)에 따라 워드라인을 구동시키는 로우디코더(26)와; 상기 어드레스 래치부(25)로 부터 로우디코더(26)에 공급되는 어드레스(AX0~AXn),(AXb0~AXbn)를 소정 형식으로 지연처리하여 센스앰프인에이블신호[SE0~SEn], [SEb0~SEbn]를 발생하는 지연부(27)로 구성된 것으로, 이의 작용을 도 4 및 도 5를 참조하여 설명하면 다음과 같다.FIG. 2 is a detailed block diagram of the sense amplifier driver in FIG. 1, and an address buffer 21 for buffering and amplifying addresses A0 to An supplied from the outside as shown therein; Transmission gates 22A-22N for selectively passing an output address of the address buffer 21 under the control of a refresh signal RF; An address counter 23 for generating an address by a counting operation; Transfer gates 24A to 24N for selectively passing an address output from the address counter 23; The address latch section 25 for latching the output addresses of the transfer gates 22A to 22N or the output addresses of the transfer gates 24A to 24N to generate the coded addresses AX0 to AXn and AXb0 to AXbn. Wow; A row decoder 26 for driving a word line according to the addresses AX0 to AXn and AXb0 to AXbn; Delay processing the addresses AX0 to AXn and AXb0 to AXbn supplied from the address latch section 25 to the row decoder 26 in a predetermined format to sense sense enable signals [SE0 to SEn] and [SEb0 to It is composed of a delay unit 27 for generating the SEbn], the operation thereof will be described with reference to Figs.

데이터 리드모드에서 로우디코더(12A-12D)는 입력 어드레스(AX),(AXb)에 따라 워드라인(WL)을 선택적으로 구동시키고, 이에 따라 메모리셀(11A~11D)에서 리드되어 출력되는 데이터가 비트라인 센스앰프(13A~13D)에 의해 소정 레벨로 증폭된 후 외부로 출력되는데, 이때, 각 비트라인 센스앰프(13A~13D)는 센스앰프 구동부(14A~14D)에 의해 구동된다.In the data read mode, the low decoders 12A-12D selectively drive the word lines WL according to the input addresses AX and AXb, and thus data read and output from the memory cells 11A to 11D is output. The bit line sense amplifiers 13A to 13D are amplified to a predetermined level and then output to the outside. At this time, each of the bit line sense amplifiers 13A to 13D is driven by the sense amplifier drivers 14A to 14D.

상기 센스앰프 구동부(14A~14D)의 작용을 도 2를 참조하여 설명하면 다음과 같다.The operation of the sense amplifier driving units 14A to 14D will be described with reference to FIG. 2 as follows.

리플레쉬모드가 아닐 때에는 외부로 부터 공급되는 어드레스(A0~An)가 어드레스 버퍼(21) 및 전송게이트(22A~22N)를 통해 어드레스 래치부(25)에 래치되고, 리플레쉬모드에서는 리플레쉬신호(RF)가 액티브되므로, 이때, 어드레스 버퍼(21)에서 어드레스 래치부(25)측으로 전달되는 어드레스(A0~An)가 전송게이트(22A~22N)에 의해 차단되는 반면 어드레스 카운터(23)의 카운트동작에 의해 자체적으로 발생된 어드레스가 전송게이트(24A~24N)를 통해 그 어드레스 래치부(25)에 래치된다.When not in the refresh mode, the addresses A0 to An supplied from the outside are latched to the address latch unit 25 through the address buffer 21 and the transfer gates 22A to 22N. In the refresh mode, the refresh signal is used. Since the RF is active, at this time, the addresses A0 to An transferred from the address buffer 21 to the address latch section 25 are blocked by the transfer gates 22A to 22N while the count of the address counter 23 is reduced. The address generated by itself by the operation is latched to the address latch portion 25 via the transfer gates 24A to 24N.

또한, 상기 어드레스 래치부(25)는 입력 어드레스를 래치하여 코딩된 형태의 어드레스(AX0~AXn),(AXb0~AXbn)를 발생하게 되는데, 그 어드레스(AX0~AXn),(AXb0~AXbn)가 직접 로우 디코더(26)의 입력으로 제공되고, 다른 한편으로는 지연부(27)에 공급되어 이로부터 센스앰프인에이블신호[SE0~SEn], [SEb0~SEbn]가 출력된다. 도 3은 상기 어드레스 래치부(25)의 상세 회로도이다.In addition, the address latch unit 25 latches an input address to generate the coded addresses AX0 to AXn and AXb0 to AXbn, and the addresses AX0 to AXbn and AXb0 to AXbn. It is provided directly to the input of the row decoder 26, and on the other hand, it is supplied to the delay unit 27 to output the sense amplifier enable signals [SE0 to SEn] and [SEb0 to SEbn]. 3 is a detailed circuit diagram of the address latch unit 25.

한편, 도 4a 및 도 4b는 도 1에서 비트라인 센스앰프(13A-13D)의 구현예를 보인 상세 회로도로서 이의 작용을 도 5a 및 도 5b를 참조하여 설명하면 다음과 같다.4A and 4B are detailed circuit diagrams showing implementation examples of the bit line sense amplifiers 13A-13D in FIG. 1, which will be described below with reference to FIGS. 5A and 5B.

먼저, 도 4a에서, 노멀 리드동작시 비트라인 센스앰프(41A~41N)에 연결된 워드라인 중에서 소정의 워드라인이 액티브되면 해당 셀에서 리드된 데이터가 비트라인에 실리게 되는데, 예로써 비트라인(BL1),(BLb1)에 실린 경우 그 셀과 연결되지 않은 비트라인들은 등화상태를 유지한다.First, in FIG. 4A, when a predetermined word line is activated among the word lines connected to the bit line sense amplifiers 41A to 41N during the normal read operation, the data read from the corresponding cell is loaded on the bit line. When loaded on BL1) and BLb1, bit lines not connected to the cell maintain an equalization state.

이때, 엔모스(NM3) 및 피모스(PM3)의 게이트에 각기 공급되는 센스앰프 인에이블신호(SE0),(SEb0)는 도 5a에서와 같이 서로 상반된 위상을 갖는 신호로서 이들은 X디코더계의 신호이며, 그 중에서 상위 블록을 분할하는 코딩신호를 소정 시간동안 지연시켜 발생한 신호이다. 여기서, 소정의 지연시간이란 셀 데이터가 완전히 전달될 때까지의 시간을 의미하며, 이때, 센스앰프 인에이블신호(SE0),(SEb0)는 도 5a에서와 같이 각각 "하이", "로우"로 액티브된다.At this time, the sense amplifier enable signals SE0 and SEb0 respectively supplied to the gates of the NMOS N3 and the PMOS PM3 are signals having phases opposite to each other, as shown in FIG. 5A, which are signals of an X decoder system. Among them, a signal generated by delaying a coding signal for dividing an upper block for a predetermined time. Here, the predetermined delay time means a time until cell data is completely delivered. In this case, the sense amplifier enable signals SE0 and SEb0 are set to "high" and "low" as shown in FIG. 5A, respectively. Becomes active.

또한, 도 4b는 또 다른 셀블록에 대한 비트라인 센스앰프의 출력 예를 보인 것이다. 따라서, 코딩신호가 상기 도 4a의 비트라인 센스앰프(41A~41N)에 공급되고 있다면 도 4b의 비트라인 센스앰프(42A~42N)에는 공급되지 않을 것이며, 이때, 물론 센스앰프 인에이블신호(SE1),(SEb1)도 액티브되지 않을 것이다.4B shows an example of output of a bit line sense amplifier for another cell block. Therefore, if the coding signal is supplied to the bit line sense amplifiers 41A to 41N of FIG. 4A, the coding signal will not be supplied to the bit line sense amplifiers 42A to 42N of FIG. 4B, and of course, the sense amplifier enable signal SE1. (SEb1) will not be active either.

그러나, 리플레쉬모드가 될 때 전체적인 전류량을 줄이기 위하여 리플레쉬 단위를 16kbit→8kbit, 8kbit→4kbit로 변경하는 것이 가능하다. 즉, 일정한 시간내에 모든 메모리셀을 리플레쉬(워드라인 액티브) 시키기 위하여 16kbit 단위로 워드라인을 액티브시키지 않고 8kbit나 4kbit 단위로 워드라인을 액티브시켜 그 시간내에서 발생되는 전류량을 대폭적으로 줄일 수 있게 된다.However, in the refresh mode, it is possible to change the refresh unit from 16 kbit to 8 kbit and 8 kbit to 4 kbit to reduce the overall amount of current. In other words, in order to refresh all memory cells within a certain time period, the word lines are activated in 8kbit or 4kbit units instead of activating the wordlines in 16kbit units, thereby greatly reducing the amount of current generated in that time. do.

그런데, 상기와 같이 8kbit나 4kbit 단위로 워드라인을 액티브시켜 모든 셀을 리플레쉬시키기 위해서는 워드라인이 한 번 액티브될 때 수용되는 셀의 개수가 16kbit 단위로 워드라인을 액티브시킬때에 비하여 2배,4배로 증가되어 그만큼 피크전류치가 높아지게 된다. 이렇게 많이 늘어난 셀을 리플레쉬시키기 위해서는 도 4a,4b와 같이 구분해주던 코딩을 항상 같이 공급되게 해주어야 한다.However, in order to refresh all cells by activating the word line in 8kbit or 4kbit units as described above, the number of cells accommodated when the wordline is activated once is twice as large as when the wordline is activated in 16kbit units. It is increased by four times, and the peak current value increases accordingly. In order to refresh such a large number of cells, it is necessary to ensure that the coding coded as shown in FIGS. 4A and 4B is always supplied together.

다시말해서, 리플레쉬모드에서 센스앰프를 인에이블시킬 때 비교적 많은 전류를 소모하게 되며, 도 5a,5b는 그때의 피크전류 발생예를 보인 것이다.In other words, when the sense amplifier is enabled in the refresh mode, a relatively large amount of current is consumed, and FIGS. 5A and 5B show examples of peak currents generated at that time.

즉, 도 5a는 비교적 높은 피크전류를 발생하는 센스앰프 인에이블 동작을 예시적으로 보인 것으로, 이에 도시한 바와 같이 센스앰프 인에이블신호(SE0,SEb0), (SE1,SEb1)를 동시에 액티브시켜 전류(Isa)가 갑작스럽게 증가되었음을 알 수 있다.That is, FIG. 5A illustrates an example of a sense amplifier enable operation that generates a relatively high peak current. As shown in FIG. 5A, the sense amplifier enable signals SE0, SEb0 and SE1, SEb1 are simultaneously activated. It can be seen that (Isa) increased abruptly.

도 5b는 상기 도 5a의 단점을 해결하기 위한 종래기술의 다른 실시예를 보인 것으로, 이에 도시한 바와 같이 센스앰프 인에이블신호(SE0,SEb0),(SE1,SEb1)를 소정의 시차를 두고 액티브시켜 전류(Isa)가 분산되었음을 알 수 있다.FIG. 5B illustrates another embodiment of the related art for solving the disadvantages of FIG. 5A. As shown in FIG. 5B, the sense amplifier enable signals SE0 and SEb0 and SE1 and SEb1 are active with a predetermined time difference. It can be seen that the current Isa is dispersed.

이와 같이 종래의 메모리셀 제어회로에 있어서는 리플레쉬모드에서 센스앰프를 인에이블시킬 때 비교적 많은 전류를 소모하게 되며, 이를 방지하기 위해 각 센스앰프 인에이블신호를 소정의 시차를 두고 액티브시키는 기술이 제안되었으나, 이와 같이 하는 경우 센스앰프의 인에이블단계에서 비트라인에 미약한 셀 데이터가 실린상태이므로 노이즈에 의해 에러데이터가 발생되는 결함이 있었다.As described above, in the conventional memory cell control circuit, a relatively large current is consumed when the sense amplifier is enabled in the refresh mode, and a technique for activating each sense amplifier enable signal with a predetermined time difference is proposed to prevent this. However, in this case, since the weak cell data is loaded on the bit line in the enable step of the sense amplifier, there is a defect that error data is generated by noise.

따라서, 본 발명이 이루고자 하는 기술적 과제는 리플레쉬 모드시에 워드라인을 소정의 단위 시간내에서 순차적으로 구동시키고, 그 워드라인과 소정의 시차를 두고 센스앰프를 워드라인과 동일한 형태로 구동시켜 피크 전류의 발생을 방지하는 메모리셀의 피크 커런트 방지회로를 제공함에 있다.Accordingly, the technical problem to be achieved by the present invention is to drive the word lines sequentially within a predetermined unit time in the refresh mode, and to drive the sense amplifiers in the same form as the word lines with a predetermined time difference from the word lines. The present invention provides a peak current prevention circuit of a memory cell that prevents generation of current.

도 1은 종래기술에 의한 메모리셀의 블록도.1 is a block diagram of a memory cell according to the prior art.

도 2는 도 1에서 센스앰프 구동부의 상세 블록도.FIG. 2 is a detailed block diagram of the sense amplifier driver of FIG. 1. FIG.

도 3은 도 2에서 어드레스 래치부의 상세 회로도.3 is a detailed circuit diagram of an address latch unit in FIG. 2;

도 4a 및 도 4b는 도 1에서 비트라인 센스앰프의 상세 회로도.4A and 4B are detailed circuit diagrams of a bit line sense amplifier in FIG.

도 5a 및 5b는 도 4a 및 도 4b에서 센스앰프 인에이블신호의 파형도.5A and 5B are waveform diagrams of a sense amplifier enable signal in FIGS. 4A and 4B.

도 6은 본 발명에 의한 메모리셀의 피크 커런트 방지회로의 일실시 예시도.6 is an exemplary view of a peak current prevention circuit of a memory cell according to the present invention.

도 7은 도 6에서 블록화 처리된 후 지연출력되는 어드레스의 파형도.FIG. 7 is a waveform diagram of an address that is delayed after being blocked in FIG. 6; FIG.

도 8은 본 발명에 의한 워드라인 및 센스앰프 인에이블신호의 제어 타이밍도.8 is a control timing diagram of a word line and a sense amplifier enable signal according to the present invention;

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

61 : 어드레스 버퍼 62A~62N,64A~64N,66A~66N : 전송게이트61: Address buffer 62A to 62N, 64A to 64N, 66A to 66N: Transfer gate

63 : 어드레스 카운터 65 : 어드레스 래치부63 address counter 65 address latch unit

67A~67N : 지연기67A ~ 67N: Delay

도 6은 본 발명의 목적을 달성하기 위한 메모리셀의 피크 커런트 방지회로의 일실시 예시 블록도로서 이에 도시한 바와 같이, 외부로 부터 공급되는 어드레스(A0~An)를 완충증폭하는 어드레스 버퍼(61)와; 정상모드에서 리플레쉬신호(RF)의 제어를 받아 상기 어드레스버퍼(61)의 출력어드레스를 통과시키는 전송게이트(62A-62N)와; 리플레쉬모드에서 상기 리플레쉬신호(RF)의 제어를 받아 어드레스 카운터(63)에서 카운트되는 내부어드레스를 통과시키는 전송게이트(64A~64N)와; 정상모드에서는 상기 전송게이트(62A-62N)의 출력 어드레스를 코딩하여 출력하고, 리플레쉬모드에서는 상기 전송게이트(64A~64N)의 출력 어드레스를 코딩한 후 소정의 시간단위로 그룹화하여 출력하는 어드레스 래치부(65)와; 상기 리플레쉬신호(RF)의 제어를 받아 정상모드에서는 상기 어드레스 래치부(65)의 출력 어드레스를 그대로 통과시키고, 리플레쉬모드에서는 그 어드레스 래치부(65)의 출력 어드레스를 지연기(67A~67N)측으로 출력하는 전송게이트(66A~66N)와; 리플레쉬모드에서 상기 전송게이트(66A~66N)의 출력 어드레스를 소정 시간동안 지연시켜 워드라인 구동용 로우디코더 및 센스앰프 구동제어부측으로 출력하는 지연기(67A~67N)로 구성한 것으로, 이와 같이 구성한 본 발명의 작용 및 효과를 첨부한 도 7 및 도 8을 참조하여 상세히 설명하면 다음과 같다.FIG. 6 is an exemplary block diagram of a peak current prevention circuit of a memory cell for achieving the object of the present invention. As shown therein, an address buffer 61 for buffering and amplifying addresses A0 to An supplied from the outside. )Wow; Transmission gates 62A-62N passing through the output address of the address buffer 61 under the control of the refresh signal RF in the normal mode; Transmission gates 64A to 64N passing through the internal address counted by the address counter 63 under the control of the refresh signal RF in the refresh mode; In the normal mode, the address latches are coded to output the output addresses of the transfer gates 62A to 62N, and in the refresh mode, the address latches are coded to be output to the transfer gates 64A to 64N and grouped by a predetermined time unit. Section 65; Under the control of the refresh signal RF, the output address of the address latch unit 65 is passed as it is in the normal mode, and in the refresh mode, the output address of the address latch unit 65 is delayed 67A to 67N. Transmission gates 66A to 66N output to the < RTI ID = 0.0 > In the refresh mode, the output addresses of the transfer gates 66A to 66N are delayed for a predetermined time, and are configured as the low decoder for word line driving and the delayers 67A to 67N for outputting them to the sense amplifier drive control unit. When described in detail with reference to FIGS. 7 and 8 attached the operation and effect of the invention as follows.

정상모드에서 센스앰프 구동부의 작용은 종래기술에서와 동일하다. 즉, 외부로 부터 공급되는 어드레스(A0~An)가 어드레스 버퍼(61) 및 전송게이트(62A~62N)를 통해 어드레스 래치부(65)에 래치되고, 이로부터 코딩된 형태의 어드레스(AX0~AXn), (AXb0~AXbn)가 발생되며, 이때, 리플레쉬신호(RF)가 "로우"로 출력되므로 이에 의해 전송게이트(66B,66D,…)가 오프되는 반면 전송게이트(66A,66C,…)가 온되어 상기 어드레스(AX0~AXn),(AXb0~AXbn) 중 어드레스(AXn)는 직접, 나머지 어드레스는 각각의 전송게이트(66A,66C,…)를 통해 지연되지 않고 그대로 출력된다.The operation of the sense amplifier driver in the normal mode is the same as in the prior art. That is, the addresses A0 to An supplied from the outside are latched in the address latch unit 65 through the address buffer 61 and the transfer gates 62A to 62N, and the addresses AX0 to AXn having a coded form therefrom. ), (AXb0 to AXbn), and at this time, the refresh signal RF is output as "low", whereby the transfer gates 66B, 66D, ... are turned off while the transfer gates 66A, 66C, ... The address AXn of the addresses AX0 to AXn and AXb0 to AXbn is directly turned on and the remaining addresses are output without being delayed through the respective transfer gates 66A, 66C,...

그러나, 리플레쉬모드에서는 상기 리플레쉬신호(RF)가 "하이"로 출력되므로 이에 의해 전송게이트(62A~62N)가 오프되어 상기 외부로 부터 공급되는 어드레스(A0~An)가 차단되는 반면, 전송게이트(64A~64N)가 온되고, 이때, 어드레스 카운터(63)의 카운트동작에 의해 자체적으로 발생된 어드레스가 그 전송게이트(64A-64N)를 통해 그 어드레스 래치부(65)에 래치된다.However, in the refresh mode, the refresh signal RF is output as "high", whereby the transfer gates 62A to 62N are turned off to block the addresses A0 to An supplied from the outside, The gates 64A to 64N are turned on, and at this time, an address generated by the counting operation of the address counter 63 is latched to the address latch portion 65 via the transfer gates 64A to 64N.

이때, 리플레쉬신호(RF)가 도 7에서와 같이 "하이"로 출력되므로, 이에 의해 상기와 반대로 전송게이트(66B,66D,…)가 온되는 반면 전송게이트(66A,66C,…)가 오프되어 상기 어드레스(AX0~AXn),(AXb0~AXbn) 중 어드레스(AXn)는 직접, 나머지 어드레스는 각각의 전송게이트(66B,66D,…)를 통한 후 각각의 지연기(67A~67N)를 통해 도 7에서와 같이 지연되어 출력된다. 이때, 상기 어드레스(AX0~AXn),(AXb0~AXbn)는 다음단의 로우디코더에 공급되어 워드라인을 구동하기 위한 조합신호로 사용된다.At this time, since the refresh signal RF is output as " high " as shown in Fig. 7, the transfer gates 66B, 66D, ... are turned on, whereas the transfer gates 66A, 66C, ... are turned off. The addresses AXn of the addresses AX0 to AXn and AXb0 to AXbn are directly transmitted through the respective transfer gates 66B, 66D, ..., and then through the respective delayers 67A to 67N. The delay is output as shown in FIG. At this time, the addresses AX0 to AXn and AXb0 to AXbn are supplied to a row decoder of the next stage and used as a combination signal for driving a word line.

정상모드에서는 전체 워드라인을 두 블록의 워드라인으로 구분하여 구동시키기 위해 두 블록의 최상위 어드레스(AXn),(AXbn)를 출력하게 되는데, 리플레쉬모드에서는 상기 리플레쉬신호(RF)를 n번째 래치에만 입력시켜 두 블록의 구분이 없도록 하였다. 이와 마찬가지로, 상기 리플레쉬신호(RF)를 n-1번째 래치까지 입력시키는 경우, 정상모드에서 네 블록으로 구분되던 워드라인이 도 7에서와 같이 소정의 시차를 갖고 동시에 구동된다.In the normal mode, the highest address (AXn) and (AXbn) of the two blocks are output to drive the entire word line into two block word lines. In the refresh mode, the refresh signal RF is latched by the nth latch. Input only to prevent the separation of the two blocks. Similarly, when the refresh signal RF is inputted to the n-1 th latch, the word line divided into four blocks in the normal mode is simultaneously driven with a predetermined time difference as shown in FIG.

즉, 도 7에서와 같이 소정 시점에서 상기 최상위 어드레스(AXn)가 액티브되면 리플레쉬모드에서 동시에 액티브되던 최상위 어드레스(AXbn)는 지연기(67A)를 통해 Dn시간만큼 지연되어 출력되고, 어드레스(AXn-1)는 지연기(67B)를 통해 Dn+1시간만큼 지연되어 출력되며, 어드레스(AXbn-1)는 지연기(67C)를 통해 Dn+2시간만큼 지연되어 출력된다.That is, as shown in FIG. 7, when the most significant address AXn is activated at a predetermined point in time, the most significant address AXbn, which was simultaneously active in the refresh mode, is delayed for a Dn time and outputted through the delay 67A, and the address AXn. -1) is output by being delayed by Dn + 1 hour through the delayer 67B, and the address AXbn-1 is output by being delayed by Dn + 2 hours through the delayer 67C.

이에 따라 상기와 같이 지연출력되는 어드레스(AXn),(AXbn),(AXn-1), (AXbn-1)가 직접 로우디코더에 공급되어 이로부터 출력되는 워드라인구동신호(WL0~WL3)가 도 8에서와 같이 소정의 시차를 두고 순차적으로 액티브되고, 그 어드레스(AXn),(AXbn) ,(AXn-1),(AXbn-1)가 다른 한편으로는 별도의 지연과정을 통해 센스앰프인에이블신호[SE0~SE3]로 공급되므로 이들이 도 8에서와 같이 워드라인구동신호(WL0~WL3)가 액티브된 후 순차적으로 액티브되며, 이에 의해 각 비트라인(BL/BLb)의 전위가 도 8에서와 같은 상태로 천이된다.Accordingly, as described above, the delayed output addresses AXn, AXbn, AXn-1, and AXbn-1 are directly supplied to the low decoder, and the word line drive signals WL0 to WL3 output therefrom are shown in FIG. As shown in Fig. 8, they are sequentially activated with a predetermined time difference, and the addresses AXn, AXbn, AXn-1, and AXbn-1, on the other hand, enable the sense amplifier through a separate delay process. Since the signals SE0 to SE3 are supplied, they are sequentially activated after the word line driving signals WL0 to WL3 are activated, as shown in FIG. 8, whereby the potentials of the respective bit lines BL / BLb are different from those of FIG. 8. Transition to the same state.

이로 인하여 리플레쉬모드에서 센스앰프를 인에이블시킬 때 전류(Ip)가 도 8에서와 같이 흐르게 된다.As a result, the current Ip flows as shown in FIG. 8 when the sense amplifier is enabled in the refresh mode.

이상에서 상세히 설명한 바와 같이, 본 발명은 리플레쉬모드에서 코딩된 어드레스를 소정의 시간단위로 분할하여 그 단위 시간내에서 각 어드레스를 순차적으로 지연시켜 로우디코더의 입력으로 제공하고, 그 지연출력되는 어드레스에 추종하여 소정의 시차를 두고 센스앰프가 인에이블되게 함으로써, 리플레쉬모드에서 피크전류를 줄이고 데이터에러 발생을 방지할 수 있는 효과가 있다.As described above in detail, the present invention divides an address coded in a refresh mode into a predetermined time unit, sequentially delays each address within the unit time, and provides the delayed address to the input of the low decoder. By enabling the sense amplifier to follow a predetermined time difference and follow the above, there is an effect of reducing the peak current in the refresh mode and preventing the occurrence of data errors.

Claims (1)

리플레쉬 신호(RF)의 제어를 받아 정상모드에서는 외부로 부터 공급되는 어드레스를 입력받아 코딩하여 출력하고, 리플레쉬모드에서는 내부에서 발생되는 어드레스를 입력받아 코딩한 후 소정의 시간단위로 그룹화하여 출력하는 어드레스 래치부(65)와; 상기 리플레쉬신호(RF)의 제어를 받아 정상모드에서 상기 어드레스 래치부(65)의 출력 어드레스를 워드라인 구동용 로우디코더에 그대로 통과시키는 전송게이트(66A,66C,...), 리플레쉬모드에서는 상기 어드레스 래치부(65)의 출력 어드레스를 소정 시간동안 지연시켜 상기 워드라인 구동용 로우디코더에 출력하는 전송게이트(66B, 66D, ...) 및 지연기(67A~67N)와, 상기 워드라인 구동용 로우디코더에 입력되는 어드레스를 근거로 하여, 워드라인이 구동된 후 소정 시간이 경과될 때 해당 센스앰프의 인에이블신호를 순차적으로 출력하는 센스앰프 구동제어부로 구성한 것을 특징으로 하는 메모리셀의 피크 커런트 방지회로.Under normal control, the refresh signal RF is controlled to receive and code an address supplied from the outside. The refresh mode receives and codes an address generated internally. An address latch section 65; Transfer gates 66A, 66C, ..., refresh mode for passing the output address of the address latch unit 65 to the word line driving low decoder in the normal mode under the control of the refresh signal RF. Transfer delays 66B, 66D, ..., and delayers 67A to 67N for delaying the output address of the address latch unit 65 for a predetermined time and outputting them to the word line driving low decoder. A memory cell comprising a sense amplifier driving controller for sequentially outputting an enable signal of a corresponding sense amplifier based on an address input to a line driving low decoder after a word line is driven. Peak Current Prevention Circuit
KR1019970013798A 1997-04-15 1997-04-15 Peak current preventing circuit for memory cell KR100271624B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970013798A KR100271624B1 (en) 1997-04-15 1997-04-15 Peak current preventing circuit for memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970013798A KR100271624B1 (en) 1997-04-15 1997-04-15 Peak current preventing circuit for memory cell

Publications (2)

Publication Number Publication Date
KR19980076896A KR19980076896A (en) 1998-11-16
KR100271624B1 true KR100271624B1 (en) 2000-12-01

Family

ID=19502789

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970013798A KR100271624B1 (en) 1997-04-15 1997-04-15 Peak current preventing circuit for memory cell

Country Status (1)

Country Link
KR (1) KR100271624B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100656874B1 (en) * 2004-07-28 2006-12-12 엠시스랩 주식회사 High speed input display driver with reducing peak current and data input method using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644997A (en) * 1987-06-26 1989-01-10 Nippon Denki Office Syst Memory refresh control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644997A (en) * 1987-06-26 1989-01-10 Nippon Denki Office Syst Memory refresh control system

Also Published As

Publication number Publication date
KR19980076896A (en) 1998-11-16

Similar Documents

Publication Publication Date Title
US5155705A (en) Semiconductor memory device having flash write function
US5483497A (en) Semiconductor memory having a plurality of banks usable in a plurality of bank configurations
KR100253564B1 (en) Synchronous dram for high speed operation
US5717638A (en) Multi-port memory cells and memory with parallel data initialization
US5848006A (en) Redundant semiconductor memory device using a single now address decoder for driving both sub-wordlines and redundant sub-wordlines
US5544101A (en) Memory device having a latching multiplexer and a multiplexer block therefor
EP0260983B1 (en) Semiconductor memory device having shared bit lines
US6621753B2 (en) Semiconductor device
US5335206A (en) Semiconductor storage device
EP2166540B1 (en) Semiconductor memory
JP2739802B2 (en) Dynamic RAM device
KR100258539B1 (en) Static type semiconductor memory device
US5608688A (en) DRAM having output control circuit
US6229758B1 (en) Semiconductor memory device that can read out data faster than writing it
KR100604890B1 (en) Semiconductor device for initialization by the unit SRAMs
US20030156487A1 (en) Semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading
KR100271624B1 (en) Peak current preventing circuit for memory cell
US5701273A (en) Memory device
US6404693B1 (en) Integrated circuit memory devices that select sub-array blocks and input/output line pairs based on input/output bandwidth, and methods of controlling same
US5812464A (en) Column select signal control circuits and methods for integrated circuit memory devices
US7366822B2 (en) Semiconductor memory device capable of reading and writing data at the same time
KR100253354B1 (en) Operation testing apparatus for semiconductor memory
JP2004152476A (en) Semiconductor memory device improved in test performance
KR19990086671A (en) Memory Devices Performing Tests Using Sense Amplifiers
US6185132B1 (en) Sensing current reduction device for semiconductor memory device and method therefor

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100726

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee