KR100270703B1 - Method and apparatus for transmitting and receiving ethernet packet for usage of protocol and handshaking used in lan packet - Google Patents

Abstract

A method and apparatus for transmitting and receiving an Ethernet packet for a bus protocol and handshaking for handling a LAN packet are disclosed. The Ethernet packet transmission / reception method includes polling a MAC layer capable of transmitting / receiving by combining the states of a receive FIFO memory and a transmit FIFO memory of a plurality of MAC layers. Polling block), the control block performing an operation for receiving a packet at the MAC layer and generating control signals, a Receive Transfer receiving a packet from the MAC layers, to the MAC layer Performing operations for transmitting the packet and generating control signals, and transmitting the packet to the MAC layer.

Description

Method and apparatus for transmitting / receiving Ethernet packet for LAN packet bus protocol and handshaking

The present invention relates to a bus protocol for LAN packets and a method and apparatus for transmitting and receiving Ethernet packets for handshaking. In particular, the present invention relates to a bus interface that defines a protocol for packet transmission between the data link layer (MAC layer, Layer 2) for packet switching Ethernet packets. That is, the present invention relates to a circuit that implements a kind of packet bus for transmitting and receiving Ethernet packets in hardware, and is usefully used in the communication field, and is used to interface between a MAC layer block and a switching block for packet switching. do.

The MAC layer device developed by LSI Logic Co., Ltd. is a packet bus interface for transmitting Ethernet packets to reduce the number of pins of a chip package. It uses one bidirectional bus that is performed sequentially without holding.

However, since this MAC layer device cannot transmit and receive at the same time, when receiving a packet, such as half duplex mode, which is one mode of Ethernet packet transmission, transmission must wait until the reception is completed. The efficiency is reduced to about two.

In addition, since transmission and reception use a single bus in common, a series of arbitration logic is required to sequentially operate the same bus, thereby requiring an additional circuit, thereby reducing the reliability of the circuit.

In addition, the method of polling the FIFO status used in the MAC layer device serially checks the first-in, first-out state of each port in order to avoid an increase in the number of pins of the MAC layer chip due to the increase in the number of ports. I told you sequentially. Thus, the time for first-in first-out status polling increases accordingly.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to provide a bus protocol for LAN packets and an apparatus and method for handshaking. More specific objects of the present invention are:

First, it provides a new interface under the MAC layer and one-chip environment of software engine.

Second, all bandwidths for transmission and reception should be used.

Third, it implements a separate transmission and reception packet interface bus interface that can be used independently without the transmission and reception operations.

Fourth, the operation of transmitting and receiving is separately configured to reduce the size of the circuit to increase the reliability of the circuit.

Fifth, implement high speed packet transmission.

Other objects and advantages of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a block diagram of an Ethernet packet transceiver according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: RX BUS

20: TX BUS

30: Receive Control

40: Receive Transfer

50: polling block

60: transmit control

70: Transmit Transfer

An embodiment of the Ethernet packet transmission and reception method according to the present invention for achieving the above object is, the reception of the first-in first-out (receive FIFO) memory and the transmit first-in first-out (transmit FIFO) memory of a plurality of MAC layers (MAC Layer) Collecting the status and reporting a MAC layer capable of transmitting and receiving to a polling block; performing a control block for receiving a packet at the MAC layer and generating control signals; receiving transfer unit Receiving a packet from the MAC layers, performing a task to transmit a packet to the MAC layer and generating control signals, and sending a packet to the MAC layer. .

An embodiment of an Ethernet packet transceiver according to the present invention for achieving the above object is to collect the first-in, first-out memory for transmission and first-in, first-out memory for transmission from a plurality of MAC layers, and the dual disabled MAC layer A polling block for filtering, a reception control unit for controlling a reception operation for receiving a packet from the MAC layer, a reception transmission unit for receiving a packet from the MAC layers, a transmission control unit for controlling a transmission operation for transmitting a packet to the MAC layer, and And a transmission transmitter for transmitting the packet to the MAC layers.

Another preferred embodiment of the Ethernet packet transceiver according to the present invention is a polling block for collecting first-in, first-out memory state information received from a plurality of MAC layers, each MAC layer, and transmits and receives packets between the MAC layer and the polling block. A receiving service scheduler which receives a first-in first-out memory state collected by the polling block by a first switch engine, determines a MAC layer to perform a next receiving operation, and then transmits the determined MAC layer ID, collected by the polling block A transmission service scheduler that receives the first-in, first-out memory state for transmission, starts receiving according to the transmitted MAC layer ID, decodes the MAC layer ID so that the MAC layer of the ID has bus ownership, and reads in a bit vector format. Receive bus, SOP, EOP, byte-valid, MAC for creating enable signals and sending packets A second switch engine to which the information on the receive bus including the error and the MAC layer ID are transmitted, determines the MAC layer to perform a next transmission operation in the transmission service scheduler, and then transmits the determined MAC layer ID, and transmits the determined MAC layer ID. A transmit bus for writing a packet after decoding a MAC layer ID to generate a write enable signal in a bit vector format so that the MAC layer of the ID has bus ownership by starting a transmission operation according to an ID, and the second switch And a transmission transmitter for transmitting the transmission signal of the transmission bus including SOP, EOP, byte-valid and the FCS information calculated in the MAC layer receiving the packet based on the information obtained from the engine to the transmission bus. .

The polling block has a function of collecting the states of the first-in, first-out memory for transmission and reception between MAC layers and reporting MAC layers capable of receiving and transmitting operations, and the receiving controller controls the receiving operation as a whole. In addition, the reception transmission unit interfaces with the MAC layer reception bus to perform actual reception transmission. In addition, the transmission control unit controls the overall transmission operation. Finally, the transmission transmission unit interfaces with the MAC layer transmission bus so that actual transmission transmission is performed.

The present invention is a hardware protocol for transmitting / receiving frame-by-frame Ethernet packets, which is an interface interworking with the IEEE 802.3 frame format, a packet bus interface protocol of an MAC device ASIC, a packet bus interface protocol of an Ethernet switch device ASIC, and transmission / reception. To a high-speed packet bus or the like.

Hereinafter, with reference to the drawings will be described in detail the specific operation of the present invention.

1 is a block diagram of an Ethernet packet transceiver according to the present invention. In the apparatus of the present invention, the polling block is a (N-1) bit vector according to the ID of the MAC layer when the first-in, first-out memory for transmitting the N MAC layers is a signal indicating buffer avail. means for generating a (bit vector) signal, and generating a (N-1) bit vector signal according to the ID of the MAC layer when the first-in, first-out memory for N MAC layers is a signal indicating packet avail. By means of

In addition, the reception control unit may be a state machine means for creating a state of a reception operation and a means for decoding a MAC layer ID to generate a read enable signal of (N-1) bits for N MAC layers. Is done.

In addition, the transmission control unit generates a state machine means for creating a state from the start to the end of the transmission operation, and decodes the MAC layer ID to provide a write enable signal of (N-1) bits for the N MAC layers. It is made by means of making.

The packet transmission / reception method according to the present invention is as follows.

The polling block performs the following steps. In the case of receiving first-in, first-out memory, transmitting a signal from each MAC layer to a polling block by checking whether an efficient packet to be sent to the switch engine is greater than or equal to a certain threshold byte, and transmitting first-in first-out memory. If there is a free space to receive the packet sent from the switch engine, transmitting a signal from each MAC layer to the polling block, and collecting the first-in, first-out memory status information received from each MAC layer in the polling block And reporting the aggregated first-in, first-out memory status to a receiving service scheduler and reporting the aggregated first-in, first-out memory status to a transmission service scheduler. In addition, the reception controller performs the following steps. Perform.

Determining, by the receiving service scheduler, a MAC layer to perform a next reception operation and transmitting the determined MAC layer ID; and starting a reception operation according to the transmitted MAC layer ID so that the MAC layer of the ID may have bus ownership. Decoding the MAC layer ID so as to create a read enable signal in a bit vector format and transmitting a packet to a receive bus, and counting the number of words being transmitted by fixing a unit that can be transmitted by one MAC layer to 16 words The read enable signal remains set until 16, and resets the read enable to end the transfer in the case of an end of packet (EOP) or after the 16th word is transmitted. ).

In addition, the receiving transmitter performs the following steps.

Latching the packet transmitted from the receive bus to the 32-bit bus and passing it to the next block, the switch engine, and the MAC layer ID and information of the Rx bus such as SOP, EOP, byte-valid, MAC error, etc. Transfer to the switch engine block is a block.

In addition, the transmission service scheduler performs the following steps.

Determining, by the transmitting service scheduler, a MAC layer to perform a next transmission operation, and then transmitting the determined MAC layer ID, starting a transmission operation according to the transmitted MAC layer ID, so that the MAC layer of the ID may have bus ownership. Decoding the MAC layer ID to create a write enable signal in bit vector format and writing a packet to the transmit bus, fixing the number of words being transmitted by fixing the unit that one MAC layer can transmit to 16 words. It keeps the write enable signal set to 3 until the count is 16, and resets the write enable to terminate the transmission after the end of packet (EOP) or after transmitting the 16th word. .

Finally, the transmission transmitter performs the following steps.

When the switch engine transmits a packet, the packet is latched and transmitted on a 32-bit bus of a transmission bus, a transmission signal such as SOP, EOP, byte-valid, etc. is transmitted on the transmission bus, and the MAC layer receiving the packet is Calculate the FCS and make a signal based on the information that the switch engine tells you whether to add the signal and transmit it to the transmit bus.

The present invention can be variously modified and can take various forms and only the specific embodiments thereof are described in the detailed description of the invention. It is to be understood, however, that the present invention is not limited to the specific forms mentioned in the detailed description of the invention, but rather includes all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to do.

Such an effect of the present invention is to improve the bandwidth (bandwidth) from the existing 1.056 Gbps to 2.112 Gbps, it is possible to reduce the chip size by changing the control circuit with a simple logic. In addition, since a bandwidth wider than the bandwidth required for actual packet transmission can be secured, burst packet transfer is possible.

In addition, since the present invention has a hardware protocol for transmitting and receiving Ethernet packets (frame unit), an interface interworking with the IEEE 802.3 frame format, the packet bus interface protocol of the MAC device ASIC, the packet bus interface protocol of the Ethernet switch device ASIC, and the transmission and reception It can be used for the separated high speed packet bus.

Claims (11)

Collecting the states of a Receive FIFO memory and a Transmit FIFO memory of a plurality of MAC layers and reporting a MAC layer capable of transmitting and receiving to a Polling Block. ; A control block performing an operation for receiving a packet at the MAC layer and generating control signals; Receiving a packet from the MAC layers by a Receive Transfer; Performing a task to transmit a packet to the MAC layer and generating control signals; And And transmitting the packet to the MAC layer. The method of claim 1, wherein reporting the MAC layer to a polling block comprises: Receiving a first-in, first-out memory for receiving, from each MAC layer, information on whether an available packet to be transmitted to the switch engine is greater than or equal to a certain threshold byte; Receiving a first-in, first-out memory for transmitting, from each MAC layer, information on whether there is free space for receiving a packet sent from the switch engine; Collecting first-in, first-out memory state information received from each MAC layer; And reporting the aggregated incoming first-in, first-out memory status to a receive service scheduler, and reporting the aggregated first-in, first-out memory status to a transmission service scheduler. The method of claim 2, wherein the control block performs an operation for receiving a packet at the MAC layer and generates control signals. Determining, by the receiving service scheduler, a MAC layer to perform a next receiving operation and transmitting the determined MAC layer ID; Start receiving according to the transmitted MAC layer ID to decode the MAC layer ID so that the MAC layer of the ID has bus ownership, and create and transmit a lead enable signal in a bit vector format. Sending a packet to the bus; And The unit that can be transmitted by one MAC layer is fixed to 16 words, and the number of words being transmitted is counted to maintain the read enable signal as three until 16, and in case of EOP (End Of Packet). Or resetting the read enable to end the transmission after transmitting the 16th word. The method of claim 1, wherein the receiving transfer unit receives a packet from the MAC layers. Latching a packet transmitted from the receive bus to the 32-bit bus and delivering it to the next block, the switch engine; And And transmitting the information of the receiving bus including the SOP, EOP, byte-valid, MAC error, and MAC layer ID to the next block, the switch engine block. The method of claim 2, wherein the performing of the task of transmitting a packet to the MAC layer and generating control signals comprises: Determining, by the transmitting service scheduler, a MAC layer to perform a next transmission operation and transmitting the determined MAC layer ID; Starting a transmission operation according to the transmitted MAC layer ID to decode the MAC layer ID so that the MAC layer of the ID has bus ownership, creating a write enable signal in bit vector format, and writing a packet to a transmission bus; And By fixing the unit that can be transmitted by one MAC layer to 16 words, the number of words being transmitted is counted, and the write enable signal is maintained until 16, and in case of EOP (end of packet) or 16 Resetting the write enable to terminate the transmission after transmitting the first word. The method of claim 1, wherein transmitting a packet to the MAC layer comprises: Latching as the packet is transmitted by the switch engine and transmitting it on the 32-bit bus of the transmit bus; Transmitting a transmission signal including an SOP, an EOP, and a byte-valid on a transmission bus; And And a MAC layer receiving the packet, calculating a FCS, and generating a signal based on information that the switch engine informs whether to add the packet to the transmit bus. A polling block for collecting the first-in first-out memory and the first-in first-out memory states for receiving from the plurality of MAC layers, and filtering the dual disabled MAC layers; A reception control unit controlling a reception operation for receiving a packet from a MAC layer; A reception transmitter for receiving a packet from MAC layers; A transmission control unit controlling a transmission operation for transmitting a packet to a MAC layer; And An Ethernet packet transceiver comprising a transmission transmitter for transmitting a packet to MAC layers. 8. The method of claim 7, wherein the polling block comprises: means for generating a (N-1) bit vector signal according to the ID of the MAC layer when the first-in, first-out memory for the N MAC layers is a signal indicating buffer utilization; And means for generating an (N-1) bit vector signal in accordance with the ID of the MAC layer when the reception first-in-first-out memory for the MAC layer is a signal indicating packet avail. The method of claim 7, wherein the receiving control unit, State machine means for creating a state from start to end of a receive operation; And And means for decoding the MAC layer ID to generate a read enable signal of (N-1) bits for the N MAC layers. The method of claim 7, wherein the transmission control unit, State machine means for creating a state from the start to the end of the transfer operation; And And means for decoding the MAC layer ID to generate a write enable signal of (N-1) bits for the N MAC layers. Multiple MAC layers; A polling block for collecting first-in, first-out memory state information received from each MAC layer; A first switch engine for transmitting and receiving a packet between the MAC layer and the polling block; A reception service scheduler which receives a first-in first-out memory state collected by the polling block, determines a MAC layer to perform a next reception operation, and then transmits the determined MAC layer ID; A transmission service scheduler for receiving a first-in, first-out memory state collected by the polling block; A receiving bus for starting a receiving operation according to the transmitted MAC layer ID to decode the MAC layer ID to generate a read enable signal in a bit vector format and to transmit a packet so that the MAC layer of the ID has bus ownership; A second switch engine to which information on the receive bus and MAC layer ID including SOP, EOP, byte-valid, and MAC error are delivered; After determining the MAC layer to perform the next transmission operation in the transmission service scheduler and transmits the determined MAC layer ID, and starts the transmission operation according to the transmitted MAC layer ID so that the MAC layer of the ID can have bus ownership A transmit bus for decoding the layer ID to produce a write enable signal in bit vector format and then to write the packet; And Transmission transmission for transmitting the transmission signal of the transmission bus including the FCS information and SOP, EOP, byte-valid calculated in the MAC layer receiving the packet based on the information obtained from the second switch engine to the transmission bus An Ethernet packet transceiver comprising a unit.