KR100270611B1 - Method for electrostatic thermal bonding of semiconductor substrate - Google Patents
Method for electrostatic thermal bonding of semiconductor substrate Download PDFInfo
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- KR100270611B1 KR100270611B1 KR1019970046677A KR19970046677A KR100270611B1 KR 100270611 B1 KR100270611 B1 KR 100270611B1 KR 1019970046677 A KR1019970046677 A KR 1019970046677A KR 19970046677 A KR19970046677 A KR 19970046677A KR 100270611 B1 KR100270611 B1 KR 100270611B1
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- 239000000758 substrate Substances 0.000 title claims abstract description 123
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000011521 glass Substances 0.000 claims abstract description 46
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000008367 deionised water Substances 0.000 claims abstract description 7
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 7
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 17
- 238000001035 drying Methods 0.000 claims description 14
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 9
- 238000005406 washing Methods 0.000 claims description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 238000000643 oven drying Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 238000000427 thin-film deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000000243 solution Substances 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 239000011259 mixed solution Substances 0.000 abstract 1
- 150000002978 peroxides Chemical class 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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Abstract
Description
본 발명은 반도체기판의 정전 열 접합방법에 관한 것으로, 특히 친수화처리를 통해 유리기판과 또는 유리가 증착된 실리콘기판과 실리콘기판을 낮은 온도 및 낮은 전압 하에서 접합시키는데 적당하도록 한 반도체기판의 정전 열 접합방법에 관한 것이다.BACKGROUND OF THE
일반적으로, 강한 전계에 의한 전자의 이동으로 전도가 이루어져 전자가 발광부에 충돌함으로써 소정의 표시를 하는 필드 에미션 디스플레이(field emission display) 등의 전계 방출 표시소자를 제조하기 위해서는 10-6torr이하의 고진공이 필요하다. 종래의 음극선관 기술을 사용하면 배기용 세관이 봉해지는 순간 발생한 가스로 인해 진공도가 나빠지게 되며, 이로 인해 동작수명은 감소한다. 이와 같은 문제점을 해결하기 위해 1969년 피. 알. 말로이(P.R.MALLOY)사의 다니엘 아이 포메란즈(DANIEL I. POMERANTZ)에 의해 세상에 알려지게 된 실리콘과 유리를 접합하는 기술이 사용되고 있다.In general, in order to manufacture a field emission display device such as a field emission display in which conduction is caused by the movement of electrons by a strong electric field and electrons collide with the light emitting part to display a predetermined value, it is 10 -6 torr or less High vacuum is required. Using the conventional cathode ray tube technology, the degree of vacuum is deteriorated due to the gas generated when the exhaust capillary is sealed, thereby reducing the operating life. 1969 to solve this problem. egg. The technology of bonding silicon and glass, known to the world by Daniel I. POMERANTZ of PLMALLOY, is used.
이와 같이 실리콘과 유리를 접합하는 방법은 직접접합과 정전 열접합이 주로 사용되며, 정전 열 접합을 이용하여 실리콘기판과 유리기판을 접합하는 필드 어시스트 본딩(field assisted bonding) 또는 애노딕 본딩(anodic bonding)을 사용하고 있다.As a method of bonding silicon and glass, direct bonding and electrostatic thermal bonding are mainly used, and field assisted bonding or anodical bonding for bonding a silicon substrate and a glass substrate using an electrostatic thermal bonding. ) Is used.
특히 정전 열 접합방법은 직접접합 방법에 비해 낮은 온도에서 친수화를 위한 약품의 처리 없이 접합이 가능하여 마이크로 머시닝, 실리콘 온 인슐레이터(SOI) 등의 분야에 사용되고 있다.In particular, the electrostatic thermal bonding method is used in the field of micromachining, silicon on insulator (SOI) and the like because it can be bonded without a chemical treatment for hydrophilization at a lower temperature than the direct bonding method.
그리고, 전계 방출 표시소자의 응용에 있어서는 실리콘기판과 유리기판 사이의 정전 열 접합을 이용하여 소자의 지지대로 이용하고 있으며, 정전 열 접합을 이용한 반도체 소자의 이용에 있어서는 가능한 소자에 가해질 손상을 줄이기 위해서 저온, 저전압 조건의 접합이 요구된다.In application of the field emission display device, electrostatic thermal bonding between a silicon substrate and a glass substrate is used as a support of the device, and in the use of a semiconductor device using electrostatic thermal bonding, in order to reduce damage to the device as much as possible. Low temperature, low voltage bonding is required.
도1은 일반적인 정전 열 접합장치의 구성도로서, 이에 도시한 바와 같이 상호 접촉된 유리기판(1)과 실리콘기판(2)에 전원을 공급하고, 그 상태를 기록하는 전원공급 및 기록부(3)와; 온도 조절부(4)의 제어를 받아 상기 상호 접촉된 유리기판(1)과 실리콘기판(2)에 열을 인가하는 가열부(5)로 구성되며, 이와 같이 유리기판(1)과 실리콘기판(2)을 접촉시키고, 유리기판(1)측이 음극, 실리콘기판(2)측이 양극이 되도록 높은 전압을 인가하여, 유리기판(1)과 실리콘기판(2)사이에 정전력이 발생하도록 하고, 실리콘기판(2)의 하부를 높은 온도로 가열하여 유리기판(1)과 실리콘기판(2)간에 영구적인 접합이 일어나도록 한다.1 is a configuration diagram of a general electrostatic thermal bonding apparatus, and as shown therein, a power supply and
상기한 바와 같이 종래의 정전 열 접합방법은 높은 처리 온도와 고전압을 필요로 하기 때문에 제조비용이 증가하고, 접합면적이 국부적이고 접합강도에 있어서도 제품의 응용에는 불안정한 문제점이 있었다.As described above, the conventional electrostatic thermal bonding method requires a high processing temperature and a high voltage, thereby increasing the manufacturing cost, having a localized bonding area, and unstable application of the product even in bonding strength.
이와 같은 문제점을 감안한 본 발명은 종래에 비해 낮은 처리 온도와 저전압을 인가하여, 넓은 접합면적과 강한 접합력을 갖는 반도체기판의 정전 열 접합방법의 제공에 그 목적이 있다.In view of the above problems, the present invention has an object of providing a method for electrostatic thermal bonding of a semiconductor substrate having a large bonding area and a strong bonding force by applying a lower processing temperature and a lower voltage than in the related art.
도1은 일반적인 정전 열 접합장치의 구조도.1 is a structural diagram of a general electrostatic thermal bonding apparatus.
도2는 본 발명 반도체기판의 정전 열 접합공정 순서도.Figure 2 is a flow chart of the electrostatic thermal bonding process of the semiconductor substrate of the present invention.
도3은 본 발명에 의한 유리-실리콘기판간의 접합부위를 촬영한 사진.Figure 3 is a photograph of the junction between the glass-silicon substrate according to the present invention.
도4는 도3을 반으로 절단한 후, 그 단면을 촬영한 단면 주사 전자현미경 사진.Fig. 4 is a cross-sectional scanning electron microscope photograph of the cross section taken after cutting Fig. 3 in half.
도5는 실리콘 기판을 식각한 후, 전압을 인가하여 접합한 시료의 주사 현미경 사진.Fig. 5 is a scanning micrograph of a sample bonded after etching a silicon substrate and applying a voltage.
상기와 같은 본 발명의 목적은 유리기판과 반도체기판을 세척하는 기판세척단계와; 상기 두 기판을 소정온도로 가열된 친수화용액에 수 분 동안 두어 친수화처리 하는 친수화 처리단계와; 상기 친수화 처리단계를 통해 친수화된 두 기판을 건조하는 건조단계와; 상기 건조된 기판을 직접접합하는 초기 직접접합단계와; 상기 직접접합된 기판을 오븐에 넣고 건조시키는 오븐건조단계와; 상기 직접접합된 기판에 소정의 전압과 열을 인가하여 정전 열 접합시키는 정전 열 접합단계로 구성함으로써 달성되는 것으로 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is a substrate washing step of washing the glass substrate and the semiconductor substrate; A hydrophilization treatment step of placing the two substrates in a hydrophilic solution heated to a predetermined temperature for a few minutes to hydrophilize; A drying step of drying the two hydrophilized substrates through the hydrophilization treatment step; An initial direct bonding step of directly bonding the dried substrate; An oven drying step of drying the directly bonded substrate in an oven; The present invention will be described in detail with reference to the accompanying drawings, which is achieved by the electrostatic heat bonding step of applying a predetermined voltage and heat to the directly bonded substrate to electrostatic heat bonding.
도2는 본 발명 반도체기판의 정전 열 접합방법의 순서도로서, 이에 도시한 바와 같이 유리기판과 반도체기판을 세척하는 기판세척단계와; 상기 두 기판을 친수화처리 하는 친수화 처리단계와; 상기 친수화 처리단계를 통해 친수화된 두 기판을 건조하는 건조단계와; 상기 건조된 기판을 직접접합하는 초기 직접접합단계와; 상기 직접접합된 기판을 오븐에 넣고 건조시키는 오븐건조단계와; 상기 직접접합된 기판에 소정의 전압과 열을 인가하여 정전 열 접합시키는 정전 열 접합단계로 이루어진다.Figure 2 is a flow chart of the electrostatic thermal bonding method of the semiconductor substrate of the present invention, the substrate washing step of washing the glass substrate and the semiconductor substrate as shown therein; A hydrophilization treatment step of hydrophilizing the two substrates; A drying step of drying the two hydrophilized substrates through the hydrophilization treatment step; An initial direct bonding step of directly bonding the dried substrate; An oven drying step of drying the directly bonded substrate in an oven; Electrostatic thermal bonding step of applying a predetermined voltage and heat to the directly bonded substrate electrostatic thermal bonding step.
상기 반도체기판은 유리기판의 상부에 실리콘박막을 증착한 기판을 사용하여도 상기의 방법과 동일한 단계를 거처 정전 열 접합을 실시하게 되며, 유리기판이 실리콘기판의 상부에 증착된 경우도 동일한 방법으로 정전 열 접합을 실시한다.The semiconductor substrate is subjected to the electrostatic thermal bonding through the same steps as the above method even when a silicon thin film is deposited on the glass substrate, and the same method is used when the glass substrate is deposited on the silicon substrate. Perform electrostatic thermal bonding.
이하, 상기와 같이 구성된 본 발명을 실시예를 통해 좀더 상세히 설명한다.Hereinafter, the present invention configured as described above will be described in more detail with reference to Examples.
먼저, 직경이 1인치인 n형 (100)방향의 실리콘기판과 직경이 1인치인 코닝유리(CORNING GLASS #7740)기판을 아세톤과 메탄올 그리고 탈이온수(D.I. WATER)를 사용하여 세척한다.First, the silicon substrate in the n-type (100) direction of 1 inch diameter and the Corning Glass (CORNING GLASS # 7740) substrate of 1 inch in diameter are washed with acetone, methanol, and deionized water (D.I. WATER).
그 다음, 세척이 완료된 실리콘기판과 유리기판을 친수화용액에 수분동안 담그고 45-100℃로 가열한다. 이때의 친수화 용액은 암모니아와 과산화수소 및 탈이온수를 4: 1: 6의 비로 혼합한 것을 사용한다.Then, the washed silicon substrate and the glass substrate are immersed in a hydrophilic solution for a few minutes and heated to 45-100 ℃. At this time, the hydrophilized solution is a mixture of ammonia, hydrogen peroxide and deionized water in a ratio of 4: 1: 6.
그 다음, 친수화 처리가 완료된 실리콘기판과 유리기판을 건조시키고, 초기접합을 실시한다. 초기접합은 불순물, 오염물이나 기판 자체의 결함에 매우 민감하기 때문에 각각의 공정시 매우 주의 하여야 한다. 만약 결함이 있다면 접합은 이루어지지 않게 된다.Then, the silicon substrate and the glass substrate on which the hydrophilization treatment is completed are dried, and initial bonding is performed. Initial bonding is very sensitive to impurities, contaminants or defects in the substrate itself, so care must be taken in each process. If there is a defect, no bonding occurs.
그 다음, 초기접합된 두 기판을 100~200℃의 오븐에서 24시간동안 보관하여 두 기판 사이에 남아 있는 수분을 완전히 제거한다. 만약 수분이 존재하면 정전 열 접합시 주어지는 온도에 의해 수분이 증기가 되면서 발생하는 가스로 인해 접합이 떨어지게 된다.Then, the two bonded substrates are stored for 24 hours in an oven at 100-200 ° C. to completely remove moisture remaining between the two substrates. If moisture is present, the junction will fall off due to the gas generated as the vapor becomes moisture by the temperature given during electrostatic thermal bonding.
그 다음, 오븐에서 완전히 건조된 초기 접합된 두 기판을 상기 도1의 장치를 이용하여 정전 열 접합을 실시한다. 이때 인가하는 전압의 범위는 50~700V로 하고, 온도는 100~500℃로 한다.Then, the first bonded two substrates completely dried in the oven is subjected to electrostatic thermal bonding using the apparatus of FIG. At this time, the range of voltage to be applied is 50 ~ 700V, the temperature is 100 ~ 500 ℃.
또한 상기 반도체기판은 실리콘 또는 ITO(INDIUM TIN OXIDE)가 코팅된 유리기판을 사용하며, ITO가 코팅된 유리기판간의 정전 열 접합방법은 일측 ITO코팅 유리기판의 일측에 ITO, 알루미늄, 티타늄, 크롬 또는 몰리브덴을 증착하고, 타측 ITO코팅 유리기판에 유리박막을 증착한 후 친수화처리를 거쳐 접합하게 된다.In addition, the semiconductor substrate uses a glass substrate coated with silicon or ITO (INDIUM TIN OXIDE), and the electrostatic thermal bonding method between the ITO coated glass substrate is ITO, aluminum, titanium, chromium or ITO on one side of the ITO coated glass substrate. Molybdenum is deposited, and a glass thin film is deposited on the other ITO-coated glass substrate, and then bonded through a hydrophilic treatment.
이를 좀더 상세히 설명하면, ITO(INDIUM TIN OXIDE)코팅 유리기판을 세척하는 기판세척단계와; 일측 ITO코팅 유리기판의 상부에 금속박막을 증착하고, 타측 ITO코팅 유리기판의 상부에 유리박막을 증착하는 증착단계와; 상기 금속박막 및 유리박막이 증착된 두 기판을 소정온도로 가열된 친수화용액에 수 분 동안 두어 친수화처리 하는 친수화 처리단계와; 상기 친수화 처리단계를 통해 친수화된 두 기판을 건조하는 건조단계와; 상기 건조된 기판을 직접접합하는 초기 직접접합단계와; 상기 직접접합된 기판을 오븐에 넣고 건조시키는 오븐건조단계와; 상기 직접접합된 기판에 소정의 전압과 열을 인가하여 정전 열 접합시키는 정전 열 접합단계로 이루어져 접합이 용이하지 않은 두 유리기판을 접합시키게 된다.In more detail, the substrate cleaning step of washing the ITO (INDIUM TIN OXIDE) coated glass substrate; A deposition step of depositing a metal thin film on top of one ITO coated glass substrate and a glass thin film on top of the other ITO coated glass substrate; A hydrophilization treatment step of placing the two substrates on which the metal thin film and the glass thin film are deposited in a hydrophilic solution heated to a predetermined temperature for a few minutes to hydrophilize; A drying step of drying the two hydrophilized substrates through the hydrophilization treatment step; An initial direct bonding step of directly bonding the dried substrate; An oven drying step of drying the directly bonded substrate in an oven; Electrostatic thermal bonding is performed by applying a predetermined voltage and heat to the directly bonded substrates to bond the two glass substrates which are not easily bonded.
또한, 도3은 본 발명에 의한 유리-실리콘기판간의 접합부위를 촬영한 사진이고, 도4는 도3을 반으로 절단한 후, 그 단면을 촬영한 단면 주사 전자현미경 사진이며, 도5는 실리콘기판을 식각한 후, 전압을 인가하여 접합한 시료의 주사 현미경 사진으로서 이에 도시한 바와 같이 상기와 같은 공정으로 유리기판과 반도체기판의 사이에는 영구적이며, 강한 접합이 형성됨을 알 수 있다. 이때, 접합을 하고자 하는 기판의 표면이 거칠 경우 유리기판과 실리콘기판간에는 부분적으로 접합되는 경우도 발생하게 된다.In addition, Figure 3 is a photograph of the junction between the glass-silicon substrate according to the present invention, Figure 4 is a cross-sectional scanning electron micrograph photographing the cross-section after cutting Figure 3 in half, Figure 5 is a silicon After etching the substrate, a scanning micrograph of a sample bonded by applying a voltage, as shown therein, can be seen that a permanent, strong bonding is formed between the glass substrate and the semiconductor substrate by the above-described process. In this case, when the surface of the substrate to be bonded is rough, partial bonding may occur between the glass substrate and the silicon substrate.
상기한 바와 같이 본 발명 반도체기판의 정전 열 접합방법은 반도체기판과 유리기판을 친수화처리한 후 접합하여 종래 보다 낮은 온도 및 전압조건에서 강한 접합력과 넓은 접합 면적을 갖도록 함으로써, 제조비용의 절감과 아울러 제품의 안정성 및 신뢰도를 향상시키는 효과가 있다.As described above, in the electrostatic thermal bonding method of the semiconductor substrate of the present invention, the semiconductor substrate and the glass substrate are bonded after being hydrophilized to have a strong bonding force and a large bonding area at a lower temperature and voltage condition than in the prior art, thereby reducing manufacturing costs and In addition, there is an effect of improving the stability and reliability of the product.
Claims (11)
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| US5407856A (en) * | 1991-05-08 | 1995-04-18 | Fraunhofer Gesellschaft Zur Forderung Der Angewandten Forschung | Direct substrate bonding |
| US5413955A (en) * | 1993-12-21 | 1995-05-09 | Delco Electronics Corporation | Method of bonding silicon wafers at temperatures below 500 degrees centigrade for sensor applications |
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| US5407856A (en) * | 1991-05-08 | 1995-04-18 | Fraunhofer Gesellschaft Zur Forderung Der Angewandten Forschung | Direct substrate bonding |
| US5413955A (en) * | 1993-12-21 | 1995-05-09 | Delco Electronics Corporation | Method of bonding silicon wafers at temperatures below 500 degrees centigrade for sensor applications |
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