KR100270450B1 - Multi-carrier modulated pc-cdma system - Google Patents

Abstract

PURPOSE: A frequency multiplexing PC-CDMA(parallel combinatory code-division multiple access) system is provided to reduce the system size and to improve system efficiency by reducing number of correlators and data identifiers. CONSTITUTION: Many data bits are converted to corresponding PN(pseudo noise) codes. The PN codes are mixed with orthogonal frequency signals and transmitted by a transmitter. A receiver identifies the PN codes to restore the original data. A storing unit stores PN code data obtained by mixing the frequency signals. A multiplexer(53) successively decodes the PN code data in code units. A correlator(54) transmits a level signal correlated with the PN code. A data identifier identifies the transmitted data based on the level signal output from the correlator(54).

Description

Frequency Multiplexing PC-CDMA System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplexed PC-CDMA (Parallel Combinatory CDMA) system configured to multiplex a PN code (Pseudo Noise Code) corresponding to a plurality of data bits to a frequency having mutual orthogonality. The present invention relates to a frequency multiplex PC-CDMA system capable of recovering received data through a small number of correlators and data determination means.

Recently, as various communication devices have been wirelessized and digitalized, the time division multiple access method (TDMA) and the frequency division multiple access method (FDMA) have gradually shifted to the code division multiple access method (CDMA). Even in the case of the divisional multiple access method, various types such as DS-CDMA (Direct Sequence CDMA) and PC-CDMA have been developed and commercialized. In particular, the PC-CDMA has attracted attention as a communication method of a mobile communication system such as a cellular system because of the advantage that it can transmit a large amount of information at high speed while minimizing the complexity of the system.

However, in the PC-CDMA system described above, for example, 16 (2 ⁴ ) PN codes are required for transmitting 4 bits of data, and therefore a large amount of PN codes are required for transmitting and receiving data. That is, for example, when 128-bit data is simultaneously transmitted, 256 (16x32) PN codes are required.

Therefore, the structure of the PN code generator is complicated in order to generate a large number of PN codes, thereby limiting the size of the cellular system to which the PC-CDMA scheme is applied, as well as the large number of PN codes. There is a problem that the stability is greatly reduced.

Accordingly, the present inventors have multiplexed PN codes corresponding to a plurality of bits into frequencies having mutual orthogonality, thereby greatly reducing the number of PN codes used in the system and transmitting data at a higher speed. -CDMA system was developed and filed as Korean Patent Application No. 97-13078.

FIG. 1 is a block diagram showing a frequency multiplex PC-CDMA system disclosed in Patent Application No. 97-13078. FIG. 1A shows a transmitter and FIG. 1B shows a receiver. In this configuration, the PN code is mapped in k-bit units while n-bit data is transmitted in parallel.

In Fig. 1A, reference numeral 31 denotes a serial / parallel converter for converting n-bit serial data into parallel data and outputting the same, and 32 (32 _{1 to} 32n) output data from the serial / parallel converter 31. Is a PN code output section for inputting each of k bits and outputting a PN code corresponding to the bit value.

Here, the PN code output units 32 _{1 to} 32 _n output 2 ^k PN codes when the data to be input is k bits, where each PN code output unit 32 _{1 to} 32 n is input data. If the values are the same, the same PN codes are all mapped and output. That is, for example, when data having the same data value is input to each PN code output section 32 ₁ and PN code output section 32n, the PN codes output from the PN code output sections 32 ₁ and 32n are: Set to the same thing.

,… ,

를 믹싱하는 믹서이고, 34는 이 믹서(33)로부터 출력되는 각 주파수신호를 합성하여 출력하는 주파수합성부이다.In the drawing, reference numerals 33 (33 _{1 to} 33n) denote frequencies having mutual orthogonality with respect to respective PN codes output from the PN code output unit 32, that is, COS (2f _c t),

,… ,

Is a mixer for mixing and 34 is a frequency synthesizer for synthesizing and outputting each frequency signal output from the mixer 33.

The frequency signal output from the frequency synthesizer 34 is digitally modulated by PSK (Phase Shift Keying) or QPSK (Quadrature PSK).

,… ,

를 각각 믹싱하는 믹서이고, 42(42₁∼42n)는 이 믹서(41)로부터 입력되는 각 주파수신호에 대하여 각각 소정의 PN코드[PN(1)∼PN(2^K)]를 승산한 후 그 결과치를 적분함으로써 입력되는 PN코드에 상관된 소정의 레벨신호를 출력하는 상관기(Correlator)이다.In FIG. 1B, reference numeral 41 (41 _{1 to} 41n) denotes a frequency signal identical to each of the frequency signals mixed in the transmitting apparatus with respect to the received and demodulated frequency signals, that is, COS (2f _c t),

,… ,

And each mixer for mixing, 42 (42 ₁ ~42n) are then each multiplied by a predetermined PN code [PN (1) ~PN (2 K)] , for each frequency signal input from the mixer 41 that It is a correlator which outputs a predetermined level signal correlated with the input PN code by integrating the resultant value.

In Fig. 1B, reference numeral 43 (43 _{1 to} 43n) corresponds to the determined PN code after determining the PN code transmitted from the transmitting apparatus of Fig. 1A based on the level of the signal input from the correlator 21. A data judging section 44 for outputting K-bit data, 44 is a parallel / serial converting section for converting and outputting parallel data applied from the data judging section 43 into serial data.

In the above configuration, in the transmitter, n-bit data output from the serial / parallel converter 31 is applied to the PN code output unit 32 in units of k bits, respectively, and the PN code output unit 32 receives the input. The PN code corresponding to the data value is output. The PN codes output through these PN code output units 32 are modulated into frequency signals having mutually orthogonality through the mixer 33, respectively, and output.

,… ,

는 예컨대 역 DFT 알고리즘(Inverse Discrete Fourier Transform Algorithm)을 이용하여 DSP(Digital Signal Processor)를 통해 용이하게 실현할 수 있다.Here, a plurality of frequency signals for the frequency modulation, namely COS (2f _c t),

,… ,

For example, the Inverse Discrete Fourier Transform Algorithm (DFT) can be easily realized through a digital signal processor (DSP).

In the receiver shown in FIG. 1B, the same frequency signal is mixed with the frequency signal mixed at the transmitting side through the mixer 41 with respect to the inputted reception signal, and the frequency signals are mutually mixed as described above. Since orthogonality is obtained, only the PN codes mixed with the same frequency signals as those mixed in the mixer 41 are output from each mixer 41.

The PN code output from the mixer 41 is restored to the original data through the correlator 42 and the data determining unit 43 and then output through the parallel / serial conversion unit 44.

That is, in the above configuration, the PN codes output from the respective PN code output units 32 are modulated into mutually orthogonal frequency signals, and at the receiving side, the same frequency signals as those of the frequency signals are mixed again, so that the PN codes of the transmitting side are mixed. The output unit 32 and the correlator 42 on the receiving side are set in a one-to-one correspondence relationship.

Therefore, since the number of PN codes required by the PN code output unit 32 can be greatly reduced, the configuration of the PN code generator (not shown) can be greatly simplified, and the same number as in the conventional method is achieved. In the case of using the PN code, the number of data to be transmitted in parallel can be greatly increased, thereby enabling data transmission to be performed at a higher speed than in the prior art.

By the way, in the above-described invention, in order to restore the original data from the data output from the mixer 41, that is, the PN code data, the correlator 42 and the data decision unit 43 are applied to the output of each mixer 41. This requires a very large number of correlators 42 and data decision units 43.

In addition, such a large number of correlators 42 and data determiners 43 become a major obstacle in reducing the size of a system equipped with the receiver, for example, a portable communication terminal, and also increase the price of the system. .

In particular, this is very unreasonable considering that each of the correlators 42 and the data judge 43 have substantially the same configuration.

Accordingly, the present invention has been made in view of the above circumstances, and can significantly reduce the number of correlators and data decision units used in the reception apparatus of the frequency multiplex PC-CDMA system, thereby improving the system configuration efficiency and lowering the price. The purpose is to provide a frequency multiplexed PC-CDMA system.

Figure 1a and 1b is a block diagram showing a conventional frequency multiplex PC-CDMA system.

Figure 2 is a block diagram showing the configuration of a receiving apparatus of a frequency multiplex PC-CDMA system according to an embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of the correlator 54 in FIG.

Figure 4 is a block diagram showing the configuration of a receiving apparatus of a frequency multiplex PC-CDMA system according to another embodiment of the present invention.

**** Brief description of the main parts of the drawing ****

51: mixer, 52: buffer,

53: multiplexer, 54: correlator,

55: data determination unit, 56: parallel / serial conversion unit,

541-1 to 541-2 ^K : Multiplier.

A frequency multiplexing PC-CDMA system according to a first aspect of the present invention for achieving the above object converts a plurality of data bits into PN codes corresponding to the data values, and converts the converted PN codes into mutually orthogonal frequencies. A frequency multiplexing PC comprising a transmitting device for mixing and transmitting a signal, and a receiving device for mixing a frequency signal having mutual orthogonality with respect to the received signal, and determining the PN code obtained at this time to restore original data. In the CDMA system, the receiving apparatus includes a plurality of storage means for storing PN code data obtained through mixing of the frequency signals, and a multiplexer for sequentially reading and outputting PN code data stored in the storage means in units of code. A correlator for outputting a level signal correlated to a PN code output from the multiplexer, and output from the correlator And data determination means for determining transmission data based on the output level signal.

In addition, the frequency multiplex PC-CDMA system according to the second aspect of the present invention converts a plurality of data bits into PN codes corresponding to the data values, and mixes the converted PN codes into frequency signals having mutual orthogonality. In the frequency multiplexing PC-CDMA system comprising a transmitting device and a receiving device to mix the frequency signal having a mutual orthogonality again to the received signal, and to determine the PN code obtained at this time to restore the original data. The reception apparatus includes a plurality of storage means for storing PN code data obtained through mixing of the frequency signal, and PN code data stored in the corresponding storage means coupled to correspond to a predetermined number of the storage means. At least one or more multiplexers sequentially reading and outputting code units, and coupled to an output of each of the multiplexers At least one correlator for outputting a level signal correlated to a PN code output from the multiplexer, and at least one data determining means coupled to the output of each correlator to determine transmission data based on the level signal output from the correlator; Characterized in that configured to include.

According to the present invention having the above-described configuration, since the PN code data stored in the plurality of storage means is sequentially input to the correlator through the multiplexer to perform data restoration, unlike in the related art, through a small number of correlators and data determination means. Received data can be restored.

Therefore, the number of correlators and data determination means can be greatly reduced, thereby simplifying the configuration of the receiving apparatus and significantly reducing the manufacturing cost thereof.

Further, in the present invention, the number of correlators and data determination means is greatly reduced, so that the power consumption consumed by the circuit unit can be greatly reduced, and thus the use time of the communication terminal employing the receiver can be significantly increased. Will be.

In addition, the receiving apparatus can reduce the size of the device because the configuration of the device can be simplified to reduce the size of the communication terminal.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

2 is a block diagram showing the configuration of a receiving apparatus of a frequency multiplex PC-CDMA system according to an embodiment of the present invention.

,… ,

를 각각 믹싱하게 된다. 상술한 바와 같이 상기 믹서(51)를 통해서 믹싱되는 각 주파수신호는 상호 직교성을 갖게 되므로, 상기 믹서(51)에서 출력되는 데이터는 도 1a에서 믹서(33)로 입력되는 데이터, 즉 각 PN코드 출력부(32)의 출력데이터에 대응하게 된다. 그리고, 상기 믹서(51)에서 출력되는 데이터는 각각 버퍼(52: 52₁∼52n)의 입력으로서 결합되고, 버퍼(52)는 입력되는 데이터, 즉 PN코드 데이터를 순차적으로 저장하게 된다.In the figure, the received signal transmitted and demodulated from the transmitter shown in Fig. 1A is combined as an input of the mixers 51 (51 _{1 to} 51n). In addition, the mixer 51 is a frequency signal that is the same as the frequency signal mixed through the mixer 33 in the transmitting apparatus of FIG. COS (2f _c t),

,… ,

Will be mixed separately. As described above, since each frequency signal mixed through the mixer 51 is orthogonal to each other, the data output from the mixer 51 is data input to the mixer 33 in FIG. 1A, that is, each PN code output. It corresponds to the output data of the unit 32. The data output from the mixer 51 are combined as inputs to the buffers 52: 52 _{1 to} 52n, respectively, and the buffer 52 sequentially stores the input data, that is, PN code data.

In FIG. 2, reference numeral 53 is a multiplexer. The multiplexer 53 reads out the data stored in the buffer 52 in PN code units and outputs the data. For example, in FIG. 1A, when the PN code output from each PN code output unit 32 includes 64 chips, the multiplexer 53 reads data from the buffer 52 in units of 64 chips. At this time, access to the buffer 52 is sequentially performed, for example, from the buffer 52 ₁ to the buffer 52n.

The output of the multiplexer 53 is then combined as an input to the correlator 54, and the correlator 54 multiplies a predetermined PN code with respect to the input data, i. A predetermined level signal correlated with the code is output.

Fig. 3 is a block diagram showing the configuration of the correlator 54, in which PN codes [PN (1), PN (2),... A plurality of multipliers for ^{multiplying, PN (2 K)] (} 541: 541-1~541-2 K) and an integrating circuit (542 for integrating each of the signal output from the multiplier 541: 542-1~ It is configured, including ^K 542-2). Here, the PN codes (PN (1), PN (2),...) Multiplied by the multiplier 541 are used. , PN ( ^2K )] corresponds to the PN code mapped and output from the PN code output unit 32 of FIG. 1A.

On the other hand, in Fig. 2, reference numeral 55 denotes a PN code transmitted from the transmitting apparatus of Fig. 1A based on the level of the signal output from the correlator 54 described above, and then, for example, K bit corresponding to the determined PN code. A data determination unit which outputs data, and 56 is a parallel / serial conversion unit that converts and outputs parallel data applied from the data determination unit 55 to serial data, and parallel / serial with these data determination units 55. The converter 56 has a configuration substantially the same as that shown in Fig. 1B.

,… ,

를 각각 믹싱하게 된다. 따라서, 상기 각 믹서(51)에서는 도 1a의 PN코드 출력부(32)에서 출력되는 PN코드 데이터가 출력되어 버퍼(52)에 각각 입력되게 된다.In the above configuration, when the reception signal is input, the mixer 51 performs predetermined frequency signals, i.e., for the reception signal, respectively. COS (2f _c t),

,… ,

Will be mixed separately. Therefore, in each mixer 51, PN code data output from the PN code output unit 32 of FIG. 1A is output and input to the buffer 52, respectively.

Subsequently, the multiplexer 53 reads the PN codes inputted to the buffer 52 in order, that is, in order from the buffer 52 ₁ to the buffer 52n, and outputs them to the correlator 54, and the correlator 54. In Fig. 3, the predetermined PN codes [PN (1), PN (2),... , PN (2 ^K )] is multiplied and the result data is integrated and output.

As is well known, in the case of a normal PN code, since each PN code is orthogonal to each other, multiplying another PN code by an input PN code ideally sets the result value to "0". When the same PN code is multiplied with the PN code, the result value is set to "1". Therefore, if the PN code data received from the transmitting apparatus side is, for example, PN (1), from the integrating circuit 542-1 coupled with the multiplier 541-1 to which the PN (1) is multiplied in FIG. from the other integrating circuit (542-2~542-2 ^K) on the other hand is a predetermined level value to be output is "0" level is output.

Next, in FIG. 2, the data determination unit 55 determines what PN code data is received from the current transmission apparatus based on the level signal input from the correlator 54, and then initially based on the determined result. The data input to the PN code output unit 32 is de-mapped and output, and the output data is output as original data through the parallel / serial conversion unit 66.

That is, in the above embodiment, since the PN codes input through the plurality of mixers 41 are sequentially input to the correlator 54 through the buffer 52 and the multiplexer 53, data restoration is executed. Through the single correlator 54 and the data determination unit 55, the received data can be restored.

Therefore, the number of correlators 54 and data determination unit 55 can be greatly reduced, thereby simplifying the configuration of the receiver and greatly reducing the manufacturing cost.

Further, in the above embodiment, since the number of correlators 54 and data determination unit 55 is greatly reduced, the power consumption consumed by the circuit unit can be greatly reduced. Considering being adopted in the terminal, this provides the effect of greatly increasing the use time of the communication terminal.

In addition, the device of the embodiment can simplify the device configuration to reduce the size of the device, which in turn provides the effect of reducing the size of the communication terminal.

On the other hand, in the embodiment shown in Fig. 2, since the multiplexer 53 has to sequentially input the PN code data stored in each buffer 52 to the correlator 53, high-speed operation of the multiplexer 53 is required. Therefore, in designing a transmission / reception system, the operation speed of the multiplexer 53 should be taken into consideration, which may cause a problem in that device design becomes difficult.

4 illustrates a receiving apparatus of a frequency multiplex PC-CDMA system according to another embodiment of the present invention in consideration of the above circumstances.

In FIG. 4, the received signals are input to the plurality of mixers 61, and the mixers 61 mix frequency signals having mutual orthogonality with respect to the received received signals as in FIG. The received data output from these mixers 61, that is, PN code data, is sequentially stored in the buffer 62.

In addition, the output of the buffer 63 is coupled as an input of the multiplexer 63, where the multiplexer 63 receives PN code data stored in a predetermined number of buffers 62 as an input, unlike in FIG. . In this case, the number of the buffers 62 coupled to the multiplexer 63 is not specific and is determined according to the performance of the transmission / reception system.

The outputs of the multiplexers 63 are then combined as inputs to the correlator 64, respectively, and the outputs of the correlator 64 are combined as inputs to the data determination unit 65. The outputs of the data determination unit 65 are combined. This parallel / serial conversion section 66 outputs the data as serial data. Of course, in this case, the correlator 64 and the data determination unit 65 have a configuration substantially the same as that in FIG.

In the above configuration, a plurality of multiplexers 63 are coupled to the output terminal of the buffer 62. Therefore, since the multiplexer 63 only needs to input data stored in a specific number of buffers 62, not the entire buffer, when the number of the multiplexers 63 is N, the operation speed is the multiplexer shown in FIG. Compared with 53), it can be set to 1 / N.

That is, in the above embodiment, since the data received from the transmitting apparatus is processed through the multiplexer 63, the correlator 64, and the data determining unit 65, the complexity of the apparatus increases as compared with the configuration shown in FIG. It can be used suitably for a system for transmitting and receiving data at high speed.

In addition, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the technical scope of the present invention.

As described above, according to the present invention, since the number of correlators and data judges used for data restoration in the receiving apparatus can be greatly reduced, the size of the system can be greatly reduced, as well as the efficiency and low cost of the system. I can get angry.

Claims (2)

Transmitter which converts a plurality of data bits into PN codes corresponding to the data values, mixes the converted PN codes into frequency signals having mutual orthogonality, and transmits them, and frequency signals having mutually orthogonality to the received signals. In the frequency multiplex PC-CDMA system, comprising a receiving device configured to mix and to recover the original data by determining the PN code obtained at this time, The receiving device includes storage means for storing PN code data obtained through mixing of the frequency signals; A multiplexer for sequentially reading and outputting PN code data stored in the storage means in units of code; A correlator for outputting a level signal correlated to a PN code output from the multiplexer; And data determination means for determining transmission data based on the level signal output from the correlator. Transmitter which converts a plurality of data bits into PN codes corresponding to the data values, mixes the converted PN codes into frequency signals having mutual orthogonality, and transmits them, and frequency signals having mutually orthogonality to the received signals. In the frequency multiplex PC-CDMA system, comprising a receiving device configured to mix and to recover the original data by determining the PN code obtained at this time, The receiving device includes storage means for storing PN code data obtained through mixing the frequency signals, respectively; At least one or more multiplexers coupled to correspond to a predetermined number of the storage means and sequentially reading and outputting PN code data stored in the corresponding storage means in units of code; At least one correlator coupled to an output of each multiplexer and outputting a level signal correlated to a PN code output from the multiplexer; And at least one data determination means coupled to an output of each correlator and determining transmission data based on a level signal outputted from the correlator.

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