KR100264441B1 - Method and circuit for sampling rate translator in cvsd modulation - Google Patents

Abstract

PURPOSE: A rate conversion circuit in a continuously variable slope delta modulation(CVSD) and method thereof is provided to directly convert a sampling rate of digital data modulated by the CVSD in a digital domain. CONSTITUTION: A CVSD/LPCM converter(201) converts 16kbps of CVSD data to be fed to a modulator into LPCM data. An UP sampling unit(202) performs an up-sampling on the output of the CVSD/LPCM converter(201). An LPCM/CVSD converter(203) converts the LPCM data by the UP sampling unit(202) into 32kbps of CVSD data. A CVSD/LPCM converter(206) converts the 32kbps of CVSD data from the converter(203) into LPCM data. A down sampling unit(205) performs a down-sampling on the LPCM data outputted from the CVSD/LPCM converter(206). An LPCM/CVSD converter(204) converts the down-sampled LPCM output from the DOWN sampling unit(205) into 16kbps of CVSD data.

Description

Speed Conversion Circuit and Method in Continuously Variable Slop Delta Modulator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed conversion circuit in a continuously variable slope delta modulator (hereinafter referred to as " CVSD "), and in particular, a continuous variable for directly converting a sampling rate of digital data modulated by CVSD in a digital domain. The present invention relates to a speed conversion circuit and a method in a slop delta modulator.

The conversion to the CVSD modulation method in the conventional analog area is made in the configuration as shown in the example of Fig. 1. In order to convert to the sampling rate of digital data modulated by the CVSD, the CVSD data of digitized 16Kbps is CVSD / ANA The log converter 101 converts the data into analog, and converts the analog data to 32 Kbps CVSD digital data from the analog / CVSD converter 102. The received CVSD 32 Kbps data is output from the analog to the CVSD / analog converter 104. In the conventional conversion method, the quantization error is accumulated by A / D and D / A conversion repeated several times. Since the distortion is severe and the analog circuits and the digital circuits are mounted at the same position, there is a problem of being affected by electromagnetic waves.

Accordingly, an object of the present invention is to provide a method and a circuit capable of converting CVSD digital data modulated at 16 Kbps or 32 Kbps directly into 32 Kbps or 16 Kbps data in a digital domain, and minimizing the effects of quantization error and electromagnetic waves.

In order to accomplish the above object, the present invention is characterized in that the CVSD is converted to LPCM in the digital domain, and the LPCM is converted into CVSD through an interpolation or decimation process.

1 is a conceptual diagram of speed conversion in a conventional analog region;

2 is a conceptual diagram of continuously variable slop delta sampling rate conversion used in an embodiment of the present invention.

3 is a flow chart used in an embodiment of the invention.

4 is a flow chart for CVSD 16/32 conversion used in an embodiment of the invention.

5 is a flow chart for CVSD 32/16 conversion used in an embodiment of the present invention.

6 is a detailed flowchart of the interpolation process of FIG. 4 used in an embodiment of the present invention.

7 is a detailed flowchart of the decimation process of FIG. 5 used in an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A detailed description of a preferred embodiment of the present invention will now be described with reference to the accompanying drawings. In the following, reference numerals are given to components of each drawing, even though the same components are shown in different drawings. Note that they have the same sign. In describing the present invention, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or a chip designer, and the definitions should be made based on the contents throughout the present specification.

2 is a CVSD sampling rate conversion system diagram according to an embodiment of the present invention.

A CVSD / LPCM converter 201 for converting 16 kbps CVSD data into LPCM data,

An upsampling unit 202 for upsampling the output of the CVSD / LPCM converter 201;

An LPCM / CVSD converter 203 for converting the LPCM data sampled by the upsampling unit 202 into CVSD data of 32 Kbps;

A CVSD / LPCM converter 206 for converting 32 Kbps data of the LPCM / CVSD converter 203 into LPCM data;

A downsampling unit 205 for downsampling the LPCM data output from the CVSD / LPCM converter 206;

The downsampling unit 205 includes an LPCM / CVSD conversion unit 204 for converting down-sampled LPCM output into 16 Kbps CVSD data.

3 is a flow chart for processing the CVSD 32Kbps conversion or CVSD 16Kbps conversion from CVSD 32Kbps referred to an embodiment of the present invention,

Checking the CVSD 32Kbps conversion mode at CVSD 16Kbps or the mode according to the CVSD 16Kbps conversion at CVSD 32Kbps,

Processing the conversion mode according to the CVSD 32Kbps conversion from the CVSD 16Kbps,

In the conversion mode according to the CVSD 16Kbps conversion from the CVSD 32Kbps is composed of a process.

4 is a flow chart for CVSD 32Kbps conversion from CVSD 16Kbps of FIG. 3 according to the present invention,

Reading and decoding the data into the CVSD;

Interpolating the decoded data in the step;

And encoding the interpolation data into CVSD.

5 is a flow chart for CVSD 16Kbps conversion from the CVSD 32Kbps of Figure 3 in accordance with the present invention.

Reading and decoding the data into the CVSD;

Decimating the decoded data in the step;

And encoding the decimated data into CVSD.

FIG. 6 is a flow diagram for the interpolation of FIG.

Reading LPCM data and inserting " 0 "

In this step, FIR filtering the output inserted with "0".

FIG. 7 is a concrete flow diagram for the decimation of FIG. 5.

Reading the LPCM data and performing FIR filtering;

And downsampling the output of the filtered FIR filter.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2 to 7.

It is generally known that it is not easy to implement a system that converts low sampling rate CVSD data directly to high rate CVSD data, since the CVSD modulated and demodulated value tracks the previous signal level and displacement, allowing the new signal level to be converted. In order to solve this problem, the present invention converts 16 Kbps CVSD data into LPCM data in the first CVSD / LPCM converter 201 and then converts the data into LPCM data. By converting the speed to 32 Kbps, the first LPCM / CVSD converter 203 converts the output LPCM data into 32 kbps CVSD data and outputs it. The second LPCM / CVSD conversion unit 204 converts the data into 16 Kbps CVSD data by reducing the speed to 16 Kbps in the unit 205. In the 32 of the up / down sampling units 202 and 205, At 16, the transfer rate from 16 to 32 is supplied by varying the frequency of the clock provided by the clock generator (not shown), and interpolation is performed by inserting "0" between bits for data or decimation by FIR filtering. The transmission speed of the data is converted to the data transmission rate. The specific speeds of the data transmission are shown in FIGS. 4 to 7. FIG. 4 is a flow chart for converting the speed from CVSD 16 to CVSD 32. In FIG. Decode the CVSD in step 4b), interpolate in step 4c, and encode it into CVSD in step 4d. FIG. 5 is a flow chart for converting the speed from CVSD 32 to CVSD 16. The data is read in step 5a. In step 5b, the data is decoded to CVSD, and in step 5c, the data is decoded and coded in step 5d. FIG. 6 is a concrete flow diagram of the interpolation process of FIG. Read and insert "0" and filter by FIR. Figure 7 reads LPCM and filters by FIR downsampling, i.e. when slowing down as above (from CVSD 32kbps to CVSD 16Kbps) for continuous amplitude values. Select one of the two amplitude values obtained through the digital filter (decimation) to obtain CVSD data of low sampling rate. Conversely, when increasing the speed (from CVSD 16Kbps to CVSD 32Kbps), the high value of the sampled amplitude value is obtained. From the sampling rate side, the unsampled amplitude value is left blank between successive amplitude values. To do this, enter "0" (interpolation), and use the amplitude value obtained after passing through the FIR digital filter. Get the data.

As described above, when converting the speed of CVSD data, there is an advantage of minimizing the effects of quantization error and electromagnetic waves generated in the conventional scheme.

Claims (4)

In the speed conversion circuit of a continuously variable slop delta modulator, A CVSD / LPCM converter 201 for converting 16 kbps CVSD data input to the modulator into LPCM data; An upsampling unit 202 for upsampling the output of the CVSD / LPCM converter 201; An LPCM / CVSD converter 203 for converting the LPCM data sampled by the upsampling unit 202 into CVSD data of 32 Kbps; A CVSD / LPCM converter 206 for converting 32 Kbps data of the LPCM / CVSD converter 203 into LPCM data; A downsampling unit 205 for downsampling the LPCM data output from the CVSD / LPCM converter 206; And a LPCM / CVSD conversion unit (204) for converting the down-sampled LPCM output from the down-sampling unit (205) into 16 Kbps CVSD data. In the speed conversion method of a continuously variable slop delta modulator, A detection process of checking a CVSD 32Kbps conversion mode or a mode according to CVSD 16Kbps conversion from CVSD 32Kbps input to the modulator; A first conversion process of processing the conversion mode according to the CVSD 32Kbps conversion from the CVSD 16Kbps, In the CVSD 32Kbps CVSD 16Kbps conversion mode in the conversion mode according to the second conversion process for processing it, characterized in that the speed conversion method in the variable slop delta modulator The method of claim 2, wherein the first conversion process is Reading and decoding the data into the CVSD; Interpolating the decoded data in the step; Encoding the interpolation data by CVSD. The method of claim 2, wherein the second conversion process is Reading the data and decoding the data into a CVSD; Decimating the decoded data in the step; Encoding the decimated data into CVSD.

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