KR100264150B1 - Mobile phone using fractional-n type if/if dual pll ic - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable terminal using a fractional-N type IF / IF dual PL IC. In particular, a first IF reference frequency generator 201 and a second IF generating an IF reference frequency after inputting an oscillation signal A reference frequency generator 206; A first IF N counter 202 for inputting and N-counting the fed back first IF oscillation frequency; A first IF phase detector 203 for comparing the first IF reference frequency with the N counted first IF oscillation frequency; A first fractional accumulator 204 for generating after processing the fractional part of the frequency; A first IF output charge pump 205 for inputting the first IF phase detection signal and the data below the decimal point of the frequency to output a first IF square wave signal that is a real value; A second IF N counter 207 for inputting and N-counting the fed back first IF oscillation frequency; A second IF phase detector 208 for comparing the second IF reference frequency with the N counted second IF oscillation frequency; A second fractional accumulator 209 for generating after processing the fractional part of the frequency; And a second IF output charge pump 210 for outputting a second IF square wave signal which is a real value. The present invention can solve a frequency problem according to domestic and foreign frequency allocation, and the PLL IC Since it is a fractional type, it is possible to divide the local frequency to be generated by the reference frequency and not change the IF frequency even if it is not an integer.

Description

Handheld terminal using Fractional-N type IF / IF Dual PL IC

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lock Loop) (hereinafter referred to as PLL) IC (Integrated Circuit; IC) used in a portable terminal, and more particularly, to generating a reference frequency inside a fractional type PLL IC. Fractional-N type IF / IF that separates parts, lowers the used frequency to intermediate frequency (hereinafter referred to as IF) band, and integrates fractional accumulator so that it can be used in both transmitter and receiver IF. The present invention relates to a portable terminal using a fractional-N-type IC / IF dual PLL IC, which allows a dual PLL IC to be installed inside a portable terminal to solve a frequency problem caused by domestic and international frequency allocation.

The conventional PLL frequency synthesizer includes a first crystal oscillator 10 for outputting an oscillation signal, as shown in FIG. A reference frequency generator 20 for inputting an oscillation signal output from the first crystal oscillator 10 and then outputting a reference frequency; An N counter 30 that inputs the fed back output frequency and counts N and outputs the counted N; A phase detector 40 for comparing a reference frequency output from the reference frequency generator 20 with an N counted frequency at the N counter 30 and then comparing the same; A loop filter 50 for outputting a direct current (DC) voltage after adjusting a constant voltage level by the phase detection signal output from the phase detector 40; And a voltage controlled oscillator (hereinafter referred to as VCO) 60 which outputs an IF oscillation frequency by controlling the voltage by the DC voltage output from the loop filter 50.

That is, the operation of the conventional PLL frequency synthesizer will be described with reference to FIG. 1. First, the first crystal oscillator 10 outputs an oscillation signal to the reference frequency generator 20 and the reference frequency generator ( 20) inputs an oscillation signal output from the first crystal oscillator 10, generates a reference frequency, and outputs the reference frequency to the phase detector 40.

Meanwhile, the N counter 30 inputs the IF oscillation frequency output and fed back from the VCO 60 to N count and outputs the N counter 30 to the phase detector 40, and the phase detector 40 generates the reference frequency. The reference frequency output from the unit 20 and the N counted frequency from the N counter 30 are input and then compared.

In addition, the loop filter 50 adjusts the constant voltage level by the phase detection signal output from the phase detector 40, and then outputs a DC voltage to the VCO 60, and the VCO 60 is the loop filter. The voltage is controlled by the DC voltage output at 50 to finally output the IF oscillation frequency.

However, although the conventional PLL frequency synthesizer has a type that can be used for IF and IF, but it is not a fractional type, it is not a fractional number, so the local frequency to be generated is divided by the reference frequency and becomes a real number having a number of digits after the decimal point. Inevitably, there was a problem that the IF frequency should be changed.

The present invention is to solve the above-mentioned conventional problems, and separate the reference frequency generator inside the fractional PLL IC, lower the use frequency to the IF band, and additionally equipped with a fractional accumulator to be used in both the transmitter and receiver IF By using the fractional-N type IF / IF dual PLL IC integrated into the portable terminal, the fractional-N type IF / IF dual PLL IC can solve the frequency problem caused by domestic and international frequency allocation. The present invention provides a portable terminal.

In order to achieve the above object, the present invention provides a portable terminal using the fractional-N type IF / IF dual PL IC, a second crystal oscillator for outputting an oscillation signal; A fractional-N type IF / IF connected to the signal output terminal of the second crystal oscillator for inputting an oscillation signal output from the second crystal oscillator and outputting a first IF square wave output signal and a second IF square wave output signal. With dual PLL; Connected to a signal output terminal of the fractional-N type IF / IF dual PLL, input a first IF square wave output signal output from the fractional-N type IF / IF dual PLL, and then adjust a constant voltage level to output a DC voltage A receiving loop filter; A receiving side VCO connected to a signal output terminal of the receiving side loop filter and controlling a voltage by a DC voltage output from the receiving side loop filter to output a first IF oscillation frequency; Connected to a signal output terminal of the fractional-N type IF / IF dual PLL, inputs a second IF square wave output signal output from the fractional-N type IF / IF dual PLL, and adjusts a constant voltage level to output a DC voltage A transmit loop filter; A transmitting side VCO connected to a signal output terminal of the transmitting side loop filter and controlling a voltage by a DC voltage output from the transmitting side loop filter to output a second IF oscillation frequency; A first amplifier for inputting and amplifying and receiving the received IF signal; A first band pass filter (hereinafter referred to as a BPF) connected to a signal output terminal of the first amplifier and configured to pass an IF signal amplified by the first amplifier to pass only an IF signal of a desired band; ; A first mixer connected to the signal output terminal of the receiving side VCO and the first BPF, inputting and mixing the first IF oscillation frequency output from the receiving side VCO and the IF signal output from the first BPF, and then outputting the mixed signal; ; A second mixer connected to a signal output terminal of a transmitting side VCO, inputting and mixing a second IF oscillation frequency output from the transmitting side VCO and an IF signal to be transmitted, and outputting a mixed IF signal; A second BPF connected to the signal output terminal of the second mixer unit to input an IF signal mixed through the second mixer unit and pass only the IF signal of a desired band; And a second amplifier connected to the signal output terminal of the second BPF to input, amplify, and output the IF signal output from the second BPF.

1 is a functional block diagram showing the configuration of a conventional PLL frequency synthesizer;

2 is a functional block diagram illustrating a transmitting / receiving terminal of a portable terminal using a fractional-N type IF / IF dual PL IC according to an embodiment of the present invention;

FIG. 3 is a functional block diagram showing the configuration of the fractional-N type IF / IF dual PLL IC in the portable terminal using the fractional-N type IF / IF dual PLC IC shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: second crystal oscillator 200: fractional-N type IF / IF dual PLL

201: first IF reference frequency generator 202: first IF N counter

203: first IF phase detector 204: first fractional accumulator

205: first IF output charge pump 206: second IF reference frequency generator

207: second IF N counter 208: second IF phase detector

209: second fraction accumulator 210: second IF output charge pump

300: receiver loop filter 400: receiver VCO

500: transmit side loop filter 600: transmit side VCO

700: first amplifier 800: first BPF

900: first mixer unit 1000: second mixer unit

1100: second BPF 1200: second amplifying unit

Hereinafter, the above-described contents will be described in detail through an embodiment according to the present invention.

2 and 3, the second crystal oscillator 100 includes a first IF reference frequency generator configured to mount an oscillation signal in the fractional-N type IF / IF dual PLL 200. The first IF reference frequency generator 201 outputted to the 201 and the second IF reference frequency generator 206 and mounted in the fractional-N type IF / IF dual PLL 200 is modified by the second correction. After inputting the oscillation signal output from the oscillator 100 generates a first IF reference frequency.

In addition, the first IF N counter 202 mounted in the fractional-N type IF / IF dual PLL 200 inputs the first IF oscillation frequency output from the receiving side VCO 400 and fed back to N counting. After outputting to the first IF phase detector 203, the first IF phase detector 203 is a first IF reference frequency and the first IF N output from the first IF reference frequency generator 201 The N-counted first IF oscillation frequency is compared through the counter 202, and then a first IF phase detection signal is output to the first IF output charge pump 205.

On the other hand, the first fractional accumulator 204 mounted in the fractional-N type IF / IF dual PLL 200 inputs the N counted first IF oscillation frequency through the first IF N counter 202, After generating the fractional part of the frequency, the first IF output charge pump 205 generates the first IF phase detection signal and the first fractional accumulator 204 output from the first IF phase detector 203. The data after the decimal point of the output frequency is input, and the first IF square wave signal, which is a real value, is output to the receiver loop filter 300.

In addition, the receiving loop filter 300 inputs a first IF square wave output signal, which is a real value output from the fractional-N type IF / IF dual PLL 200, and adjusts a constant voltage level to adjust the DC voltage to the receiving side. Output to the VCO 400, and the receiving side VCO 400 controls the voltage according to the DC voltage output from the receiving side loop filter 300 to set the first IF oscillation frequency to the first mixer 900. Will output

Meanwhile, the first amplifier 700 amplifies the received IF signal and outputs the amplified signal to the first BPF 800, and the first BPF 800 is operated by the first amplifier 700. Inputs the amplified IF signal to pass only the IF signal of the desired band, the first mixer 900 is the first IF oscillation frequency output from the receiving side VCO (400) and the first BPF (800) Input and mix the output IF signal and output.

In addition, the second IF reference frequency generator 206 mounted in the fractional-N type IF / IF dual PLL 200 inputs an oscillation signal output from the second crystal oscillator 100 and then a second IF. The second IF N counter 207 which generates a reference frequency and is mounted in the fractional-N type IF / IF dual PLL 200 is fed back from the transmitting VCO 600 and fed back to the first IF oscillation frequency. N is counted and then output to the second IF phase detector 208.

On the other hand, the second IF phase detector 208 is the second IF reference frequency output from the second IF reference frequency generator 206 and the second IF oscillation counted N through the second IF N counter 207 After comparing the frequencies, the second IF phase detection signal is output to the second IF output charge pump 210, and the second fractional accumulator 209 is N counted through the second IF N counter 208. 2 inputs an IF oscillation frequency, and processes the fractional part of the frequency, and generates the second IF output charge pump 210. The second IF phase charge signal 210 outputs the second IF phase detection signal output from the second IF phase detector 208. The data of the fractional part of the frequency output from the second fractional accumulator 209 is input, and a second IF square wave signal, which is a real value, is output to the transmission-side loop filter 500.

In addition, the transmitting loop filter 500 inputs the second IF square wave output signal output from the second IF output charge pump 210 mounted in the fractional-N type IF / IF dual PLL 200. DC voltage is output to the transmitting side VCO 600 by adjusting the constant voltage level, and the transmitting side VCO 600 controls the voltage by the DC voltage output from the transmitting side loop filter 500 to generate a second IF oscillation. The frequency is output to the second mixer 1000.

Meanwhile, the second mixer 1000 inputs and mixes a second IF oscillation frequency output from the transmitting VCO 600 and an IF signal to be transmitted, and then mixes the mixed IF signal with the second BPF 1100. The second BPF 1100 inputs the IF signal mixed through the second mixer 1000 and passes only the IF signal of a desired band, and the second amplification unit 1200 receives the IF signal. The present embodiment is constructed by inputting and amplifying the IF signal output from the second BPF 1100.

Hereinafter, the operation process of as described above will be described with reference to FIGS. 2 and 3.

First, the second crystal oscillator 100 includes a first IF reference frequency generator 201 and a second IF reference frequency generator (201) mounted with the oscillation signal in the fractional-N type IF / IF dual PLL 200. 206).

In addition, the first IF reference frequency generator 201 mounted in the fractional-N type IF / IF dual PLL 200 inputs an oscillation signal output from the second crystal oscillator 100 and then receives a first IF. Generate a reference frequency.

Meanwhile, the first IF N counter 202 mounted in the fractional-N type IF / IF dual PLL 200 inputs the first IF oscillation frequency output from the receiving side VCO 400 and fed back to N counting. After outputting, the signal is output to the first IF phase detector 203.

In addition, the first IF phase detector 203 may have a first IF reference frequency output from the first IF reference frequency generator 201 and a first IF oscillation N counted through the first IF N counter 202. After comparing the frequencies, the first IF phase detection signal is output to the first IF output charge pump 205.

In addition, the first fractional accumulator 204 mounted in the fractional-N type IF / IF dual PLL 200 inputs an N counted first IF oscillation frequency through the first IF N counter 202. After generating the fractional part of the frequency, the first IF output charge pump 205 generates the first IF phase detection signal and the first fractional accumulator 204 output from the first IF phase detector 203. The data after the decimal point of the output frequency is input, and the first IF square wave signal, which is a real value, is output to the receiver loop filter 300.

Meanwhile, the receiving loop filter 300 inputs a first IF square wave output signal, which is a real value output from the fractional-N type IF / IF dual PLL 200, and adjusts a constant voltage level to adjust the DC voltage to the receiving side. Output to VCO (400).

In addition, the receiving side VCO 400 controls the voltage by the DC voltage output from the receiving loop filter 300 and outputs a first IF oscillation frequency to the first mixer 900.

Meanwhile, the first amplifier 700 amplifies the received IF signal and outputs the amplified signal to the first BPF 800, and the first BPF 800 is operated by the first amplifier 700. Inputs amplified IF signal and passes only IF signal of desired band.

The first mixer 900 inputs and mixes a first IF oscillation frequency output from the receiving side VCO 400 and an IF signal output from the first BPF 800, and then mixes the mixed signals.

In addition, the second IF reference frequency generator 206 mounted in the fractional-N type IF / IF dual PLL 200 inputs an oscillation signal output from the second crystal oscillator 100 and then a second IF. Generate a reference frequency.

On the other hand, the second IF N counter 207 mounted in the fractional-N type IF / IF dual PLL 200 inputs the first IF oscillation frequency output from the transmitting side VCO 600 and fed back to N counting. And output to the second IF phase detector 208.

In addition, the second IF phase detector 208 is the second IF reference frequency output from the second IF reference frequency generator 206 and the second IF oscillation counted N through the second IF N counter 207. After comparing the frequencies, the second IF phase detection signal is output to the second IF output charge pump 210.

In addition, the second fractional accumulator 209 inputs the N-counted second IF oscillation frequency through the second IF N counter 208 to generate after processing the fractional part of the frequency, and generates the second IF. The output charge pump 210 inputs the second IF phase detection signal output from the second IF phase detector 208 and the fractional part data of the frequency output from the second fractional accumulator 209 to generate a real value. 2 outputs an IF square wave signal to the transmitting loop filter 500.

Meanwhile, the transmitting loop filter 500 inputs the second IF square wave output signal output from the second IF output charge pump 210 mounted in the fractional-N type IF / IF dual PLL 200. The DC voltage is output to the transmitting side VCO 600 by adjusting the constant voltage level.

In addition, the transmitting side VCO 600 controls the voltage by the DC voltage output from the transmitting side loop filter 500 and outputs a second IF oscillation frequency to the second mixer 1000.

Meanwhile, the second mixer 1000 inputs and mixes a second IF oscillation frequency output from the transmitting VCO 600 and an IF signal to be transmitted, and then mixes the mixed IF signal with the second BPF 1100. The second BPF 1100 receives the IF signal mixed through the second mixer 1000 and passes only the IF signal of a desired band.

The second amplifier 1200 inputs and amplifies the IF signal output from the second BPF 1100 and outputs the amplified signal.

Therefore, the reference frequency generators 201 and 206 are separated into the transmitter and the receiver in the portable terminal, the frequency used is reduced to the IF band, and the fraction accumulators 204 and 209 are additionally mounted on the transmitter and the receiver. By installing the fractional-N type IF / IF dual PLL IC 200 that is integrally implemented so that both the receiver and the IF can be used, the local frequency to be generated is divided by the reference frequency to become an integer because the PLL IC is a fractional type. You do not need to change the IF frequency even if it is a real number with decimal places.

As described above, the portable terminal using the present invention Fractional-N-type IF / IF Dual PLIC IC separates the reference frequency generator inside the fractional PLL IC, lowers the use frequency to the IF band, and additionally installs a fractional accumulator. By installing the fractional-N type IF / IF dual PLL IC integrated into the portable terminal, which can be used in both the transmitter and receiver IF, the frequency problem due to frequency allocation at home and abroad can be solved. Type, it is possible to divide the local frequency to be generated by the reference frequency and not change the IF frequency even if it is not an integer but has a number of digits after the decimal point. There is an effect that can improve the characteristics.

Claims (2)

A second crystal oscillator for outputting an oscillation signal; A fractional-N type IF / IF connected to the signal output terminal of the second crystal oscillator for inputting an oscillation signal output from the second crystal oscillator and outputting a first IF square wave output signal and a second IF square wave output signal. With dual PLL; Connected to a signal output terminal of the fractional-N type IF / IF dual PLL, input a first IF square wave output signal output from the fractional-N type IF / IF dual PLL, and then adjust a constant voltage level to output a DC voltage A receiving loop filter; A receiving side VCO connected to a signal output terminal of the receiving side loop filter and controlling a voltage by a DC voltage output from the receiving side loop filter to output a first IF oscillation frequency; Connected to a signal output terminal of the fractional-N type IF / IF dual PLL, inputs a second IF square wave output signal output from the fractional-N type IF / IF dual PLL, and adjusts a constant voltage level to output a DC voltage A transmit loop filter; A transmitting side VCO connected to a signal output terminal of the transmitting side loop filter and controlling a voltage by a DC voltage output from the transmitting side loop filter to output a second IF oscillation frequency; A first amplifier for inputting and amplifying and receiving the received IF signal; A first BPF connected to a signal output terminal of the first amplifying unit and inputting an IF signal amplified by the first amplifying unit to pass only an IF signal of a desired band; A first mixer connected to the signal output terminal of the receiving side VCO and the first BPF, inputting and mixing the first IF oscillation frequency output from the receiving side VCO and the IF signal output from the first BPF, and then outputting the mixed signal; ; A second mixer connected to a signal output terminal of a transmitting side VCO, inputting and mixing a second IF oscillation frequency output from the transmitting side VCO and an IF signal to be transmitted, and outputting a mixed IF signal; A second BPF connected to the signal output terminal of the second mixer unit to input an IF signal mixed through the second mixer unit and pass only the IF signal of a desired band; And a second amplifier connected to the signal output terminal of the second BPF to input and amplify the IF signal output from the second BPF, and output the amplified N-IF / IF dual PLC LED. Portable terminal used. 2. The apparatus of claim 1, wherein the fractional-N type IF / IF dual PLL comprises: a first IF reference frequency generator for generating a first IF reference frequency after inputting an oscillation signal output from the second crystal oscillator; A first IF N counter for inputting and counting N first IF oscillation frequencies output from the receiving VCO and fed back; A N counted through the first IF reference frequency and the first IF N counter connected to the signal output terminal of the first IF reference frequency generator and the first IF N counter; A first IF phase detector for comparing a first IF oscillation frequency and outputting a first IF phase detection signal; A first fractional accumulator connected to the signal output terminal of the first IF N counter and inputting a first IF oscillation frequency N-counted through the first IF N counter to process a fractional part of the frequency and generate the fraction; Connected to the signal output terminal of the first IF phase detector and the first fractional accumulator, inputting the first IF phase detection signal output from the first IF phase detector and the fractional part data of the frequency output from the first fractional accumulator; A first IF output charge pump for outputting a real value first IF square wave signal; A second IF reference frequency generator for generating a second IF reference frequency after inputting the oscillation signal output from the second crystal oscillator; A second IF N counter which inputs the first IF oscillation frequency fed back from the transmitting side VCO and counts N and outputs the count; A second counted N through the second IF reference frequency and the second IF N counter connected to the signal output terminal of the second IF reference frequency generator and the second IF N counter; A second IF phase detector for outputting a second IF phase detection signal after comparing the two IF oscillation frequencies; A second fractional accumulator connected to a signal output terminal of the second IF N counter and inputting a second IF oscillation frequency N-counted through the second IF N counter to process a fractional part of the frequency; Is connected to the signal output terminal of the second IF phase detector and the second fractional accumulator, inputs the second IF phase detection signal output from the second IF phase detector and the fractional part data of the frequency output from the second fractional accumulator; And a second IF output charge pump configured to output a second IF square wave signal which is a real value.