KR100261593B1 - Cctv camera - Google Patents

Abstract

PURPOSE: A closed circuit television camera is provided to design an NTSC type camera with two PAL type oscillators to support the PAL type broadcasting as well as NTSC. CONSTITUTION: The closed circuit television camera includes a base clock provider, a driving pulse generator, a color signal clock provider, a synchronous signal generator and a regulating filter. The base clock provider provides one clock out of an NTSC type base clock and a PAL type base clock based on a user selection. The driving pulse generator receives the base clock from the base clock provider, outputs a pulse signal for signal processing and a pulse signal for CCD driving and provides either of a color signal clock of NTSC type and a color signal clock of PAL type. The color signal clock provider provides either one of the color signal clocks of NTSC and PAL types. The synchronous signal generator receives a divided clock output from the driving pulse generator and the color signal clock output from the color signal generator to output a synchronous signal, compares the phases of the divided clock and the color signal clock to output a phase difference signal representing the phase difference. The regulating filter receives the phase difference signal and converts the received signal into a direct voltage signal.

Description

Closed circuit television camera

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a closed circuit television (CCTV) camera. More specifically, the National Television System Committe (NTSC) has a structure of a PAL (Phase Alternating by Line system) method. It's a closed-loop television camera.

In general, closed-loop television cameras include cameras using the NTS method and cameras using the arm method.

In a closed circuit television camera using the NTS method, various clocks and NTSs for converting and outputting a signal of light incident on a solid-state image pickup device (CCD: Charge Coupled Device (CCD)) into an electrical signal are outputted. Each clock in the synchronous system for obtaining the C-type image output is generated by a clock divided at 28.63636 MHz, the base system clock.

The frequency relationship of the basic clock used in the NTC video output is as follows.

The color subcarrier (3.579545 MHz) is 28.63636 MHZ / 8,

Horizontal sync (15.734 KHz) is 28.63636 MHz / 1820,

Vertical sync (59.94 Hz) is 28.63636 MHz / 477750.

As can be seen from the above, the NTS method can generate various pulses necessary for the system by using the base clock of 28.63636 MHz.

On the other hand, the closed-circuit television camera using the arm type uses the basic clock of 28.375 MHz, but this cannot produce a subcarrier (4.43361875 MHz) to produce a color signal. In addition to the system basic clock, a 17.734 MHz color-only clock is used. Since the color-only clock and the basic clock are used simultaneously in one system, a phase comparison circuit is also used separately to match the phases of the two clocks.

Hereinafter, a conventional closed circuit television camera will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram of a conventional NC-type closed circuit television camera, and Fig. 2 is a circuit diagram of the camera.

As shown in Fig. 1 and Fig. 2, a conventional NC-type closed circuit television camera includes a clock supply unit (1) for supplying a 28.63636 MHz clock which is a basic clock; The driving pulse generator 3 which receives the clock supplied from the clock supply unit 1 and outputs a signal processing pulse signal and a CD driving pulse signal, divides the input clock into two and outputs the signal through the signal line 7. )Wow; And a synchronization signal generator 5 for receiving a two-division clock output from the drive pulse generator 3 through the signal line 7 and outputting a synchronization signal.

Here, the clock supply unit 1 is composed of a crystal oscillator X1 generating a clock of 28.63636 MHz and peripheral circuits C1, R1, C2, C3, VC1.

In addition, the horizontal synchronizing signal HD of the synchronizing signals output from the synchronizing signal generator 5 is input to the driving pulse generator 3 via the signal line 11 through the vertical synchronizing signal VD through the signal line 11. do.

The operation of the conventional NT-type closed circuit television camera is as follows.

First, the crystal oscillator X1 of the clock supply unit 1 and its peripheral circuits C1, R1, C2, C3, and VC1 generate a stable basic clock of 28.63636 MHz and output it to the driving pulse generator 3.

The driving pulse generator 3 divides the basic clock supplied from the clock supply unit 1 into two parts and outputs the basic clock to the synchronization signal generator 5 through the signal line 7.

The synchronization signal generator 5 receives a two-division clock, in which the basic clock is divided by two, from the driving pulse generator 3 through the signal line 7 to receive the synchronization signals VD, HD, CBLK, FIELD, CSYNC, and 4FSC. Create and print

At this time, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are output to the driving pulse generator 3 through the respective signal lines 9 and 11.

On the other hand, the driving pulse generator 3 uses the basic clock input from the clock supply unit 1 and the synchronization signals HD and VD input from the synchronization signal generator 5 to perform the signal processing pulse signals XRG and XH1. , XH2, XSUB, XV2, XV1, XSG1, XV3, XSG2, XV4) and CD drive pulse signals (XSHP, XSHD, XSH1, XSH2, CLP1, CLP4) are generated and output.

3 is a block diagram of a conventional arm-type closed loop television camera.

As shown in FIG. 3, the conventional arm-type closed-loop television camera includes a first clock supply unit 13 for supplying a 28.375 MHz clock which is a basic clock; Generates a driving pulse that receives a basic clock supplied from the first clock supply unit 13, outputs a signal processing pulse signal and a CD driving pulse signal, divides the input clock into two and outputs the signal through the signal line 23. Section 15; A second clock supply unit 17 for supplying a 17.734 MHz clock which is a color signal clock; The two-division clock output from the driving pulse generator 15 is input through the signal line 23, the color signal clock is supplied from the second clock supply unit 17, and the synchronization signal is output. The two-division clock and the color signal are output. A synchronization signal generator 19 for comparing a clock and outputting a signal with respect to a phase difference; And a smoothing and filter unit 21 which receives a signal for the phase difference between the two-division clock and the color signal clock output from the synchronization signal generator 19, converts the signal into a DC voltage, and outputs the signal to the second clock supply unit 17. .

Here, of the synchronization signals output from the synchronization signal generator 19, the horizontal synchronization signal HD is transmitted through the signal line 25, and the vertical synchronization signal VD is transferred to the drive pulse generator 15 through the signal line 27. Is entered.

The operation of such a closed arm television camera of the related art is as follows.

First, the first clock supply unit 13 generates a stable basic clock of 28.375 MHz and outputs it to the driving pulse generator 15.

The driving pulse generator 15 divides the basic clock supplied from the first clock supply unit 13 into two parts and outputs the basic clock to the synchronization signal generator 19 through the signal line 23.

On the other hand, since the color signal related synchronization signal cannot be generated using only the base clock, the second clock supply unit 17 supplies the 17.734 MHz clock, which is the color signal clock, to the synchronization signal generator 19.

The synchronization signal generator 19 receives a two-division clock, in which the basic clock is divided by two, from the driving pulse generator 15 through the signal line 23, and receives a color signal clock supplied from the second clock supply unit 15. The phase difference is compared, and a signal for the phase difference as a result of the comparison is output to the smoothing and filter unit 21.

The smoothing and filter unit 21 receives a phase difference signal output from the synchronization signal generator 19, converts the phase difference signal into a corresponding DC signal, and outputs the DC signal to the second clock supply unit 17.

The second clock supply unit 17 receives a DC signal corresponding to a phase difference output from the smoothing and filter unit 21, so that the color signal clock supplied to the synchronization signal generator 19 is in phase with the two-division clock. The phase of the signal is changed and supplied to the synchronization signal generator 19.

The synchronization signal generator 19 receives a color signal clock whose phase is changed by the second clock supply unit 17, receives a two-division clock input from the driving pulse generator 15, and generates and outputs a synchronization signal.

At this time, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are output to the driving pulse generator 15 through the respective signal lines 25 and 27.

On the other hand, the drive pulse generator 15 uses the basic clock input from the first clock supply unit 13 and the synchronization signals HD and VD input from the synchronization signal generator 19 to perform signal processing pulse signals and CC. Generate and output the de-drive pulse signal lamp.

However, as described above, in the conventional closed-loop television camera, since the NTS type camera and the arm type camera have oscillation structures suitable for each camera, the development period and the development cost are increased by developing both cameras at the time of developing each camera. There is a problem.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and by designing the structure using two oscillators, which are arm methods, to the NT type camera, it is possible to support not only the NT method but also the arm method. To provide a closed circuit television camera.

1 is a block diagram of a conventional NT-type closed-loop television camera,

2 is a circuit diagram of a conventional NT-type closed circuit television camera,

3 is a block diagram of a conventional arm-type closed-loop television camera,

4 is a block diagram of a closed circuit television camera according to an embodiment of the present invention;

5A and 5B are circuit diagrams of a closed circuit television camera according to an embodiment of the present invention.

As a means for achieving the above object, the present invention,

Basic clock supply means for supplying one of an NC-type base clock and an arm-based base clock according to a user's selection;

Drive pulse generation means for receiving a base clock supplied from the base clock supply means, outputting a signal processing pulse signal and a CD driving pulse signal, and dividing the base clock to output a divided clock;

Color signal clock supply means for supplying one of an NC-type color signal clock and an arm-type color signal clock according to a user's selection;

A phase difference indicating a phase difference by receiving a divided clock output from the driving pulse generating means, receiving a color signal clock output from the color signal generating means, and outputting a synchronous signal, comparing phases of the divided clock and the color signal clock; Synchronizing signal generating means for outputting a signal;

And a smoothing and filtering means for receiving a phase difference signal output from the synchronization signal generating means, converting the signal into a corresponding DC voltage signal, and outputting the converted DC voltage signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a closed circuit television camera according to an embodiment of the present invention, and FIGS. 5A and 5B are circuit diagrams of the camera.

4 and 5, the closed-loop television camera according to an embodiment of the present invention according to the user's selection of one of the 28.63636 MHz clock of the NC-based base clock and 28.375 MHz clock of the arm-based clock A basic clock supply unit 30 for outputting a clock; Pulse signal for signal processing (XRG, XH1, XH2, XSUB, XV2, XV1, XSG1, XV3, XSG2, XV4) and CD drive pulse signal (XSHP,) by receiving the basic clock supplied from the basic clock supply unit 30 A drive pulse generator 40 for outputting XSHD, XSH1, XSH2, CLP1, and CLP4, and outputting the divided clock generated by dividing the base clock by two through the signal line 80; A color signal clock supply unit 50 for supplying one of an NTS type color signal clock 14.31818 MHz clock and an arm type color signal clock 17.734 MHz clock according to a user's selection; The two-division clock output from the driving pulse generator 40 is input, the color-signal clock output from the color signal clock supply unit 50 is input, and a synchronization signal is output. The signal for the phase difference between the two-division clock and the color signal clock is output. A synchronization signal generator 60 for outputting; It includes a smoothing and filter unit 70 for receiving a signal for the phase difference output from the synchronization signal generator 60, converts it into a corresponding DC voltage signal and outputs it to the color signal clock supply unit 50.

The base clock supply unit 30 according to the embodiment of the present invention may generate a first crystal oscillator (X1) generating a clock of 28.63636 MHz, which is an NTS type clock, and a clock of 28.375 MHz, an arm type base clock, according to a user's selection. ), A second capacitor C2 connected between one terminal of the first crystal oscillator X1 and ground, and a third capacitor C3 connected between the other terminal of the first crystal oscillator X1 and ground. ), A third resistor R3 connected between both terminals of the first crystal oscillator X1, and a first variable capacitor VC1 connected between one terminal of the first crystal oscillator X1 and ground. And both sides of the first crystal oscillator X1 are connected to the driving pulse generator 40.

In addition, the color signal clock supply unit 50 generates a second crystal oscillator (X2) generating a 14.31818 MHz clock, which is an N-S type color signal clock, and a 17.734 MHz clock, which is an arm type color signal clock, according to a user's selection, and a second crystal. The eighth capacitor C8 and the second variable capacitor VC2 connected in parallel between one side terminal of the oscillator X2 and the ground and the positive terminal are grounded, and the negative terminal is output from the smoothing and filter unit 70. A variable capacitor diode VD1 connected to the DC voltage value for the phase difference signal, a ninth capacitor C9 connected between the other terminal of the second crystal oscillator X2 and the variable capacitor diode VD1, The thirteenth resistor R13 connected between both terminals of the second crystal oscillator X2 and the first input terminal are connected to the other terminal of the second crystal oscillator X2, and the second input terminal has a voltage Vcc. ) And the output terminal has a second crystal oscillation The first NAND gate N1 connected to one terminal of the ruler X2, the first input terminal is connected to the output terminal of the first NAND gate N1, and the second input terminal is connected to the voltage Vcc. And a second NAND gate N2 having an output terminal connected to the synchronization signal generator 60.

In addition, the smoothing and filter unit 70 has an inverting terminal connected to the phase difference signal output from the synchronization signal generator 60 through the tenth resistor R10, and the non-inverting terminal is connected between the voltage Vcc and ground. A first operational amplifier OP1 and a first operational amplifier OP1 connected in series and connected between an eighth resistor R8 and a ninth resistor R9 having an output terminal connected to the color signal clock supply unit 50; A fifth capacitor C5 and an eleventh resistor R11 connected in series between the inverting terminal and the output terminal of the second terminal, and the inverting terminal and the output terminal of the first operational amplifier OP1 in parallel. And a sixth capacitor C6 and a twelfth resistor R12.

In addition, when the driving pulse generator 40 operates in the arm manner, the first resistor R1 is selected by the user, and when the driving pulse generator 40 operates in the ANTSI method, the second resistor R2 is selected.

In addition, when the sync signal generator 60 operates in the arm manner, the fifth resistor R5 and the seventh resistor R7 are selected by the user. When the sync signal generator 60 operates in the arm manner, the fourth resistor R4 is operated by the user. And the sixth resistor R6 are selected.

In addition, the horizontal synchronizing signal HD of the synchronizing signals output from the synchronizing signal generator 60 is input to the driving pulse generator 40 through the signal line 100 through the vertical synchronizing signal VD through the signal line 100. do.

With the above configuration, the operation of the closed-loop television camera according to the embodiment of the present invention is as follows.

First, in order to operate the closed-circuit television camera in the NC system, the user causes the first crystal oscillator X1 of the basic clock supply unit 30 to generate a 28.63636 MHz clock, which is the basic clock of the NC system.

In addition, the second crystal oscillator X2 of the color signal clock supply unit 50 generates a 14.31818 MHz clock, which is an NC-based color signal clock.

Next, the second resistor R2, the fourth resistor R4, and the sixth resistor R6 are operable, and the first resistor R1, the fifth resistor R5, and the seventh resistor R7 are Do not work.

In this manner, the closed-loop television camera has a conventional arm-type structure, but operates in an NC-type method.

On the other hand, in order to operate the closed-circuit television camera in the arm manner, the user causes the first crystal oscillator X1 of the basic clock supply unit 30 to generate a 28.375 MHz clock which is an arm type basic clock.

In addition, the second crystal oscillator X2 of the color signal clock supply unit 50 generates a 17.734 MHz clock which is an arm type color signal clock.

Next, the second resistor R2, the fourth resistor R4, and the sixth resistor R6 are not operated, and the first resistor R1, the fifth resistor R5, and the seventh resistor R7 are To work.

This allows the closed loop television camera to operate in an armed fashion.

The operation of such a closed circuit television camera is as follows.

First, the base clock supply unit 30 selects one clock from a 28.63636 MHz clock, which is an NC-type base clock, and a 28.375 MHz clock, an eight-base clock, according to a user's selection. It generates through (C1, R3, C2, C3, VC1) and outputs it to the drive pulse generator 40.

At this time, the first resistor R1 and the second resistor R2 connected to the driving pulse generator 40 operate according to the method selected by the user.

The driving pulse generator 40 divides the basic clock supplied from the basic clock supply unit 30 into two parts and outputs the basic clock to the synchronization signal generator 60 through the signal line 80.

On the other hand, since the color signal-related sync signal cannot be generated using only the basic clock, the color signal clock supply unit 50 is one of the NTS-type color signal clocks, 14.31818 MHz clock and 17.734 MHz clock, according to the method selected by the user. Is generated through the second crystal oscillator X2 and the peripheral circuits C8, C9, R13, R14, R15, VC1, N1, and N2, and is supplied to the synchronization signal generator 60.

Next, the synchronization signal generator 60 receives a two-division clock, in which the basic clock is divided by two, from the driving pulse generator 40 through the signal line 80, and receives the color signal clock supplied from the color signal clock supply unit 50. It receives the input and compares the phase difference, and outputs the signal for the phase difference that is the comparison result to the smoothing and filter unit 70.

In this case, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 connected to the synchronization signal generator 60 may be selected by the user. It works accordingly.

On the other hand, the smoothing and filter unit 70 receives the phase difference signal output from the synchronization signal generator 60 and operates the operational amplifier OP1 based on a reference value determined by the eighth resistor R8 and the ninth resistor R9. ) Converts the phase difference signal inputted to the inverting terminal to the corresponding DC voltage value and outputs the converted DC signal to the color signal clock supply unit 50.

The variable capacitance diode VD1 of the color signal clock supply unit 50 changes the capacitance to a DC voltage value with respect to the phase difference output from the smoothing and filter unit 70, and the second crystal oscillator X2 changes the variable capacitance diode VD1. The clock oscillation changes according to the change of the capacitance, and the phase of the color signal clock is changed so that the phase is equal to the phase of the two-division clock output from the driving pulse generator 40. The color signal clock having the same phase is converted into the synchronization signal generator ( 60).

Next, the synchronization signal generator 60 receives a color signal clock whose phase is changed by the color signal clock supply unit 50, receives a two-division clock input from the driving pulse generator 40, and generates and outputs a synchronization signal. do.

At this time, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are output to the driving pulse generator 40 through the respective signal lines 90 and 100.

On the other hand, the driving pulse generator 40 uses the basic clock input from the basic clock supply unit 30 and the synchronization signals HD and VD input from the synchronization signal generator 60 to perform signal processing pulse signals XRG, XH1, XH2, XSUB, XV2, XV1, XSG1, XV3, XSG2, XV4) and CD drive pulse signals (XSHP, XSHD, XSH1, XSH2, CLP1, CLP4) are generated and output.

As described above, in the embodiment of the present invention, by designing a structure using two oscillators, which are arm methods, to an NC type camera, a closed circuit television camera capable of supporting both an NC type method and an arm method can be provided. have.

Claims (6)

Basic clock supply means for supplying one of an NC-type base clock and an arm-based base clock according to a user's selection; Drive pulse generation means for receiving a base clock supplied from the base clock supply means, outputting a signal processing pulse signal and a CD driving pulse signal, and dividing the base clock to output a divided clock; Color signal clock supply means for supplying one of an NC-type color signal clock and an arm-type color signal clock according to a user's selection; A phase difference indicating a phase difference by receiving a divided clock output from the driving pulse generating means, receiving a color signal clock output from the color signal generating means, and outputting a synchronous signal, comparing phases of the divided clock and the color signal clock; Synchronizing signal generating means for outputting a signal; And a smoothing and filtering means for receiving a phase difference signal output from the synchronizing signal generating means, converting the signal into a corresponding DC voltage signal, and outputting the same. The method of claim 1, The basic clock supply means is connected between a first crystal oscillator for generating one of the clock of the NC type and the basic clock of the arm type, between one terminal of the first crystal oscillator and ground. A second capacitor, a third capacitor connected between the other terminal of the first crystal oscillator and ground, a third resistor connected between both terminals of the first crystal oscillator, and one side of the first crystal oscillator And a first variable capacitor connected between the terminal and the ground, wherein both terminals of the first crystal oscillator are connected to the driving pulse generating means. The method of claim 2, The base clock of the NC system is a 28.63636 MHz clock, the base clock of the arm system is a 28.375 MHz clock, characterized in that the closed circuit television camera. The method of claim 1, The color signal clock supply means is connected in parallel between a second crystal oscillator for generating one clock of the NC-type color signal clock and the eight-color color signal clock, and one terminal of the second crystal oscillator and ground. An eighth capacitor and a second variable capacitor, a variable capacitor diode having a positive terminal grounded and a negative terminal connected to a corresponding DC voltage signal for the phase difference signal outputted from the smoothing and filtering means, and the second capacitor A ninth capacitor connected between the other terminal of the crystal oscillator and the variable capacitance diode, a thirteenth resistor connected between both terminals of the second crystal oscillator, and a first input terminal of the second crystal oscillator Connected to a terminal, a second input terminal is connected to a power supply voltage, and an output terminal is one side of the second crystal oscillator A first NAND gate connected to the terminal, a first input terminal connected to an output terminal of the first NAND gate, a second input terminal connected to a power supply voltage, and an output terminal connected to the synchronization signal generating means A closed loop television camera comprising a second NAND gate. The method of claim 4, wherein The color signal clock of the NTS system is 14.31818 MHz clock, and the color signal clock of the eight system is 17.734 MHz clock. The method of claim 1, The smoothing and filtering means has an inverting terminal connected to the phase difference signal outputted from the synchronization signal generating means through a tenth resistor, a non-inverting terminal connected in series between a power supply voltage and ground, and an output terminal of the color signal. A first operational amplifier connected between an eighth resistor and a ninth resistor connected to a clock supply means, and a fifth capacitor and an eleventh resistor connected in series between an inverting terminal and an output terminal of the first operational amplifier; And a sixth capacitor and a twelfth resistor connected in parallel between the inverting terminal and the output terminal of the first operational amplifier.

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