KR100260045B1 - Heat sink construction for power semiconductor module - Google Patents
Heat sink construction for power semiconductor module Download PDFInfo
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- KR100260045B1 KR100260045B1 KR1019980007497A KR19980007497A KR100260045B1 KR 100260045 B1 KR100260045 B1 KR 100260045B1 KR 1019980007497 A KR1019980007497 A KR 1019980007497A KR 19980007497 A KR19980007497 A KR 19980007497A KR 100260045 B1 KR100260045 B1 KR 100260045B1
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- H—ELECTRICITY
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Abstract
Description
본 발명은 파워 트랜지스터 및 IGBT(Insulated Gate Bipolar Transistor) 등과 같이 많은 전력을 사용하는 소자의 방열판을 개선하여 방열성을 향상하고 접합층의 균열을 방지하는 전력 반도체 모듈의 방열판 구조에 관한 것이다.The present invention relates to a heat sink structure of a power semiconductor module for improving heat dissipation and preventing cracking of a bonding layer by improving a heat sink of a device that uses a lot of power, such as a power transistor and an insulated gate bipolar transistor (IGBT).
일반적으로 파워 트랜지스터 및 IGBT 등과 같이 많은 전력을 스위칭하는 전력 반도체 모듈은 동작시에 많은 열이 발생하게 된다. 이러한 열은 전력 반도체 모듈을 과동작시켜 기기의 오동작에 따른 안전 사고를 초래하거나 내구성 저하에 따른 제품의 수명저하를 유발한다. 그러므로 전력 반도체 모듈은 발생되는 열을 발산하기 위한 방열판을 구비하고 있다.In general, power semiconductor modules that switch a lot of power, such as power transistors and IGBTs, generate a lot of heat during operation. This heat can overpower the power semiconductor module, resulting in a safety accident due to malfunction of the device or a reduction in the life of the product due to reduced durability. Therefore, the power semiconductor module has a heat sink for dissipating generated heat.
도 1은 종래의 전력 반도체 모듈의 접합상태를 나타내는 구성도가 도시된다.1 is a block diagram showing a bonding state of a conventional power semiconductor module.
전력 반도체 모듈은 회로패턴(14)과 칩(15)의 적층체 및 전극단자(16)를 세라믹 기판(12) 상에 접합하고 접합된 칩(15)과 전극단자(16)를 결선한 구성을 지닌다. 열전도성이 좋은 구리 재질을 이용하여 세라믹 기판(12)보다 큰 체적으로 성형한 방열판(11)이 솔더(13)를 이용하여 세라믹 기판(12)의 하부면에 접합됨으로써 적절한 방열이 이루어지도록 한다.The power semiconductor module has a structure in which a laminate of the circuit patterns 14 and the chips 15 and the electrode terminals 16 are bonded on the ceramic substrate 12, and the bonded chips 15 and the electrode terminals 16 are connected. Have The heat dissipation plate 11 formed in a volume larger than that of the ceramic substrate 12 using a copper material having good thermal conductivity is bonded to the lower surface of the ceramic substrate 12 using the solder 13 so that proper heat dissipation is achieved.
그런데 세라믹 기판(12)과 방열판(11)의 적층구조처럼 서로 상이한 열팽창률을 지니는 두 재료를 고온에서 접합함에 있어 솔더(13)가 용해되는 온도 및 젖음성을 나타낼 수 있는 약 300℃ 이상의 온도에서 자유롭게 팽창되었던 각각의 재료가 접합 후 냉각되는 과정에서 수축률의 차이를 보인다.However, when joining two materials having different thermal expansion coefficients at high temperatures, such as the laminated structure of the ceramic substrate 12 and the heat sink 11, at a temperature of about 300 ° C. or more, which may indicate the melting temperature and the wettability of the solder 13. Each of the expanded material exhibits a difference in shrinkage as it cools after bonding.
이로 인해 강도가 약한 동(銅) 재질을 사용한 방열판(11)이 소정의 곡률반경(r)을 지니는 곡면으로 변형되는데, 특히 구속되지 않고 자유로운 상태인 하단부에서 변형이 심화된다. 이와 같이 방열판(11)이 변형되면 시스템 장착시 방열면적이 줄어들어 동작 신뢰성 및 내구성이 저하되는 것은 물론 제조현장에서 이를 보정하기 위한 추가적인 공정이 필요하다.As a result, the heat dissipation plate 11 using a weak strength copper material is deformed into a curved surface having a predetermined radius of curvature r. In particular, the deformation is intensified at the lower end portion, which is not constrained and free. As such, when the heat sink 11 is deformed, the heat dissipation area is reduced when the system is mounted, so that operation reliability and durability are deteriorated, as well as an additional process for correcting this in a manufacturing site is required.
따라서 본 발명은 파워 트랜지스터 및 IGBT 등과 같이 많은 전력을 사용하는 소자의 방열판을 개선하여 방열성을 향상하고 접합층의 균열을 방지하는 전력 반도체 모듈의 방열판 구조를 제공한다.Accordingly, the present invention provides a heat sink structure of a power semiconductor module that improves heat dissipation and prevents cracking of a bonding layer by improving a heat sink of a device that uses a lot of power, such as a power transistor and an IGBT.
도 1은 종래의 전력 반도체 모듈의 접합상태를 나타내는 구성도,1 is a configuration diagram showing a bonding state of a conventional power semiconductor module;
도 2는 본 발명 따른 전력 반도체 모듈의 접합상태를 나타내는 구성도.2 is a block diagram showing a bonding state of a power semiconductor module according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11, 21: 방열판 12, 22: 세라믹 기판11, 21: heat sink 12, 22: ceramic substrate
13, 23: 솔더 14, 24: 회로패턴13, 23: solder 14, 24: circuit pattern
15, 25: 칩 16, 26: 전극단자15, 25: chip 16, 26: electrode terminal
21a: 장방형홈 t: 두께21a: rectangular groove t: thickness
L: 길이 r: 곡률반경L: length r: radius of curvature
이러한 목적을 달성하기 위해 본 발명은 회로패턴(24), 칩(25), 전극단자(26) 등이 접합되는 세라믹 기판(22) 상에 솔더(23)를 이용하여 방열판(21)을 접합한 전력 반도체 모듈에 있어서, 상기 방열판(21)은 중앙 위치에 상기 세라믹 기판(22)이 수용되고 솔더(23)를 이용하여 접합되도록 주변에 비하여 두께가 얇아지는 장방형홈(21a)을 지니는 것을 특징으로 하는 전력 반도체 모듈의 방열판 구조를 제공한다.In order to achieve the above object, the present invention uses a solder 23 on a ceramic substrate 22 to which a circuit pattern 24, a chip 25, an electrode terminal 26, and the like are bonded to the heat sink 21. In the power semiconductor module, the heat dissipation plate 21 has a rectangular groove 21a which is thinner than the periphery so that the ceramic substrate 22 is accommodated at a central position and bonded using the solder 23. It provides a heat sink structure of the power semiconductor module.
이때 상기 회로패턴(24)에서 장방형홈(21a) 부분의 두께는 기계적 강도가 허용하는 최소치로 한다.At this time, the thickness of the rectangular groove 21a portion of the circuit pattern 24 is the minimum value allowed by the mechanical strength.
이하 첨부된 도 2를 참조하여 본 발명의 일실시예에 따른 전력 반도체 모듈의 방열판 구조를 상세히 설명하는 바, 도 2는 본 발명 따른 전력 반도체 모듈의 접합상태를 나타내는 구성도이다.Hereinafter, a heat sink structure of a power semiconductor module according to an embodiment of the present invention will be described in detail with reference to FIG. 2. FIG. 2 is a configuration diagram illustrating a bonding state of a power semiconductor module according to the present invention.
본 발명은 회로패턴(24), 칩(25), 전극단자(26) 등이 접합되는 세라믹 기판(22) 상에 솔더(23)를 이용하여 방열판(21)을 접합한 전력 반도체 모듈에 적용한다. 회로패턴(24), 칩(25), 전극단자(26) 등의 접합 및 결선은 종래와 동일성을 유지하는 것이 가능하다.The present invention is applied to a power semiconductor module in which a heat sink 21 is bonded using a solder 23 on a ceramic substrate 22 to which a circuit pattern 24, a chip 25, an electrode terminal 26, and the like are bonded. . Bonding and wiring of the circuit pattern 24, the chip 25, the electrode terminal 26, and the like can maintain the same as in the prior art.
도 1을 통하여 설명한 방열판(11)의 휨현상은 접합부의 면적이 클수록 심화되는데 종래에는 이를 방지하기 위해 방열판(11)이 휘어지는 반대방향으로 미리 휨을 성형하는 방법이나 접합면적을 줄이기 위해 세라믹 기판(12)을 분할하는 방법을 사용하였다. 그러나 전자의 방법은 솔더(13)를 이용한 접합시 휨을 억제하여 방열성의 저하는 피할 수 있으나 근본적으로 열에 대하여 발생하는 응력을 줄일 수 없어 신뢰성 및 내구성에 대한 대책으로 미흡하다. 후자의 방법은 세라믹 기판(12) 간의 전류 흐름을 위한 연결공정이 추가되고 작업성도 좋지 않다.The warpage phenomenon of the heat dissipation plate 11 described with reference to FIG. 1 is intensified as the area of the joint increases. In order to prevent this, the ceramic substrate 12 may be formed in advance in a direction in which the heat dissipation plate 11 is bent, or to reduce the bonding area. The method of dividing was used. However, the former method can prevent the deterioration of heat dissipation by suppressing warping during soldering using the solder 13, but it is fundamentally insufficient as a measure for reliability and durability because it cannot reduce the stress generated with respect to heat. The latter method adds a connection process for current flow between the ceramic substrates 12 and is poor in workability.
이에 본 발명에 따르면 상기 방열판(21)은 중앙 위치에 상기 세라믹 기판(22)을 수용하기 위한 장방형홈(21a)을 지니도록 성형한다. 장방형홈(21a)은 주변에 비하여 두께가 얇아지도록 하기 위함인데, 세라믹 기판(22)이 장방형홈(21a)에 솔더(23)를 이용하여 접합되도록 하는 점은 종래와 동일하다. 방열판(21)에 장방형홈(21a)을 음각함에 따라 서로 상이한 열팽창률을 지니는 두 재료를 고온에서 접합하는 과정에서 발생하는 스트레스 및 스트레인은 개략적으로 다음의 공식으로 설명할 수 있다.Accordingly, according to the present invention, the heat sink 21 is molded to have a rectangular groove 21a for accommodating the ceramic substrate 22 at a central position. The rectangular grooves 21a are intended to be thinner than the periphery, but the ceramic substrate 22 is bonded to the rectangular grooves 21a by using the solder 23 as in the related art. As the rectangular grooves 21a are engraved on the heat sink 21, stresses and strains generated in the process of joining two materials having different thermal expansion rates at high temperatures can be schematically described by the following formula.
여기에서 α는 재료의 선팽창계수, ΔT는 온도차, r은 곡률반경, E는 탄성계수 F는 변형력, υ는 포아슨비, t는 접합부 두께, L은 접합부 두께이고, 상기한 각각의 첨자 A 및 B는 방열판(21) 및 세라믹 기판(22)을 나타낸다.Where α is the coefficient of linear expansion of the material, ΔT is the temperature difference, r is the radius of curvature, E is the elastic modulus F is the strain, υ is the Poisson's ratio, t is the junction thickness, L is the junction thickness, and the respective subscripts A and B Denotes a heat sink 21 and a ceramic substrate 22.
상기한 공식에서 방열판(21)의 음각된 부분의 두께 tA와 곡률반경 r을 변수로 보고 나머지를 상수로 하면 좌변이 일정해지고 우변의 마지막 항도 상수항으로 된다. 이때 tA를 작아지게 하면 우변의 두 번째 항의 크기가 증가하므로 우변의 첫 번째 항은 그만큼 감소해야 한다. 그러기 위해서는 곡률반경r이 커지므로 변형이 줄어든다. 즉, 방열판(21)의 장방형홈(21a) 부분의 두께 tA를 적절히 줄이면 방열판(21)의 변형을 방지 또는 축소할 수 있다.In the above formula, if the thickness t A and the radius of curvature r of the engraved portion of the heat sink 21 are regarded as variables, the left side becomes constant and the last term of the right side becomes a constant term. If t A is made smaller, the second term on the right side increases, so the first term on the right side should decrease by that much. To do this, the radius of curvature r becomes large, so the deformation is reduced. That is, when the thickness t A of the rectangular groove 21a portion of the heat sink 21 is appropriately reduced, deformation of the heat sink 21 can be prevented or reduced.
이때 상기 회로패턴(24)에서 장방형홈(21a) 부분의 두께는 기계적 강도가 허용하고 열용량에 영향을 주지 않는 최소치로 한다. 상기한 공식에 의하면 tA가 작을수록 휨변형 방지의 측면에서는 유리하나 부피가 줄어들어 열용량이 적어짐에 따른 방열 기능의 약화는 물론 세라믹 기판(22)을 접합하는 과정에서 고온의 솔더(23)에 의해 비틀림 변형이 발생되고 접합후 냉각시 균열되는 문제점을 초래할 수도 있으므로 너무 얇아지지 않도록 한다.At this time, the thickness of the portion of the rectangular groove 21a in the circuit pattern 24 is the minimum value allowed by the mechanical strength and does not affect the heat capacity. According to the above formula, the smaller t A is advantageous in terms of the prevention of warpage deformation, but the volume is reduced, so that the heat dissipation is reduced due to the decrease in the heat capacity. Do not become too thin as torsional deformation may occur and it may cause a problem of cracking during joining and cooling.
장방형홈(21a)의 설계시 공식을 유도하여 두께를 결정하는 것은 복잡하고 정확성도 떨어지므로 다양한 치수로 제작된 다수의 모델을 이용하여 실험으로 최적화하는 것이 바람직하다. 일반적으로 모듈의 내부구조가 복잡화될수록 세라믹 기판(22)의 크기도 커지는데 접합층의 면적이 커짐에 따라 열용량을 증가시키기 위해 방열판(21)의 크기를 증가시킬수록 방열판(21)의 휨은 더 증가한다.Determining the thickness by deriving a formula when designing the rectangular groove 21a is complicated and inferior in accuracy, so it is desirable to optimize the experiment by using a plurality of models manufactured in various dimensions. In general, as the internal structure of the module becomes more complicated, the size of the ceramic substrate 22 also increases, and as the area of the bonding layer increases, the size of the heat sink 21 increases in order to increase the heat capacity. Increases.
이상의 구성 및 작용에 의하여 본 발명에 따른 전력 반도체 모듈의 방열판 구조는 파워 트랜지스터 및 IGBT 등과 같이 많은 전력을 사용하는 소자의 방열판을 개선하여 방열성을 향상하고 접합층의 균열을 방지하는 효과가 있다.The heat sink structure of the power semiconductor module according to the present invention by the above configuration and action has the effect of improving the heat sink of the device using a lot of power, such as power transistor and IGBT to improve heat dissipation and prevent cracking of the bonding layer.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980007497A KR100260045B1 (en) | 1998-03-06 | 1998-03-06 | Heat sink construction for power semiconductor module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980007497A KR100260045B1 (en) | 1998-03-06 | 1998-03-06 | Heat sink construction for power semiconductor module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100833929B1 (en) * | 2001-12-15 | 2008-05-30 | 삼성테크윈 주식회사 | Method for forming cavity on heat spreader of TBGA semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20000050865A (en) * | 1999-01-15 | 2000-08-05 | 전주범 | Aligning Device for attaching LTCCM Module on Heat-Sinc |
| KR100886808B1 (en) * | 2002-02-19 | 2009-03-04 | 페어차일드코리아반도체 주식회사 | Power semiconductor module assembling unit having heat sink |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100833929B1 (en) * | 2001-12-15 | 2008-05-30 | 삼성테크윈 주식회사 | Method for forming cavity on heat spreader of TBGA semiconductor package |
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