KR100258358B1 - The method and apparatus for data coherency of distributed shared memory - Google Patents

Abstract

PURPOSE: A method and apparatus for maintaining a data consistency of a distributed shared memory are provided to manage a local memory distributed to a plurality of nodes which mount a plurality of processors by embodying a local memory directory, and by maintaining a data consistency between local memories mounted in each node. CONSTITUTION: A local memory access address latch detects and stores an address accessed to a local memory. An address latch receives a relevant address from the local memory access address latch, and searches a local memory directory. A directory cache is composed of the 16M number of address.

Description

Method and device for maintaining data consistency in distributed shared memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a symmetric multi-processor (hereinafter, abbreviated as " SMP ") of a distributed shared-memory architecture, and more particularly to a plurality of nodes equipped with a plurality of processors. The present invention relates to a method and apparatus for controlling data coherency of distributed shared memory that maintains the consistency of shared memory mounted in each node by implementing a local memory directory to manage local memory distributed in each node.

In general, SMP systems with distributed shared memory architectures have a single copy of the operating system for each node with multiple processors. This means that the interconnect structure must be applied to maintain consistency in the interconnect between the processor and the memory in the node. In addition, it is a system suitable for developer applications because each node's operating system performs a lot of work in terms of performance or resource utilization by application addition. The SMP architecture provided by each vendor is basically the same, allowing for simple porting of the software.

On the other hand, the disadvantage of the large single node SMP system is that the size and speed of the backplane, and the number of processors that can be mounted depending on the shared system bus is limited.

In order to improve this disadvantage, conventionally, as shown in FIG. 1, an SMP system having a distributed shared memory structure has been implemented.

1 is a structural diagram of an 8-way SMP system of a general distributed shared memory structure. As shown in FIG. 1, each node 100 and 200 supports up to four processors 101 to 104 on a local bus. Distributed memory structure, each having a plurality of memory cards 201 to 204, and each of the processors 101 to 104 and 201 to 204 sharing the memory 120 and 220 through the bus transaction control units 111 and 211. It consists of.

Each of the nodes 100 and 200 configured as described above shares data through an interconnection bus, and PCI bridges 130 and 131 to which an interconnection bus may be connected may be input / output buses (PCI I / O buses). Share it.

On the other hand, the interconnect bus is a standard Scalable Coherent Interconnect (SCI) bus, which is easy to increase system scalability (interconnecting multiple processing nodes).

In addition, the memory 120 and 220 of each node shared by each node may provide data requested from itself or another node through the bus transaction control unit 111 and 211 and the memory control unit 122 and 212. Each node implements a memory directory (not shown) that manages the state of the data, that is, the state of the data changed by the transaction of itself or another node.

This memory directory manages the history of other node's processors with respect to the memory of its own node.

For example, as shown in FIG. 3, when the address of the memory directory is 'A [31: 0]', 4 GB (Giga Byte) can be addressed. In other words, 4G is required when managing the history in byte units. At this time, if the cache line size is 32 bytes, the history management of the memory is performed in 32 byte units.

According to the memory reference, 2 bits are required to classify the state into 'Clean, Shared, Invalid (Dirty)', and thus, 32 MByte memory is required to manage 256 Mbit (Mega bit) (128M * 2bit). do.

However, the SMP system of the distributed shared memory structure according to the related art uses an interconnection bus to connect each node, thereby increasing system scalability, while the bus itself has a narrow transmission width, and pipelining during signal transmission. Because of the point-to-point transmission method, the delay time on the interconnection bus is increased, and online transaction processing (OLTP: On), which is a general application program of the server, is problematic. -Line Transaction Processing) Since the application requires continuous communication and mutual interference between SMP processors, the access to the interconnect bus becomes very frequent, resulting in a performance degradation of the system.

In addition, the memory directory for managing distributed shared memory according to the prior art should use a high-speed memory of at least 10 nsec (nano sec) access time, and must be 1: 1 mapping (1: 1 mapping). Therefore, a large memory capacity is required, and when a memory of up to 64GByte is loaded, a memory directory for managing it requires a large amount of high-speed memory, which consumes a lot of space on the board and is expensive. There was this.

Therefore, the present invention implements the interconnect bus of the distributed shared memory structure as a high speed local bus that transmits signals in a pipelining manner with a wide bus transmission width, and improves the problems of the prior art. Managed local memory directory manages all distributed shared memory only with fast small local memory directory regardless of the capacity of distributed shared memory, thereby maintaining data consistency among local memory distributed in each node It is an object of the present invention to provide a method and an apparatus for controlling data consistency of a shared memory.

Another object of the present invention is to implement a local memory directory that manages each distributed shared memory at high speed and small capacity regardless of the capacity of the distributed shared memory to access the local memory to manage all distributed shared memory, transaction type (Transaction Type) The local memory directory is controlled according to the current state of the local memory directory and the result of snooping a transaction driven to a remote node, thereby maintaining data consistency among the distributed local memories.

1 is a block diagram of an 8-way SMP system of a general distributed shared memory structure,

2 is a data configuration diagram of a conventional local memory directory,

3 is a block diagram of an apparatus for maintaining data consistency of a distributed shared memory according to the present invention;

4 is a diagram illustrating the configuration of data in a local memory directory in FIG. 3;

5A to 5D are flowcharts illustrating a data consistency maintenance process of a distributed shared memory according to the present invention.

<Description of Symbols for Main Parts of Drawings>

111: bus transaction controller 112: memory controller

116: directory control unit 117: local memory directory

Such a data coherency control process of the distributed shared memory to achieve the object of the present invention, when a predetermined processor refers to the local memory in its node in a node consisting of SMP of a distributed shared memory structure equipped with a plurality of processors Detecting a bus transaction and detecting a state of a local memory directory managing the local memory when the bus transaction is a read for write (RAW); A second step of observing a snoop phase after generating a corresponding transaction at a remote node when the local memory directory state is invalid; A third step of receiving the data back from the remote node and supplying the data to the processor when the corresponding data exists as a result of snooping; A fourth step of receiving a corresponding memory state from the remote node if the corresponding data does not exist as a result of snooping; A fifth step of performing a snoop step after generating an invalidation transaction (Invalidation) of the corresponding data in the remote node when the state of the local memory directory is shared; A sixth step of invalidating the corresponding data of the remote node and providing the corresponding data to the processor from the local memory when the corresponding data existing in the remote node is shared as a result of snooping; When the corresponding data does not exist in the far node as a result of snooping, a seventh process of providing the corresponding data existing in the own node to the corresponding processor is performed.

In addition, in order to achieve the object of the present invention, a data coherency control process of another distributed shared memory refers to a local memory in a node of a processor in a node composed of a symmetric multiprocessor of a distributed shared memory structure having a plurality of processors. Detecting a corresponding bus transaction and detecting a local memory directory state managing the local memory when the bus transaction is a simple read for read (RIR) transaction; Delaying a currently driven transaction according to the local memory directory state, generating a simple read transaction at a remote node, and observing a snoop step; A third state in which the data is written back from the remote node and supplied to the corresponding processor when the local memory directory state is invalid and the corresponding data is dirty by a predetermined processor of the remote node as a result of snooping of the local bus of the remote node; Process; A fourth step of receiving a corresponding memory state from the remote node if the corresponding data does not exist as a result of snooping; If the state of the local memory directory is shared and the snoop step observes that the predetermined processor of the remote node is sharing the data, the response period of the transaction that has been postponed after receiving the state of the data from the remote node A fifth step in which the request processor reformates the transaction; When the corresponding data does not exist in the remote node as a result of snooping, the sixth process of providing the corresponding data existing in the own node to the corresponding processor is performed.

In addition, the data coherency control process of the distributed shared memory to achieve the object of the present invention is that a predetermined processor in the node consisting of a symmetric multiprocessor of a distributed shared memory structure equipped with a plurality of processors, the local memory in its own node Detecting a corresponding bus transaction if referred to, and detecting a state of a local memory directory managing the local memory when the bus transaction is an invalidated transaction; A second step of observing a snoop step after running an invalidation transaction on a local bus of a remote node when the local memory directory state is a shared state; A third step of changing the state of the local memory directory to a clean state after receiving the state of the data from the remote node when the specific processor of the remote node has the corresponding data in the shared state as a result of the snoop step observation; As a result of observing the snoop step, if the specific processor of the far node does not have the corresponding data, the fourth process of maintaining the state of the local memory directory after receiving the state of the corresponding data from the far node.

In order to achieve the object of the present invention, a data coherency control process of a distributed shared memory includes a process in which a predetermined processor of a remote node has a local memory in its node in a node composed of a symmetric multiprocessor of a distributed shared memory structure having a plurality of processors. A first step of detecting a corresponding bus transaction when referring to the method; A second step of updating a local memory directory state to an invalid state when the detected transaction is an invalidated transaction; If the detected transaction reads data, the local memory directory state is updated to invalid state if it is a read transaction for writing or shared state if it is a simple read transaction, and then data is read from local memory. 3 courses; If the detected transaction is a write transaction, it is characterized in that the fourth step of updating the local memory directory to the corresponding state.

In order to achieve the object of the present invention, the data coherency control apparatus of distributed shared memory manages the data coherency by managing the history of shared local memory mounted on a plurality of nodes composed of symmetric multiprocessors of a distributed shared memory structure having a plurality of processors. A data coherence control device of a distributed shared memory including a local memory directory for holding a local memory directory and directory control means for controlling the local memory directory, the local memory directory having a local memory access address for detecting and storing an address for accessing a local memory. Latch means; And a directory cache configured to receive a corresponding address from the local memory access address latching means and to latch a search for a local memory directory.

Wherein the directory cache comprises a byte offset of a predetermined bit for byte-by-byte addressing in the cache line; A predetermined bit index address that addresses the address of the directory cache when accessing the directory cache; A tag address for mapping the index address at a predetermined rate; According to the increase in the capacity of the local memory, it is characterized by consisting of a spare address to secure the capacity of the management memory.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a data coherence control device of a distributed shared memory of each node according to the present invention. As shown therein, data or transactions to a local bus and an interconnect bus are controlled by a bus transaction control unit 111. First and second request / responders 113a and 113b, respectively requesting and responding to each other; First and second order queues (IOQ) for storing transactions driven by the local bus and the interconnection bus according to the order of occurrence under the control of the bus transaction controller (BTC) 111. Interface portions 114a and 114b; First and second delay queue interface units 115a and 115b which delay or execute each transaction recorded in the first and second order hold queue interface units 114a under the control of the control unit 111 of the bus transaction. )Wow; A directory controller 116 for controlling history management of the local memory 220 under the control of the bus transaction controller 111; The local memory directory 117 manages the history of the local memory 220 under the control of the directory controller 116 to maintain data consistency.

The local memory directory 117 may include a local memory access address latch for detecting and storing an address for accessing the local memory 220; And a directory cache that receives the corresponding address from the local memory access address latch and latches to search for a local memory directory.

The directory cache further includes bytes offsets (A [4: 0]) for byte-by-byte addressing in cache lines of a second level cache memory in a processor; An index address (A [28: 5]) consisting of 16 Mega addresses (4 MBytes in total), 2 bits per address, addressing the directory cache to indicate memory status (Clean, Shared, Dirty); A tag address Tag addr A [31:29] that maps the index address A [28: 5] in a 1: 8 ratio; As the capacity of the local memory 120 increases, a reserved address A [35:32] for securing the capacity of the management memory is configured.

The operation of the present invention configured as described above will be described in detail with reference to FIGS. 1 to 5D.

First, the present invention implements a local memory directory 117 (directory cache) with only a small amount of fast directories in order to maintain data coherency between distributed memories in an SMP computer system having a distributed shared memory structure.

That is, the local memory directory 117 manages the state of data when local memory in its node is accessed from the processor of the remote node. By managing the memory access history from the remote node in this way, when the processor in its node accesses the local memory, it makes an appropriate response with reference to the stored history.

In order to manage the history of the local memory, the local memory directory is allocated 2 bits per line (32 bytes) of each cache (second level cache memory L2 mounted in the processor), and three states exist.

Here, the three states are first a clean state indicating that the address has not been accessed from the remote node's processor at all, and when the address is accessed for read reference from the remote node's processor, the data of the address is stored. If the shared address indicates that it is shared with the remote node's processor, and the address is accessed for a write reference from the remote node's processor, the data at that address is invalid and only valid for the remote node's processor. There will be an Invalid state indicating there is.

Here, it will be described in more detail with reference to Figure 4 as follows.

There is a local memory access address latch that detects and stores an address that accesses a local memory, and a second stage address latch that is used to retrieve and update a local memory directory 117 by receiving the address from the local memory access address latch. . The directory cache is composed of 16M addresses (4MByte total), 2 bits per address.

If the capacity of the local memory 120 is 4GByte, a high speed memory such as a total RAM of 32MByte is required to implement the directory cache required for the local memory 120. In the present invention, this is implemented as 4MByte. It is.

To this end, as shown in FIG. 4, an address having eight different tag addresses for a specific index address exists.

In the case of accessing the directory cache in the local memory directory 117 implemented as described above, there may be a case where a processor in its node accesses local memory and a processor of a remote node accesses local memory.

First, a case in which a predetermined processor accesses a local memory located in its node will be described in detail with reference to FIG. 5.

FIG. 5A is a flowchart illustrating management of a local memory directory when a read and write bus transaction for writing occurs while a specific processor accesses distributed shared memory in its node. As shown in FIG. Is in a dirty state, and another processor on the same local bus may have this data read by a bus read-for-line transaction or with a dirty cache line when requested by a bus read-for-line transaction. A processor may present its data on a local bus by means of an implicit writeback transaction.

In this case, in the case of a read transaction for writing, only the requested processor takes the corresponding data, and the local memory 120 does not update. On the other hand, when the generated transaction is simply a read-only transaction, the requested processor not only takes the data but also updates the local memory 120. At this time, a write cycle occurs in the local memory.

Also, when a particular processor on a local bus attempts to swap another cache line at the same index address to map a new cache line, if that cache line is dirty, the cache line is first placed by a bus write line transaction. It writes to local memory and then maps a new cache line. At this time, a write cycle occurs in the local memory.

In the two cases of writing to the local memory as described above, the data is not present in the remote node because a particular processor in the node has the relevant data dirty, so the state of the local memory directory is kept without updating. The clean state is maintained.

When a transaction occurring on the local bus is a read for writing and another processor does not have the data in a dirty state, the state of the local memory directory 117 is first checked before memory access.

When the state of the local memory directory 117 is in a clean state, the data is provided to the request processor from the local memory without updating the state of the local memory directory 117.

However, if the state of the local memory directory 117 is invalid, since the corresponding data must be read from the remote node, the current transaction is first deferred. Then, the data is requested to the bus transaction control unit 111 at the far node through the interconnection bus. The bus transaction controller of the far node issues a read transaction for writing to the local bus within the far node and then observes the snoop phase.

When the 'HITM' signal is driven in the snoop step, it means that a specific processor on the remote local bus has the corresponding data dirty. Subsequently, the processor executes the writeback transaction. The control unit receives the writeback data and delivers the data to the bus transaction control unit 111 of its node through the interconnection bus.

The bus transaction control unit 111 that receives data through the interconnection bus performs a response cycle of a transaction that has been postponed on its local bus, and provides the processor to the processor that has issued a read transaction for writing the corresponding data. 120 and the local memory directory 117 are not updated.

On the other hand, when the 'HITM' signal is not driven in the snoop step (Inactive), it means that there is no corresponding data on the local bus of the remote node. Therefore, the remote bus transaction controller controls the bus transaction of the node through the interconnection bus. Will return a response stating that no data was requested.

As such, the bus transaction controller 111 that has received a response that there is no data requested from the remote node performs a response period of a transaction that has been postponed on the local bus of its node to read and write the corresponding data from the local memory 120. It provides the processor that issued the read transaction.

This means that a particular processor of the remote node has an address that matches the index address but has a different tag address in the cache directory of the local memory directory 117, so that the status of the local memory directory 117 is not updated and continues to be invalid. Will be maintained.

If the state of the local memory directory 117 is shared, since the corresponding data is shared with the remote node, the current transaction is postponed first, and then the corresponding data is transferred to the bus transaction controller of the remote node through the interconnection bus. You will be asked to invalidate. The bus transaction controller of the far node issues an invalidation transaction to the local bus in the far node and then observes the snoop phase.

When the 'HIT' signal is driven in the snoop phase, it means that a specific processor on the local bus of the far node has the shared data. Therefore, the bus transaction controller of the far node is connected to the bus transaction controller of the corresponding node through the interconnection bus. 111) to announce the invalidation.

The bus transaction control unit 111 performs a response cycle of a transaction that has been postponed on its node's local bus and provides the processor with the read data for writing the data from local memory. Since is invalidated, the state of the local memory directory 117 is updated to a clean state.

If the 'HIT' signal is not driven in the snoop phase, it means that there is no corresponding data on the local bus of the far node, and the far bus transaction controller does not have the corresponding data in the bus transaction controller 111 of the node through the interconnect bus. Will pass the response.

The bus transaction control unit 111 of the node performs a response cycle of a transaction that has been postponed on the local bus to read the data from the local memory 120 and provide the processor to the read transaction for writing.

This means that the address of the local memory directory 117 remains shared without updating the state of the local memory directory 117 because it means that a particular processor on the remote node has an address that matches the address in the cache directory of the local memory directory 117 but has a different tag address. Will be maintained.

Next, when a node's processor accesses local memory 120 (a specific processor accesses distributed shared memory in its node), a bus transaction for simple reading occurs. With reference to Figure 5b will be described in more detail as follows.

If a transaction occurring on the local bus is a simple read operation and another processor does not have the data in a dirty state, the state of the local memory directory 117 is first checked before the memory access.

When the state of the local memory directory 117 is in a clean state, the corresponding data is provided from the local memory 120 without updating the state of the local memory directory 117.

If the local memory directory 117 is in an invalid state, since the corresponding data must be read from the remote node, the current transaction must be deferred first, and then the bus transaction controller of the remote node through the interconnection bus. You will be asked for that data. The bus transaction controller of the far node issues a simple read transaction to the local bus in the far node and observes the snoop phase.

When the 'HITM' signal is driven in the snoop phase, it means that a particular processor on the local bus of the far node has dirty data, and the processor performs a writeback transaction in succession. The bus transaction control unit of the node receives the write back data and delivers it to the bus transaction control unit 111 of the node through the interconnection bus. After receiving the above data, it executes the response cycle of the delayed transaction on the local bus of the node and provides the data to the processor that issued the simple read transaction. In this case, the local memory 120 of its own node is updated, and the state of the local memory directory 117 is updated to the shared state.

If the 'HITM' signal is not driven in the snoop phase, it means that there is no corresponding data on the local bus of the far node, and the bus transaction controller of the far node is the bus transaction controller 111 of the node through the interconnection bus. Will return a response saying that the data is missing.

The bus transaction control unit 111 receiving the above response performs a response period of a transaction that has been postponed on the local bus of its node, reads the data from the local memory, and provides the processor with the simple read transaction.

This means that the address of the local memory directory 117 is kept invalid because the specific processor of the remote node has the same address in the cache directory of the local memory directory 117 but the tag address is different. Will be maintained.

When the state of the local memory directory 117 is shared, it is necessary to check whether the corresponding data is shared with the remote node. Therefore, first, the current transaction is deferred, and then the bus in the remote node through the interconnection bus. The transaction controller is required to confirm whether the data is shared. The bus transaction controller of the far node generates a transaction for simple reading on the local bus in the far node and observes the snoop phase.

When the 'HIT' signal is driven in the snoop phase, it means that a particular processor on the local bus of the far node has the corresponding data shared, so the bus transaction controller of the far node is connected to the node through the interconnect bus. The bus transaction control unit 111 of the response is shared.

At this time, the bus transaction control unit 111 retries the request processor to perform the transaction again in the response period of the transaction that has been postponed on the local bus of its node.

When the request processor restarts the bus transaction, the bus transaction control unit 111 drives the 'HIT' signal in the snoop phase, thereby informing that the data is being shared and supplying data from the local memory 120 in a response period. . At this time, the state of the local memory directory 117 is not updated and continues to be shared.

If the 'HIT' signal is not driven in the snoop phase, it means that there is no corresponding data on the local bus, and the bus transaction controller of the far node is requested to the bus transaction controller 111 of the node through the interconnection bus. Will return a response. The bus transaction controller 111 receiving the response performs a response cycle of the transaction, which has been postponed on the local bus of its node, to read the corresponding data from the local memory 120 and provide the read transaction to the processor. This means that the index address in the directory cache of the local memory directory 117 matches, but because the tag processor has a different address from a particular processor on the remote node, the state of the local memory directory 117 is not updated and continues to be shared. Will be maintained.

Next, a process of detecting a bus transaction generated when a predetermined processor accesses the local memory 120 of its node, and managing the local memory directory 117 when an invalidation bus transaction occurs, see FIG. 5C. When described in more detail as follows.

When the transaction occurring on the local bus is invalidation, the state of the local memory directory 117 is first checked.

If the state of the local memory directory 117 is in a clean state, it means that the corresponding data is not present in the remote node. Therefore, the local memory directory 117 ends without invalidating a transaction on the local bus of the remote node.

However, if the state of the local memory directory 117 is invalid, a particular processor of the remote node may have an address in the cache directory of the local memory directory 117 that has an identical address but a different tag address. Because it means that there is, the status of the local memory directory 117 is not updated, and the transaction is terminated.

In addition, when the state of the local memory directory 117 is shared, it is necessary to check whether the corresponding data is shared with the remote node. Therefore, the bus transaction controller in the remote node is connected to the local bus in the remote node through the interconnection bus. After generating an invalidation transaction, observe the snoop phase.

When the 'HIT' signal is driven in the snoop phase, it means that a specific processor on the local node's local bus has the data shared, so the bus transaction controller of the remote node can access the node's bus through the interconnect bus. The transaction control unit 111 responds to the sharing. At this time, the bus transaction control unit 111 of the node updates the state of the local memory directory 117 to a clean state because the data shared by the remote node is invalidated.

However, if the 'HIT' signal is not driven in the snoop phase, it means that there is no corresponding data on the local bus of the far node, and the bus transaction controller of the far node is the bus transaction controller 111 of the node through the interconnect bus. ) Is sent a response saying that the data is missing. This means that the address of the local memory directory 117 is shared because a particular processor of the remote node has shared the address of the index in the cache directory of the node's local memory directory 117, but the tag address is different. The transaction is terminated without updating.

Next, a process of detecting a bus transaction generated when a processor of a remote node accesses the local memory 120 of its node and managing the local memory directory 117 according to the corresponding bus transaction will be described with reference to FIG. 5D. It will be described in detail as follows.

If a bus transaction generated in a specific processor of the remote node is an invalidation transaction, it means that the processor in the remote node attempts to update the data read first, thus invalidating the state of the local memory directory 117. Update to.

Also, if the bus transaction type is Write, the bus write line on the local node's local bus in order to replace the data first read and updated by the processor at the remote node with another cache line at the same index address. (Bus Write Line) This is the case when a transaction is executed or an implicit writeback is performed by a simple read request of another processor on a remote local bus.

At this time, the bus transaction control unit 111 of the corresponding node means that the data requested to the corresponding furnace no longer exists in the case of writing by a bus write line transaction on the local bus of the remote node. Therefore, the state of the local memory directory 117 is updated to a clean state. In the case of a write by an implicit writeback transaction caused by a simple read request of another processor on the local bus of the remote node, it means that the corresponding data is shared with the local node. Thus, the state of the local memory directory 117 is shared. Update to the state.

In addition, when an implicit writeback transaction occurs due to a read request for writing to another processor on the local bus of the far node, a cache to cache transfer occurs on the far node. Access does not occur in the local memory 120 of the node, and the state of the local memory directory 117 remains in an invalid state.

In addition, when the bus transaction type is read for writing, since the processor at the far node is ultimately reading to update the data, the corresponding data is provided from the local memory 120 and the local memory directory 117 is provided. The state is updated to invalid state.

In addition, when the bus transaction is a simple read (RFR) transaction, since the processor at the remote node reads the data as read-only, the corresponding data is provided from the local memory 120, and the local memory directory 117 The state is updated to shared state.

As described above, in the SMP system having a distributed shared memory structure, the present invention has a locality of time and space because of its characteristics, and therefore, the probability of generating an address having the same index address but different tag address is very low. By using the method and apparatus for controlling data coherency of distributed shared memory according to the present invention, a directory cache may be implemented with a small amount of high-speed memory regardless of the maximum shared memory capacity, thereby maintaining data consistency among distributed local memories. It has an effect.

Claims (10)

In a node consisting of a symmetric multiprocessor of a distributed shared memory structure having a plurality of processors, a predetermined processor detects a corresponding bus transaction when referring to local memory in its node, and when the bus transaction is a read transaction for writing, Detecting a local memory directory state managing the local memory; A second step of observing a snoop step after generating a corresponding transaction at a remote node when the local memory directory state is invalid; A third step of receiving the data back from the remote node and supplying the data to the processor when the corresponding data exists as a result of snooping; A fourth step of receiving a corresponding memory state from the remote node if the corresponding data does not exist as a result of snooping; A fifth step of performing a snoop step after generating an invalidation transaction of the corresponding data in a remote node when the state of the local memory directory is shared; A sixth step of invalidating the corresponding data of the remote node and providing the corresponding data to the processor from the local memory when the corresponding data existing in the remote node is shared as a result of snooping; And a seventh process of providing the corresponding data existing in the own node to the corresponding processor when the corresponding data does not exist in the remote node as a result of the snooping. The method of claim 1, wherein the fourth process comprises: receiving a result from the remote node when there is no corresponding data on the remote local bus as a result of snooping of the local bus of the remote node; Maintaining the local memory directory state after receiving the result from the remote node, and performing a delayed transaction to provide the corresponding data from the local memory to the processor. . 2. The method of claim 1, wherein the seventh step comprises: receiving a result from the remote node when there is no corresponding data on the remote local bus as a result of snooping of the local bus of the remote node; Performing a response period of a transaction that has been postponed on the local bus of the node after receiving a response from the remote node that there is no corresponding data; According to the response of the transaction, the corresponding data is provided to the processor that generated the transaction from the local memory of its node, and the local memory directory state consists of maintaining the shared state. Way. In a node composed of a symmetric multiprocessor with a distributed shared memory structure having a plurality of processors, when a processor refers to local memory in its node, a corresponding bus transaction is detected and the bus transaction is a simple read of data. Detecting a state of a local memory directory managing the local memory; Delaying a currently driven transaction according to the local memory directory state, generating a simple read transaction at a remote node, and observing a snoop step; A third state in which the data is written back from the remote node and supplied to the corresponding processor when the local memory directory state is invalid and the corresponding data is dirty by a predetermined processor of the remote node as a result of snooping of the local bus of the remote node; Process; A fourth step of receiving a corresponding memory state from the remote node if the corresponding data does not exist as a result of snooping; If the state of the local memory directory is shared and the snoop step observes that the predetermined processor of the remote node is sharing the data, the response period of the transaction that has been postponed after receiving the state of the data from the remote node A fifth step in which the request processor re-executes the transaction; And a sixth process of providing the corresponding data existing in the own node to the corresponding processor when the corresponding data does not exist in the remote node as a result of the snooping. 5. The method of claim 4, wherein the fourth process comprises: receiving a status from the remote node when there is no corresponding data as a result of snooping of the local bus of the remote node; Maintaining the state of the local memory directory as it is after receiving the state from the remote node, and performing the delayed transaction to provide the corresponding data from the local memory to the processor. . 5. The method of claim 4, wherein the sixth step comprises: receiving a result from the remote node when there is no corresponding data on the remote local bus as a result of snooping of the local bus of the remote node; Performing a response period of a transaction that has been postponed on the local bus of the node after receiving a response indicating that there is no corresponding data from the remote node; According to the response of the transaction, the corresponding data is provided to the processor that generated the transaction from the local memory of its node, and the local memory directory state consists of maintaining the shared state. Way. In a node composed of a symmetric multiprocessor of a distributed shared memory structure having a plurality of processors, a predetermined processor detects a corresponding bus transaction when the local memory in the node is referenced, and the local memory when the bus transaction is an invalidated transaction. Detecting a state of a local memory directory to manage a state; A second step of observing a snoop step after running an invalidation transaction on a local bus of a remote node when the local memory directory state is a shared state; A third step of changing the state of the local memory directory to a clean state after receiving the state of the data from the remote node when the specific processor of the remote node has the corresponding data in the shared state as a result of the snoop step observation; If the particular processor of the remote node does not have the corresponding data as a result of the snoop step observation, a fourth process of receiving the state of the data from the remote node and maintaining the state of the local memory directory as it is distributed How to control data consistency in memory. A first step of detecting a corresponding bus transaction when a predetermined processor of a remote node refers to local memory in its node in a node formed of a symmetric multiprocessor of a distributed shared memory structure having a plurality of processors; A second step of updating a local memory directory state to an invalid state when the detected transaction is an invalidated transaction; If the detected transaction reads data, the local memory directory state is updated to invalid state if it is a read transaction for writing or shared state if it is a simple read transaction, and then data is read from local memory. 3 courses; And a fourth process of updating a local memory directory to a corresponding state when the detected transaction is a write transaction. A local memory directory for managing data history by maintaining a history of shared local memory, which is mounted in a plurality of nodes of a symmetric multiprocessor of a distributed shared memory structure having a plurality of processors, and a directory controller for controlling the local memory directory In the data consistency control device of distributed shared memory including: The local memory directory includes a byte offset of a predetermined bit for byte-by-byte addressing in a cache line; A predetermined bit index address that addresses the address of the directory cache when accessing the directory cache; A tag address for mapping the index address at a predetermined rate; And a preliminary address for securing a capacity of a management memory according to an increase in the capacity of the local memory. 10. The apparatus of claim 9, wherein the index address has a size of 4 megabytes and has 8 different tag addresses for each index address.

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